TWI497669B - 形成於半導體基板上之導電凸塊及其製法 - Google Patents

形成於半導體基板上之導電凸塊及其製法 Download PDF

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Publication number
TWI497669B
TWI497669B TW101109805A TW101109805A TWI497669B TW I497669 B TWI497669 B TW I497669B TW 101109805 A TW101109805 A TW 101109805A TW 101109805 A TW101109805 A TW 101109805A TW I497669 B TWI497669 B TW I497669B
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Taiwan
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layer
conductive bump
opening
openings
conductive
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TW101109805A
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TW201340267A (zh
Inventor
簡豐隆
林怡宏
陳宜興
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矽品精密工業股份有限公司
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Priority to TW101109805A priority Critical patent/TWI497669B/zh
Priority to CN201210098106.0A priority patent/CN103325760B/zh
Priority to US13/644,006 priority patent/US8569162B2/en
Publication of TW201340267A publication Critical patent/TW201340267A/zh
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Publication of TWI497669B publication Critical patent/TWI497669B/zh

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Description

形成於半導體基板上之導電凸塊及其製法
本發明係關於導電凸塊及其製法，特別是關於一種形成於半導體基板上之導電凸塊及其製法。
相較於打線接合(Wire Bond)技術，覆晶封裝(Flip Chip Package)之特徵在於半導體晶片與封裝基板間的電性連接係透過銲錫凸塊而非一般之金線。近年來，由於高密度以及高速度之半導體元件需求之增加，同時因應電子產品之體積逐漸縮小的趨勢，將覆晶元件設置於低成本的有機電路板，如：印刷電路板，並以環氧樹脂底膠(Underfill resin)填充於晶片下方以減少矽晶片與有機電路板之間因熱膨脹差異所產生的熱應力，上述之種製法已呈一種趨勢。
如第1A圖所示，半導體晶片1的表面上具有銲墊(electronic pad)100，而封裝基板4亦具有相對應的電性接觸墊40，在該半導體晶片1與封裝基板4之間可以適當地設置銲錫凸塊5或其他導電黏著材料，使該半導體晶片1係以作用面朝下的模式設置於該封裝基板4上，其中，該銲錫凸塊5或導電黏著材料提供該半導體晶片1與該封裝基板4間的電性輸入/輸出(I/O)以及機械性的連接。
於一般覆晶製程中，會於該半導體晶片1之銲墊100上形成導電凸塊13(如第1B圖所示)，且於該封裝基板4之電性接觸墊40上形成預銲錫(圖未示)，以藉由兩凸塊相接而利於半導體晶片1與封裝基板4兩者之對位接合；接著，在足以使該導電凸塊13熔融之回銲(solder reflow)溫度條件下，將導電凸塊13回銲至相對應之封裝基板4之電性接觸墊40上之預銲錫(圖未示)，從而形成銲錫凸塊5。之後，如第1A圖所示，再使用底膠6以實現半導體晶片1與封裝基板4的耦合，以確保半導體晶片1與封裝基板4兩者之電性連接的完整性與可靠性。
習知半導體晶片1之導電凸塊13之製程中，如第1B圖所示，係先於一晶圓10上覆蓋一絕緣層12，以保護該晶圓10表面免受外在環境影響而劣化，且該絕緣層12係外露該些銲墊100，再於該晶圓10上形成一絕緣保護層11，且該絕緣保護層11上形成有開孔110以外露該些銲墊100；接著，形成凸塊底下金屬層(under bump metallization,UBM)131於外露之銲墊100上，再形成銲錫材料134於該凸塊底下金屬層131上以製作出導電凸塊13，並進行切單製程，以將該晶圓10切割為複數個半導體晶片1。
然而，該銲錫材料134所形成之導電凸塊13經回銲後，該導電凸塊13之體積及高度之平均值與公差控制不易；當該導電凸塊13體積平均值偏小時，因錫量不足，容易使銲墊100僅部分沾錫或完全未沾錫，因而形成假銲或空銲，造成信賴性問題。若該導電凸塊13之體積平均值偏大時，容易發生因錫量過多而與鄰近接點造成短路之接點橋接(bridge)現象。
因此，該銲錫材料134所形成之導電凸塊13之體積及高度之公差大，不僅銲錫凸塊5容易產生缺陷，導致電性連接品質不良，且銲錫凸塊5所排列成之柵狀陣列(grid array)容易產生共面性(coplanarity)不良，因而部分銲點形成假銲或空銲而導致產品失效。故該銲錫材料134所形成之導電凸塊13，將使該半導體晶片1難以達到細間距的要求。
有鑑於此，係發展出一種覆晶凸塊技術，如第1C圖所示，係先於該絕緣保護層11之開孔110中之凸塊底下金屬層131上形成銅柱132，再於該銅柱132上形成銲錫材料134，以利用銅材不會於回銲製程中改變形狀之特性，而控制導電凸塊13’的高度與體積，進而控制該銲錫凸塊5之崩潰(collapse)範圍，使該半導體晶片1較易於達到細間距的要求。
惟，隨著電子產品輕薄短小的發展趨勢，該晶圓10上各個I/O之間的間距將越來越接近，而該晶圓10上的導電凸塊13’之尺寸亦逐漸縮小，但該銅柱132係為一剛性結構，而該剛性結構之應力會集中於該凸塊底下金屬層131與絕緣保護層11兩者之交界介面(interface)S上，導致於該凸塊底下金屬層131與絕緣保護層11之交界介面S上容易發生剝落(peeling)，而造成產品可靠度不佳之問題。
因此，如何克服上述習知技術的問題，實已成目前亟欲解決的課題。
鑑於上述習知技術之種種缺失，本發明係提供一種形成於半導體基板上之導電凸塊，該半導體基板上具有複數銲墊及絕緣保護層，其中，該絕緣保護層形成有複數第一開孔，以令該銲墊外露於該對應之第一開孔，該導電凸塊包括：金屬層，係形成於外露於各該第一開孔中之銲墊上；金屬柱，係形成於該金屬層上；以及導電材料，係形成於該金屬柱上；其中，該導電凸塊與該第一開孔的孔壁之間係具有間距。
本發明復提供一種導電凸塊之製法，係包括：形成一絕緣保護層於一具有複數銲墊之半導體基板上；形成複數第一開孔於該絕緣保護層上，以令該銲墊外露於該對應之第一開孔；形成金屬層於該銲墊上；形成金屬柱於該金屬層上；以及形成導電材料於該金屬柱上，以令該金屬層、金屬柱與導電材料作為該導電凸塊，且該導電凸塊與該第一開孔的孔壁之間具有間距。
前述之製法中，其步驟可包括：形成阻層於該絕緣保護層上；形成口徑小於該第一開孔之孔徑的複數開口於該阻層上，且該開口對應該第一開孔，以令該銲墊外露於該開口；形成該導電凸塊於該開口中之銲墊上；以及移除該阻層。
前述之導電凸塊及其製法中，該半導體基板上可具有絕緣層，係形成於具有該銲墊之表面，使該絕緣保護層係形成於該絕緣層上，且該絕緣層具有複數第二開孔，以令該銲墊對應外露於該第二開孔。該導電凸塊與該第二開孔的孔壁之間可具有間距，且該第二開孔之孔徑可小於該第一開孔之孔徑。
本發明又提供一種形成於半導體基板上之導電凸塊，該半導體基板上具有複數銲墊及線路增層結構，該線路增層結構上具有複數電性連接墊及絕緣保護層，該絕緣保護層形成有複數第一開孔，以令該電性連接墊外露於該對應之第一開孔，該導電凸塊包括：金屬層，係形成於外露於該第一開孔中之電性連接墊上；金屬柱，係形成於該金屬層上；導電材料，係形成於該金屬柱上；以及其中，該導電凸塊與該第一開孔的孔壁之間係具有間距。
本發明再提供一種導電凸塊之製法，係包括：形成一具有複數電性連接墊之線路增層結構於一具有複數銲墊之半導體基板上；形成一絕緣保護層於該線路增層結構上；形成複數第一開孔於該絕緣保護層上，以令該電性連接墊外露於該對應之第一開孔；形成金屬層於該電性連接墊上；形成金屬柱於該金屬層上；以及形成導電材料於該金屬柱上，以令該金屬層、金屬柱與導電材料作為該導電凸塊，且該導電凸塊與該第一開孔的孔壁之間具有間距。
前述之製法中，其步驟可包括：形成阻層於該線路增層結構上；形成口徑小於該第一開孔之孔徑的複數開口於該阻層上，且該開口對應該第一開孔，以令該電性連接墊外露於該開口；形成該導電凸塊於該開口中之電性連接墊上；以及移除該阻層。
前述之導電凸塊及其製法中，該線路增層結構可具有設於該半導體基板與銲墊上之至少一介電層、設於該介電層上之線路、及設於該介電層中且電性連接該線路與銲墊之複數導電盲孔，又該電性連接墊設於該最外層之線路上，而該絕緣保護層係形成於該最外層之介電層上。
前述之導電凸塊及其製法中，可包括形成絕緣層於該半導體基板具有該銲墊之表面上，使該線路增層結構係形成於該絕緣層上，且該絕緣層具有複數第二開孔，以令該線路增層結構經該第二開孔電性連接該銲墊。
前述之兩種導電凸塊及其製法態樣中，該金屬柱可為銅柱。
另外，前述之兩種導電凸塊及其製法態樣中，可包括形成阻障層於該金屬柱與該導電材料之間，以作為該導電凸塊之成份。
由上可知，本發明導電凸塊及其製法，主要藉由該導電凸塊與該第一開孔的孔壁之間具有間距，使該金屬層與絕緣保護層之間並無交界介面，故相較於習知技術，本發明有效避免金屬柱之應力集中於不同材質之交界介面上，因而避免導電凸塊發生剝落之現象，以達到提升產品可靠度之目的。
再者，藉由該導電凸塊與該第一開孔的孔壁之間具有間距，使後續覆晶製程中，底膠可流入第一開孔，而增加底膠與該半導體晶片之接觸面積，亦即強化底膠與該絕緣保護層間之結合力，因而可避免半導體晶片發生脫落之問題，以達到提升產品可靠度之目的。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
請參閱第2A至2D圖，係為本發明之導電凸塊之製法之第一實施例之剖面示意圖，所述之導電凸塊2係形成於半導體晶片3上。
如第2A圖所示，形成一絕緣層32於一具有複數銲墊300之半導體基板30上，且該絕緣層32具有複數第二開孔320，以令各該銲墊300對應外露於該第二開孔320。
接著，形成一絕緣保護層31於該絕緣層32上，再形成複數第一開孔310於該絕緣保護層31上且對應各該第二開孔320之位置，以令各該銲墊300對應外露於各該第一開孔310。
於本實施例中，該半導體基板30係為晶圓，而於其他實施例中，該半導體基板30亦可為矽基板或玻璃基板。
再者，形成該銲墊300之材質可為鋁材，且形成該絕緣層32之材質可為氮化矽(SiN)或矽的氧化合物(SiOX )以作為鈍化層(passivation layer)，而形成該絕緣保護層31之材質可為聚亞醯胺(Polyimide,PI)、苯環丁烯(Benezocy-clobutene,BCB)或聚苯噁唑(Polybenzoxazole,PBO)。
又，該第二開孔320之孔徑r小於該第一開孔310之孔徑R。
另外，因於各該銲墊300上所進行之製程相同，故圖式中僅以單一銲墊300作表示。
如第2B圖所示，形成一金屬層21於該絕緣保護層31與各該銲墊300上，再形成一光阻層33於該金屬層21上。
接著，藉由曝光、顯影製程，形成複數開口330於該光阻層33上，且各該開口330對應該第一及第二開孔310,320之位置，以令各該銲墊300上之金屬層21外露於各該開口330。
於本實施例中，該開口330之口徑t小於該第一及第二開孔310,320之孔徑R,r。
再者，該金屬層21係作為後述電鍍金屬材料所需之電流傳導路徑，且形成該金屬層21之材質可為鈦/銅(Ti/Cu)或鈦/鎢/銅(Ti/W/Cu)。
如第2C圖所示，電鍍形成一金屬柱22於各該開口330中之金屬層21上，再形成一阻障層(barrier layer)23於各該金屬柱22上。接著，形成一如銲錫材料之導電材料24於各該阻障層23上。
於本實施例中，該金屬層21亦可作為凸塊底下金屬層(under bump metallization,UBM)，且該金屬柱22係為銅柱，而形成該阻障層23之材質可為鎳(Ni)、鈦/鎢(Ti/W)或鎳釩(Ni/V)。
如第2D圖所示，移除該光阻層33及其下之金屬層21，以令該金屬層21、金屬柱22、阻障層23與導電材料24作為導電凸塊2，且令該導電凸塊2與該第一及第二開孔310,320的孔壁之間具有間距D,d，亦即該導電凸塊2之寬度w小於該第一及第二開孔310,320之孔徑R,r。
接著，經由切單至製程，以形成具有該導電凸塊2之半導體晶片3。
如第2E圖所示，於後續製程中，經回銲該導電凸塊2，使該導電材料24覆晶結合一封裝基板(圖未示)。
本發明導電凸塊2之製法，主要藉由該導電凸塊2與該第一及第二開孔310,320的孔壁之間具有間距D,d，亦即該導電凸塊2未接觸該絕緣保護層31與絕緣層32，使該金屬層21與該絕緣保護層31(及該絕緣層32)之間並無交界介面(interface)，故該金屬柱22之應力將集中於金屬材之銲墊300與金屬層21上，而不會集中於不同材質(非金屬材)之絕緣保護層31(及該絕緣層32)上，因而可避免因該金屬柱22之應力集中於不同材質之交界介面上而導致該導電凸塊2剝落之問題。
再者，藉由該第一及第二開孔310,320完全露出該導電凸塊2，且該第二開孔320之孔徑r小於該第一開孔310之孔徑R，以形成階梯孔洞，使後續覆晶製程的形成底膠(圖未示)之步驟中，底膠可流入階梯孔洞，而增加底膠與該半導體晶片3之接觸面積，亦即強化底膠與該絕緣保護層31間之結合力，以避免該半導體晶片3發生脫落之問題。
基於上述優點，將使封裝基板(圖略)與半導體晶片3覆晶相接合所構成之封裝件(圖略)中，所形成之電性接點更能夠承受該封裝基板與該半導體晶片3間所產生之應力，而使該封裝件具有更佳的可靠度。
因此，本發明復提供一種形成於半導體基板30上之導電凸塊2，該半導體基板30上具有銲墊300及絕緣保護層31，其中，該絕緣保護層31形成有第一開孔310，以令該銲墊300外露於該第一開孔310，而該導電凸塊2係設於該第一開孔310中之銲墊300上。
所述之導電凸塊2之寬度w小於該第一開孔310之孔徑R，使該導電凸塊2與該第一開孔310的孔壁之間係具有間距D，且該導電凸塊2係包括：形成於該銲墊300上之金屬層21、形成於該金屬層21上之金屬柱22、形成於該金屬柱22上之阻障層23、以及形成於該阻障層23上之導電材料24。
所述之金屬柱22係為銅柱。
另外，該絕緣保護層31與該半導體基板30之間復形成有絕緣層32，且該絕緣層32具有第二開孔320，以令該銲墊300外露於該第二開孔320；又該第二開孔320之孔徑r小於該第一開孔310之孔徑R，且該第二開孔320之孔徑r大於該導電凸塊2之寬度w，使該導電凸塊2與該第二開孔320的孔壁之間亦具有間距d，如第2D圖所示。
請參閱第3A至3D圖，係為本發明之導電凸塊2之製法之第二實施例之剖面示意圖。本實施例與第一實施例之差異僅在於半導體晶片3’之結構，其他相關製程均大致相同，故不再贅述。
如第3A圖所示，提供一具有至少一銲墊300之半導體基板30，且形成一絕緣層32於該半導體基板30上，該絕緣層32具有第二開孔320，以外露各該銲墊300。
接著，形成一線路增層結構34於該絕緣層32及銲墊300上，該線路增層結構34具有設於該絕緣層32與銲墊300上之至少一介電層340、設於該介電層340上之線路341、及設於該介電層340中且電性連接該線路341之複數導電盲孔342，該導電盲孔342係經該第二開孔320電性連接該銲墊300，又該最外層之線路341具有電性連接墊301。
於本實施例中，形成該銲墊300之材質可為鋁材，且形成該介電層340之材質可為聚亞醯胺(Polyimide,PI)、苯並環丁烯(Benezocy-clobutene,BCB)或聚苯噁唑(Polybenzoxazole,PBO)，而形成該線路341之材質可為鈦/銅(Ti/Cu)或鈦/鎢/銅(Ti/W/Cu)。
再者，有關電性連接墊301之數量與線路增層結構34之層數並無特別限制。
又，因於各該電性連接墊301上所進行之導電凸塊製程相同，故圖式中僅以單一電性連接墊301作表示。
如第3B圖所示，形成一絕緣保護層31於於該最外層之介電層340上，再形成複數第一開孔310於該絕緣保護層31上，以令各該電性連接墊301外露於各該第一開孔310。
如第3C圖所示，形成一金屬層21於該絕緣保護層31與各該電性連接墊301上，再形成一光阻層33於該金屬層21上。
接著，形成複數開口330於該光阻層33上，且各該開口330對應該第一開孔310之位置，以令各該電性連接墊301上之金屬層21外露於各該開口330。
最後，藉由金屬層21電鍍形成一導電凸塊2於各該開口330中之電性連接墊301上。
如第3D圖所示，移除該光阻層33及其下之金屬層21，令該導電凸塊2與該第一開孔310的孔壁之間具有間距D，亦即該導電凸塊2之寬度w小於該第一開孔310之孔徑R。
之後，經由切單至製程，以形成具有該導電凸塊2之半導體晶片3’。
因此，本發明復提供一種形成於半導體基板30上之導電凸塊2，該半導體基板30上具有銲墊300及線路增層結構34，該線路增層結構34上具有電性連接墊301及絕緣保護層31，該絕緣保護層31形成有第一開孔310，以令該電性連接墊301外露於該第一開孔310，而該導電凸塊2係設於該第一開孔310中之電性連接墊301上。
所述之導電凸塊2之寬度w小於該第一開孔310之孔徑R，使該導電凸塊2與該第一開孔310的孔壁之間係具有間距D，且該導電凸塊2係包括：形成於該電性連接墊301上之金屬層21、形成於該金屬層21上之金屬柱22、形成於該金屬柱22上之阻障層23、以及形成於該阻障層23上之導電材料24。
所述之金屬柱22係為銅柱。
所述之線路增層結構34具有至少一設於該半導體基板30與銲墊300上之介電層340、設於該介電層340上之線路341、及設於該介電層340中且電性連接該線路341與銲墊300之導電盲孔342。
所述之絕緣保護層31係形成於該最外層之介電層340上，且最外層之線路341具有該電性連接墊301。
於一實施例中，該線路增層結構34與該半導體基板30之間復形成有絕緣層32，且該絕緣層32具有第二開孔320，以令該導電盲孔342經該第二開孔320電性連接該銲墊300。
綜上所述，本發明之導電凸塊及其製法，係藉由該導電凸塊與該第一開孔的孔壁之間具有間距，使該金屬層與絕緣保護層之間並無交界介面，故有效避免金屬柱之應力集中於不同材質之交界介面上，因而避免導電凸塊發生剝落之現象，以達到提升產品可靠度之目的。
再者，藉由該第一開孔(及第二開孔)完全露出該導電凸塊(於第一實施例中，該第二開孔之孔徑小於該第一開孔之孔徑)，使後續覆晶製程中，底膠可流入第一開孔(及與第二開孔)，而增加底膠與該半導體晶片之接觸面積，亦即強化底膠與該絕緣保護層間之結合力，因而可避免半導體晶片發生脫落之問題，以達到提升產品可靠度之目的。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
1,3,3’．．．半導體晶片
10．．．晶圓
100,300．．．銲墊
11,31．．．絕緣保護層
110．．．開孔
12,32．．．絕緣層
13,13’,2．．．導電凸塊
131．．．凸塊底下金屬層
132．．．銅柱
134．．．銲錫材料
21．．．金屬層
22．．．金屬柱
23．．．阻障層
24．．．導電材料
30．．．半導體基板
301．．．電性連接墊
310．．．第一開孔
320．．．第二開孔
33．．．光阻層
330．．．開口
34．．．線路增層結構
340．．．介電層
341．．．線路
342．．．導電盲孔
4．．．封裝基板
40．．．電性接觸墊
5．．．銲錫凸塊
6．．．底膠
R,r．．．孔徑
t．．．口徑
w．．．寬度
D,d．．．間距
S．．．交界介面
第1A圖係為習知覆晶式封裝結構之剖面示意圖；
第1B及1C圖係為習知具有導電凸塊之半導體晶片之不同態樣之剖面示意圖；
第2A至2E圖係為本發明之導電凸塊之製法之第一實施例之剖面示意圖；以及
第3A至3D圖係為本發明之導電凸塊之製法之第二實施例之剖面示意圖。
2．．．導電凸塊
21．．．金屬層
22．．．金屬柱
23．．．阻障層
24．．．導電材料
3．．．半導體晶片
30．．．半導體基板
300．．．銲墊
31．．．絕緣保護層
310．．．第一開孔
32．．．絕緣層
320．．．第二開孔
D,d．．．間距
R,r．．．孔徑
w．．．寬度

Claims (18)

  1. 一種形成於半導體基板上之導電凸塊，該半導體基板上具有複數銲墊及絕緣保護層，其中，該絕緣保護層形成有複數第一開孔，以令該銲墊外露於該對應之第一開孔，該導電凸塊包括：金屬層，係形成於外露於各該第一開孔中之銲墊上；金屬柱，係形成於該金屬層上；導電材料，係形成於該金屬柱上；以及其中，該導電凸塊與該第一開孔的孔壁之間係具有間距，以外露出該銲墊之部分表面。
  2. 如申請專利範圍第1項所述之導電凸塊，其中，該半導體基板上復具有絕緣層，係形成於具有該銲墊之表面，使該絕緣保護層係形成於該絕緣層上，且該絕緣層具有複數第二開孔，以令該銲墊對應外露於該第二開孔。
  3. 如申請專利範圍第2項所述之導電凸塊，其中，該導電凸塊與該第二開孔的孔壁之間具有間距。
  4. 如申請專利範圍第2或3項所述之導電凸塊，其中，該第二開孔之孔徑小於該第一開孔之孔徑。
  5. 一種形成於半導體基板上之導電凸塊，該半導體基板上具有複數銲墊及線路增層結構，其中，該線路增層結構具有設於該半導體基板與銲墊上之至少一介電層、設於該介電層上之線路、及設於該介電層中且電 性連接該線路與銲墊之複數導電盲孔，又該電性連接墊設於該最外層之線路上，而該絕緣保護層係形成於該最外層之介電層上，該線路增層結構上具有複數電性連接墊及絕緣保護層，該絕緣保護層形成有複數第一開孔，以令該電性連接墊外露於該對應之第一開孔，該導電凸塊包括：金屬層，係形成於外露於該第一開孔中之電性連接墊上；金屬柱，係形成於該金屬層上；導電材料，係形成於該金屬柱上；以及其中，該導電凸塊與該第一開孔的孔壁之間係具有間距，以外露出該電性連接墊之部分表面。
  6. 如申請專利範圍第5項所述之導電凸塊，其中，該半導體基板上具有絕緣層，係形成於具有該銲墊之表面，使該線路增層結構係形成於該絕緣層上，且該絕緣層具有複數第二開孔，以令該線路增層結構經該第二開孔電性連接該銲墊。
  7. 如申請專利範圍第1或5項所述之導電凸塊，其中，該金屬柱係為銅柱。
  8. 如申請專利範圍第1或5項所述之導電凸塊，復包括阻障層，係形成於該金屬柱與該導電材料之間。
  9. 一種導電凸塊之製法，係包括：形成一絕緣保護層於一具有複數銲墊之半導體基板上； 形成複數第一開孔於該絕緣保護層上，以令該銲墊外露於該對應之第一開孔；形成金屬層於該銲墊上；形成金屬柱於該金屬層上；以及形成導電材料於該金屬柱上，以令該金屬層、金屬柱與導電材料作為該導電凸塊，且該導電凸塊與該第一開孔的孔壁之間具有間距，以外露出該銲墊之部分表面。
  10. 如申請專利範圍第9項所述之導電凸塊之製法，復包括：形成阻層於該絕緣保護層上；形成口徑小於該第一開孔之孔徑的複數開口於該阻層上，且該開口對應該第一開孔，以令該銲墊外露於該開口；形成該導電凸塊於該開口中之銲墊上；以及移除該阻層。
  11. 如申請專利範圍第9項所述之導電凸塊之製法，復包括形成絕緣層於該半導體基板具有該銲墊之表面上，使該絕緣保護層係形成於該絕緣層上，且該絕緣層具有複數第二開孔，以令該銲墊對應外露於該第二開孔。
  12. 如申請專利範圍第11項所述之導電凸塊之製法，其中，該第二開孔之孔徑小於該第一開孔之孔徑。
  13. 如申請專利範圍第12項所述之導電凸塊之製法，其中，該導電凸塊與該第二開孔的孔壁之間具有間距。
  14. 一種導電凸塊之製法，係包括：形成一具有複數電性連接墊之線路增層結構於一具有複數銲墊之半導體基板上，其中，該線路增層結構具有設於該半導體基板與銲墊上之至少一介電層、設於該介電層上之線路、及設於該介電層中且電性連接該線路與銲墊之複數導電盲孔，又該電性連接墊設於該最外層之線路上，而該絕緣保護層係形成於該最外層之介電層上；形成一絕緣保護層於該線路增層結構上；形成複數第一開孔於該絕緣保護層上，以令該電性連接墊外露於該對應之第一開孔；形成金屬層於該電性連接墊上；形成金屬柱於該金屬層上；以及形成導電材料於該金屬柱上，以令該金屬層、金屬柱與導電材料作為該導電凸塊，且該導電凸塊與該第一開孔的孔壁之間具有間距，以外露出該電性連接墊之部分表面。
  15. 如申請專利範圍第14項所述之導電凸塊之製法，復包括：形成阻層於該線路增層結構上；形成口徑小於該第一開孔之孔徑的複數開口於該阻層上，且該開口對應該第一開孔，以令該電性連接墊外露於該開口；形成該導電凸塊於該開口中之電性連接墊上；以 及移除該阻層。
  16. 如申請專利範圍第14項所述之導電凸塊之製法，復包括形成絕緣層於該半導體基板具有該銲墊之表面上，使該線路增層結構係形成於該絕緣層上，且該絕緣層具有複數第二開孔，以令該線路增層結構經該第二開孔電性連接該銲墊。
  17. 如申請專利範圍第9或14項所述之導電凸塊之製法，其中，該金屬柱係為銅柱。
  18. 如申請專利範圍第9或14項所述之導電凸塊之製法，復包括形成阻障層於該金屬柱與該導電材料之間，以作為該導電凸塊之成份。
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Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103035604B (zh) * 2012-12-17 2014-07-16 矽力杰半导体技术(杭州)有限公司 一种倒装芯片封装结构及其制作工艺
US10163828B2 (en) * 2013-11-18 2018-12-25 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and fabricating method thereof
US10090267B2 (en) * 2014-03-13 2018-10-02 Taiwan Semiconductor Manufacturing Co., Ltd Bump structure and method for forming the same
US10356911B2 (en) 2014-07-04 2019-07-16 Samsung Electro-Mechanics Co., Ltd. Electronic device module and method of manufacturing the same
US9437565B2 (en) * 2014-12-30 2016-09-06 Advanced Seminconductor Engineering, Inc. Semiconductor substrate and semiconductor package structure having the same
DE102015100521B4 (de) 2015-01-14 2020-10-08 Infineon Technologies Ag Halbleiterchip und Verfahren zum Bearbeiten eines Halbleiterchips
US9653336B2 (en) * 2015-03-18 2017-05-16 Amkor Technology, Inc. Semiconductor device and manufacturing method thereof
US10461049B2 (en) * 2015-12-14 2019-10-29 Mitsubishi Electric Corporation Semiconductor device and manufacturing method therefor
KR102549580B1 (ko) * 2016-06-14 2023-06-29 (주)와이솔 플립 칩
JP2018006391A (ja) * 2016-06-28 2018-01-11 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US10818627B2 (en) * 2017-08-29 2020-10-27 Advanced Semiconductor Engineering, Inc. Electronic component including a conductive pillar and method of manufacturing the same
US10903151B2 (en) * 2018-05-23 2021-01-26 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method of manufacturing the same
KR102540961B1 (ko) * 2018-07-05 2023-06-07 삼성전자주식회사 반도체 칩, 및 이를 가지는 반도체 패키지
JP7383881B2 (ja) * 2019-01-16 2023-11-21 富士電機株式会社 半導体装置および半導体装置の製造方法
TWI693644B (zh) * 2019-01-28 2020-05-11 鼎元光電科技股份有限公司 封裝結構及其製造方法
US11600590B2 (en) * 2019-03-22 2023-03-07 Advanced Semiconductor Engineering, Inc. Semiconductor device and semiconductor package

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5943597A (en) * 1998-06-15 1999-08-24 Motorola, Inc. Bumped semiconductor device having a trench for stress relief
US20060226542A1 (en) * 2005-04-11 2006-10-12 Siliconware Precision Industries Co., Ltd. Semiconductor device and fabrication method thereof
US20090079094A1 (en) * 2007-09-21 2009-03-26 Stats Chippac, Ltd. Solder Bump with Inner Core Pillar in Semiconductor Package
US20120007230A1 (en) * 2010-07-08 2012-01-12 Taiwan Semiconductor Manufacturing Company, Ltd. Conductive bump for semiconductor substrate and method of manufacture

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09232321A (ja) * 1996-02-26 1997-09-05 Citizen Watch Co Ltd バンプ電極及びその製造方法
JP4324572B2 (ja) * 2005-03-03 2009-09-02 カシオマイクロニクス株式会社 バンプの形成方法
CN101221913A (zh) * 2007-01-08 2008-07-16 矽品精密工业股份有限公司 具导电凸块的半导体装置及其制法
JP2009064812A (ja) * 2007-09-04 2009-03-26 Panasonic Corp 半導体装置の電極構造およびその関連技術

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5943597A (en) * 1998-06-15 1999-08-24 Motorola, Inc. Bumped semiconductor device having a trench for stress relief
US20060226542A1 (en) * 2005-04-11 2006-10-12 Siliconware Precision Industries Co., Ltd. Semiconductor device and fabrication method thereof
US20090079094A1 (en) * 2007-09-21 2009-03-26 Stats Chippac, Ltd. Solder Bump with Inner Core Pillar in Semiconductor Package
US20120007230A1 (en) * 2010-07-08 2012-01-12 Taiwan Semiconductor Manufacturing Company, Ltd. Conductive bump for semiconductor substrate and method of manufacture

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