CN103325760B - 形成于半导体基板上的导电凸块及其制法 - Google Patents

形成于半导体基板上的导电凸块及其制法 Download PDF

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CN103325760B
CN103325760B CN201210098106.0A CN201210098106A CN103325760B CN 103325760 B CN103325760 B CN 103325760B CN 201210098106 A CN201210098106 A CN 201210098106A CN 103325760 B CN103325760 B CN 103325760B
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perforate
conductive projection
weld pad
protective layer
insulating protective
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CN103325760A (zh
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简丰隆
林怡宏
陈宜兴
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Siliconware Precision Industries Co Ltd
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Siliconware Precision Industries Co Ltd
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Abstract

一种形成于半导体基板上的导电凸块及其制法，该半导体基板上具有多个接点及一绝缘保护层，其中，该绝缘保护层形成有外露该接点的多个开孔，该导电凸块设于该开孔中的接点上，且该导电凸块与该开孔的孔壁间具有间距，借以使该导电凸块与绝缘保护层之间不具交界接口，以避免导电凸块因应力集中于不同材质的交界接口上而发生剥落。

Description

形成于半导体基板上的导电凸块及其制法
技术领域
本发明涉及一种导电凸块及其制法，特别是关于一种形成于半导体基板上的导电凸块及其制法。
背景技术
相比于打线接合(WireBond)技术，覆晶封装(FlipChipPackage)的特征在于半导体芯片与封装基板间的电性连接通过焊锡凸块而非一般的金线。近年来，由于高密度以及高速度的半导体组件需求的增加，同时因应电子产品的体积逐渐缩小的趋势，将覆晶组件设置于低成本的有机电路板，如：印刷电路板，并以环氧树脂底胶(Underfillresin)填充于芯片下方以减少硅芯片与有机电路板之间因热膨胀差异所产生的热应力，上述的种制法已呈一种趋势。
如图1A所示，半导体芯片1的表面上具有焊垫(electronicpad)100，而封装基板4也具有相对应的电性接触垫40，在该半导体芯片1与封装基板4之间可以适当地设置焊锡凸块5或其它导电粘着材料，使该半导体芯片1以作用面朝下的模式设置于该封装基板4上，其中，该焊锡凸块5或导电粘着材料提供该半导体芯片1与该封装基板4间的电性输入/输出(I/O)以及机械性的连接。
于一般覆晶工艺中，会于该半导体芯片1的焊垫100上形成导电凸块13(如图1B所示)，且于该封装基板4的电性接触垫40上形成预焊锡(图未示)，以借由两凸块相接而利于半导体芯片1与封装基板4两者的对位接合；接着，在足以使该导电凸块13熔融的回焊(solderreflow)温度条件下，将导电凸块13回焊至相对应的封装基板4的电性接触垫40上的预焊锡(图未示)，从而形成焊锡凸块5。的后，如图1A所示，再使用底胶6以实现半导体芯片1与封装基板4的耦合，以确保半导体芯片1与封装基板4两者的电性连接的完整性与可靠性。
现有半导体芯片1的导电凸块13的工艺中，如图1B所示，通过先于一晶圆10上覆盖一绝缘层12，以保护该晶圆10表面免受外在环境影响而劣化，且该绝缘层12外露该些焊垫100，再于该晶圆10上形成一绝缘保护层11，且该绝缘保护层11上形成有开孔110以外露该些焊垫100；接着，形成凸块底下金属层(underbumpmetallization，UBM)131于外露的焊垫100上，再形成焊锡材料134于该凸块底下金属层131上以制作出导电凸块13，并进行切单工艺，以将该晶圆10切割为多个半导体芯片1。
然而，该焊锡材料134所形成的导电凸块13经回焊后，该导电凸块13的体积及高度的平均值与公差控制不易；当该导电凸块13体积平均值偏小时，因锡量不足，容易使焊垫100仅部分沾锡或完全未沾锡，因而形成假焊或空焊，造成信赖性问题。若该导电凸块13的体积平均值偏大时，容易发生因锡量过多而与邻近接点造成短路的接点桥接(bridge)现象。
因此，该焊锡材料134所形成的导电凸块13的体积及高度的公差大，不仅焊锡凸块5容易产生缺陷，导致电性连接品质不良，且焊锡凸块5所排列成的栅状数组(gridarray)容易产生共面性(coplanarity)不良，因而部分焊点形成假焊或空焊而导致产品失效。所以该焊锡材料134所形成的导电凸块13，将使该半导体芯片1难以达到细间距的要求。
有鉴于此，发展出一种覆晶凸块技术，如图1C所示，先于该绝缘保护层11的开孔110中的凸块底下金属层131上形成铜柱132，再于该铜柱132上形成焊锡材料134，以利用铜材不会于回焊工艺中改变形状的特性，而控制导电凸块13’的高度与体积，进而控制该焊锡凸块5的崩溃(collapse)范围，使该半导体芯片1较易于达到细间距的要求。
然而，随着电子产品轻薄短小的发展趋势，该晶圆10上各个I/O之间的间距将越来越接近，而该晶圆10上的导电凸块13’的尺寸也逐渐缩小，但该铜柱132为一刚性结构，而该刚性结构的应力会集中于该凸块底下金属层131与绝缘保护层11两者的交界接口(interface)S上，导致于该凸块底下金属层131与绝缘保护层11的交界接口S上容易发生剥落(peeling)，而造成产品可靠度不佳的问题。
因此，如何克服上述现有技术的问题，实已成目前亟欲解决的课题。
发明内容
鉴于上述现有技术的种种缺失，本发明的主要目的在于提供一种形成于半导体基板上的导电凸块及其制法，避免导电凸块因应力集中于不同材质的交界接口上而发生剥落。
形成于半导体基板上的导电凸块，该半导体基板上具有多个焊垫及绝缘保护层，其中，该绝缘保护层形成有多个第一开孔，以令该焊垫外露于该对应的第一开孔，该导电凸块包括：金属层，其形成于外露于各该第一开孔中的焊垫上；金属柱，其形成于该金属层上；以及导电材料，其形成于该金属柱上；其中，该导电凸块与该第一开孔的孔壁之间具有间距。
本发明还提供一种导电凸块的制法，其包括：形成一绝缘保护层于一具有多个焊垫的半导体基板上；形成多个第一开孔于该绝缘保护层上，以令该焊垫外露于该对应的第一开孔；形成金属层于该焊垫上；形成金属柱于该金属层上；以及形成导电材料于该金属柱上，以令该金属层、金属柱与导电材料作为该导电凸块，且该导电凸块与该第一开孔的孔壁之间具有间距。
前述的制法中，其步骤可包括：形成阻层于该绝缘保护层上；形成口径小于该第一开孔的孔径的多个开口于该阻层上，且该开口对应该第一开孔，以令该焊垫外露于该开口；形成该导电凸块于该开口中的焊垫上；以及移除该阻层。
前述的导电凸块及其制法中，该半导体基板上可具有绝缘层，其形成于具有该焊垫的表面，使该绝缘保护层形成于该绝缘层上，且该绝缘层具有多个第二开孔，以令该焊垫对应外露于该第二开孔。该导电凸块与该第二开孔的孔壁之间可具有间距，且该第二开孔的孔径可小于该第一开孔的孔径。
本发明还提供一种形成于半导体基板上的导电凸块，该半导体基板上具有多个焊垫及线路增层结构，该线路增层结构上具有多个电性连接垫及绝缘保护层，该绝缘保护层形成有多个第一开孔，以令该电性连接垫外露于该对应的第一开孔，该导电凸块包括：金属层，其形成于外露于该第一开孔中的电性连接垫上；金属柱，其形成于该金属层上；导电材料，其形成于该金属柱上；以及其中，该导电凸块与该第一开孔的孔壁之间具有间距。
本发明再提供一种导电凸块的制法，其包括：形成一具有多个电性连接垫的线路增层结构于一具有多个焊垫的半导体基板上；形成一绝缘保护层于该线路增层结构上；形成多个第一开孔于该绝缘保护层上，以令该电性连接垫外露于该对应的第一开孔；形成金属层于该电性连接垫上；形成金属柱于该金属层上；以及形成导电材料于该金属柱上，以令该金属层、金属柱与导电材料作为该导电凸块，且该导电凸块与该第一开孔的孔壁之间具有间距。
前述的制法中，其步骤可包括：形成阻层于该线路增层结构上；形成口径小于该第一开孔的孔径的多个开口于该阻层上，且该开口对应该第一开孔，以令该电性连接垫外露于该开口；形成该导电凸块于该开口中的电性连接垫上；以及移除该阻层。
前述的导电凸块及其制法中，该线路增层结构可具有设于该半导体基板与焊垫上的至少一介电层、设于该介电层上的线路、及设于该介电层中且电性连接该线路与焊垫的多个导电盲孔，又该电性连接垫设于该最外层的线路上，而该绝缘保护层形成于该最外层的介电层上。
前述的导电凸块及其制法中，可包括形成绝缘层于该半导体基板具有该焊垫的表面上，使该线路增层结构形成于该绝缘层上，且该绝缘层具有多个第二开孔，以令该线路增层结构经该第二开孔电性连接该焊垫。
前述的两种导电凸块及其制法实施例中，该金属柱可为铜柱。
另外，前述的两种导电凸块及其制法方法中，可包括形成阻障层于该金属柱与该导电材料之间，以作为该导电凸块的成份。
由上可知，本发明导电凸块及其制法，主要借由该导电凸块与该第一开孔的孔壁之间具有间距，使该金属层与绝缘保护层之间并无交界接口，所以相比于现有技术，本发明有效避免金属柱的应力集中于不同材质的交界接口上，因而避免导电凸块发生剥落的现象，以达到提升产品可靠度的目的。
此外，借由该导电凸块与该第一开孔的孔壁之间具有间距，使后续覆晶工艺中，底胶可流入第一开孔，而增加底胶与该半导体芯片的接触面积，也就是强化底胶与该绝缘保护层间的结合力，因而可避免半导体芯片发生脱落的问题，以达到提升产品可靠度的目的。
附图说明
图1A为现有覆晶式封装结构的剖面示意图；
图1B及图1C为现有具有导电凸块的半导体芯片的不同实施例的剖面示意图；
图2A至图2E为本发明的导电凸块的制法的第一实施例的剖面示意图；以及
图3A至图3D为本发明的导电凸块的制法的第二实施例的剖面示意图。
主要组件符号说明
1，3，3’半导体芯片
10晶圆
100，300焊垫
11，31绝缘保护层
110开孔
12，32绝缘层
13，13’，2导电凸块
131凸块底下金属层
132铜柱
134焊锡材料
21金属层
22金属柱
23阻障层
24导电材料
30半导体基板
301电性连接垫
310第一开孔
320第二开孔
33光阻层
330开口
34线路增层结构
340介电层
341线路
342导电盲孔
4封装基板
40电性接触垫
5焊锡凸块
6底胶
R，r孔径
t口径
w宽度
D，d间距
S交界接口。
具体实施方式
以下借由特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其它优点及功效。
须知，本说明书所附图式所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供本领域技术人员的了解与阅读，并非用以限定本发明可实施的限定条件，所以不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”及“一”等的用语，也仅为便于叙述的明了，而非用以限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当也视为本发明可实施的范畴。
请参阅图2A至图2D，其为本发明的导电凸块的制法的第一实施例的剖面示意图，所述的导电凸块2形成于半导体芯片3上。
如图2A所示，形成一绝缘层32于一具有多个焊垫300的半导体基板30上，且该绝缘层32具有多个第二开孔320，以令各该焊垫300对应外露于该第二开孔320。
接着，形成一绝缘保护层31于该绝缘层32上，再形成多个第一开孔310于该绝缘保护层31上且对应各该第二开孔320的位置，以令各该焊垫300对应外露于各该第一开孔310。
于本实施例中，该半导体基板30为晶圆，而于其它实施例中，该半导体基板30也可为硅基板或玻璃基板。
此外，形成该焊垫300的材质可为铝材，且形成该绝缘层32的材质可为氮化硅(SiN)或硅的氧化合物(SiOX)以作为钝化层(passivationlayer)，而形成该绝缘保护层31的材质可为亚聚酰胺(Polyimide，PI)、苯环丁烯(Benezocy-clobutene，BCB)或聚苯并噁唑(Polybenzoxazole，PBO)。
此外，该第二开孔320的孔径r小于该第一开孔310的孔径R。
另外，因于各该焊垫300上所进行的工艺相同，所以图式中仅以单一焊垫300作表示。
如图2B所示，形成一金属层21于该绝缘保护层31与各该焊垫300上，再形成一光阻层33于该金属层21上。
接着，借由曝光、显影工艺，形成多个开口330于该光阻层33上，且各该开口330对应该第一及第二开孔310，320的位置，以令各该焊垫300上的金属层21外露于各该开口330。
于本实施例中，该开口330的口径t小于该第一及第二开孔310，320的孔径R，r。
此外，该金属层21作为后述电镀金属材料所需的电流传导路径，且形成该金属层21的材质可为钛/铜(Ti/Cu)或钛/钨/铜(Ti/W/Cu)。
如图2C所示，电镀形成一金属柱22于各该开口330中的金属层21上，再形成一阻障层(barrierlayer)23于各该金属柱22上。接着，形成一如焊锡材料的导电材料24于各该阻障层23上。
于本实施例中，该金属层21也可作为凸块底下金属层(underbumpmetallization，UBM)，且该金属柱22为铜柱，而形成该阻障层23的材质可为镍(Ni)、钛/钨(Ti/W)或镍钒(Ni/V)。
如图2D所示，移除该光阻层33及其下的金属层21，以令该金属层21、金属柱22、阻障层23与导电材料24作为导电凸块2，且令该导电凸块2与该第一及第二开孔310，320的孔壁之间具有间距D，d，也就是该导电凸块2的宽度w小于该第一及第二开孔310，320的孔径R，r。
接着，经由切单至工艺，以形成具有该导电凸块2的半导体芯片3。
如图2E所示，于后续工艺中，经回焊该导电凸块2，使该导电材料24覆晶结合一封装基板(图未示)。
本发明导电凸块2的制法，主要借由该导电凸块2与该第一及第二开孔310，320的孔壁之间具有间距D，d，也就是该导电凸块2未接触该绝缘保护层31与绝缘层32，使该金属层21与该绝缘保护层31(及该绝缘层32)之间并无交界接口(interface)，所以该金属柱22的应力将集中于金属材的焊垫300与金属层21上，而不会集中于不同材质(非金属材)的绝缘保护层31(及该绝缘层32)上，因而可避免因该金属柱22的应力集中于不同材质的交界接口上而导致该导电凸块2剥落的问题。
此外，借由该第一及第二开孔310，320完全露出该导电凸块2，且该第二开孔320的孔径r小于该第一开孔310的孔径R，以形成阶梯孔洞，使后续覆晶工艺的形成底胶(图未示)的步骤中，底胶可流入阶梯孔洞，而增加底胶与该半导体芯片3的接触面积，也就是强化底胶与该绝缘保护层31间的结合力，以避免该半导体芯片3发生脱落的问题。
基于上述优点，将使封装基板(图略)与半导体芯片3覆晶相接合所构成的封装件(图略)中，所形成的电性接点更能够承受该封装基板与该半导体芯片3间所产生的应力，而使该封装件具有更佳的可靠度。
因此，本发明还提供一种形成于半导体基板30上的导电凸块2，该半导体基板30上具有焊垫300及绝缘保护层31，其中，该绝缘保护层31形成有第一开孔310，以令该焊垫300外露于该第一开孔310，而该导电凸块2设于该第一开孔310中的焊垫300上。
所述的导电凸块2的宽度w小于该第一开孔310的孔径R，使该导电凸块2与该第一开孔310的孔壁之间具有间距D，且该导电凸块2包括：形成于该焊垫300上的金属层21、形成于该金属层21上的金属柱22、形成于该金属柱22上的阻障层23、以及形成于该阻障层23上的导电材料24。
所述的金属柱22为铜柱。
另外，该绝缘保护层31与该半导体基板30之间还形成有绝缘层32，且该绝缘层32具有第二开孔320，以令该焊垫300外露于该第二开孔320；又该第二开孔320的孔径r小于该第一开孔310的孔径R，且该第二开孔320的孔径r大于该导电凸块2的宽度w，使该导电凸块2与该第二开孔320的孔壁之间也具有间距d，如图2D所示。
请参阅图3A至图3D，其为本发明的导电凸块2的制法的第二实施例的剖面示意图。本实施例与第一实施例的差异仅在于半导体芯片3’的结构，其它相关工艺均大致相同，所以不再赘述。
如图3A所示，提供一具有至少一焊垫300的半导体基板30，且形成一绝缘层32于该半导体基板30上，该绝缘层32具有第二开孔320，以外露各该焊垫300。
接着，形成一线路增层结构34于该绝缘层32及焊垫300上，该线路增层结构34具有设于该绝缘层32与焊垫300上的至少一介电层340、设于该介电层340上的线路341、及设于该介电层340中且电性连接该线路341的多个导电盲孔342，该导电盲孔342经该第二开孔320电性连接该焊垫300，又该最外层的线路341具有电性连接垫301。
于本实施例中，形成该焊垫300的材质可为铝材，且形成该介电层340的材质可为亚聚酰胺(Polyimide，PI)、苯并环丁烯(Benezocy-clobutene，BCB)或聚苯并噁唑(Polybenzoxazole，PBO)，而形成该线路341的材质可为钛/铜(Ti/Cu)或钛/钨/铜(Ti/W/Cu)。
此外，有关电性连接垫301的数量与线路增层结构34的层数并无特别限制。
再者，因于各该电性连接垫301上所进行的导电凸块工艺相同，所以图式中仅以单一电性连接垫301作表示。
如图3B所示，形成一绝缘保护层31于于该最外层的介电层340上，再形成多个第一开孔310于该绝缘保护层31上，以令各该电性连接垫301外露于各该第一开孔310。
如图3C所示，形成一金属层21于该绝缘保护层31与各该电性连接垫301上，再形成一光阻层33于该金属层21上。
接着，形成多个开口330于该光阻层33上，且各该开口330对应该第一开孔310的位置，以令各该电性连接垫301上的金属层21外露于各该开口330。
最后，借由金属层21电镀形成一导电凸块2于各该开口330中的电性连接垫301上。
如图3D所示，移除该光阻层33及其下的金属层21，令该导电凸块2与该第一开孔310的孔壁之间具有间距D，也就是该导电凸块2的宽度w小于该第一开孔310的孔径R。
之后，经由切单至工艺，以形成具有该导电凸块2的半导体芯片3’。
因此，本发明还提供一种形成于半导体基板30上的导电凸块2，该半导体基板30上具有焊垫300及线路增层结构34，该线路增层结构34上具有电性连接垫301及绝缘保护层31，该绝缘保护层31形成有第一开孔310，以令该电性连接垫301外露于该第一开孔310，而该导电凸块2设于该第一开孔310中的电性连接垫301上。
所述的导电凸块2的宽度w小于该第一开孔310的孔径R，使该导电凸块2与该第一开孔310的孔壁之间具有间距D，且该导电凸块2包括：形成于该电性连接垫301上的金属层21、形成于该金属层21上的金属柱22、形成于该金属柱22上的阻障层23、以及形成于该阻障层23上的导电材料24。
所述的金属柱22为铜柱。
所述的线路增层结构34具有至少一设于该半导体基板30与焊垫300上的介电层340、设于该介电层340上的线路341、及设于该介电层340中且电性连接该线路341与焊垫300的导电盲孔342。
所述的绝缘保护层31形成于该最外层的介电层340上，且最外层的线路341具有该电性连接垫301。
于一实施例中，该线路增层结构34与该半导体基板30之间还形成有绝缘层32，且该绝缘层32具有第二开孔320，以令该导电盲孔342经该第二开孔320电性连接该焊垫300。
综上所述，本发明的导电凸块及其制法，借由该导电凸块与该第一开孔的孔壁之间具有间距，使该金属层与绝缘保护层之间并无交界接口，所以有效避免金属柱的应力集中于不同材质的交界接口上，因而避免导电凸块发生剥落的现象，以达到提升产品可靠度的目的。
此外，借由该第一开孔(及第二开孔)完全露出该导电凸块(于第一实施例中，该第二开孔的孔径小于该第一开孔的孔径)，使后续覆晶工艺中，底胶可流入第一开孔(及与第二开孔)，而增加底胶与该半导体芯片的接触面积，也就是强化底胶与该绝缘保护层间的结合力，因而可避免半导体芯片发生脱落的问题，以达到提升产品可靠度的目的。
上述实施例仅用以例示性说明本发明的原理及其功效，而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (7)

1.一种形成于半导体基板上的导电凸块，该半导体基板上具有多个焊垫及绝缘保护层，其中，该绝缘保护层形成有多个第一开孔，以令该焊垫外露于对应的该第一开孔，该导电凸块包括：
金属层，其形成于外露于各该第一开孔中的焊垫上；
金属柱，其形成于该金属层上；
导电材料，其形成于该金属柱上；
其中，该导电凸块与该第一开孔的孔壁之间具有间距，以外露出该焊垫的部份表面；以及
绝缘层，其形成于具有该焊垫的表面，使该绝缘保护层形成于该绝缘层上，且该绝缘层具有多个第二开孔，以令该焊垫对应外露于该第二开孔，该导电凸块与该第二开孔的孔壁之间具有间距，其中，该第二开孔的孔径小于该第一开孔的孔径。
2.根据权利要求范围1所述的导电凸块，其特征在于，该金属柱为铜柱。
3.根据权利要求范围1所述的导电凸块，其特征在于，该导电凸块还包括阻障层，其形成于该金属柱与该导电材料之间。
4.一种导电凸块的制法，其包括：
形成一绝缘保护层于一具有多个焊垫的半导体基板上；
形成多个第一开孔于该绝缘保护层上，以令该焊垫外露于对应的该第一开孔；
形成金属层于该焊垫上；
形成金属柱于该金属层上；
形成导电材料于该金属柱上，以令该金属层、金属柱与导电材料作为该导电凸块，且该导电凸块与该第一开孔的孔壁之间具有间距，以外露出该焊垫的部份表面；以及
形成绝缘层于该半导体基板具有该焊垫的表面上，使该绝缘保护层形成于该绝缘层上，且该绝缘层具有多个第二开孔，以令该焊垫对应外露于该第二开孔，该导电凸块与该第二开孔的孔壁之间具有间距，其中，该第二开孔的孔径小于该第一开孔的孔径。
5.根据权利要求范围4所述的导电凸块的制法，其特征在于，该制法还包括：
形成阻层于该绝缘保护层上；
形成口径小于该第一开孔的孔径的多个开口于该阻层上，且该开口对应该第一开孔，以令该焊垫外露于该开口；
形成该导电凸块于该开口中的焊垫上；以及
移除该阻层。
6.根据权利要求范围4所述的导电凸块的制法，其特征在于，该金属柱为铜柱。
7.根据权利要求范围4所述的导电凸块的制法，其特征在于，该制法还包括形成阻障层于该金属柱与该导电材料之间，以作为该导电凸块的成份。
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