CN102194760A - 半导体结构及形成半导体装置的方法 - Google Patents

半导体结构及形成半导体装置的方法 Download PDF

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Publication number
CN102194760A
CN102194760A CN2010102510890A CN201010251089A CN102194760A CN 102194760 A CN102194760 A CN 102194760A CN 2010102510890 A CN2010102510890 A CN 2010102510890A CN 201010251089 A CN201010251089 A CN 201010251089A CN 102194760 A CN102194760 A CN 102194760A
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layer
welding disk
conductive welding
width
base material
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CN2010102510890A
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曾明鸿
陈承先
郭正铮
陈志华
萧景文
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Publication of CN102194760A publication Critical patent/CN102194760A/zh
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Abstract

本发明公开了一种半导体结构及形成半导体装置的方法，其中该半导体结构包括：一基材以及一柱体，基材包括一导电焊盘，该导电焊盘具有一第一宽度，柱体电性耦接于该导电焊盘，该柱体具有一第二宽度，其中该第一宽度比该第二宽度大了大约6微米或6微米以上。本发明提供一凸块底部金属化结构，用于一半导体装置中。一钝化层形成于接触垫上，而暴露接触垫的至少一部分。一保护层，例如一聚酰亚胺层，形成于该钝化层上。该凸块底部金属化结构，例如一导电柱体形成于该接触垫上，使下方的接触垫朝侧向延伸而超过该凸块底部金属化结构一足够大的距离，而避免或减少钝化层与保护层的破裂。

Description

半导体结构及形成半导体装置的方法
技术领域
本发明涉及半导体装置，尤其涉及一种半导体装置的凸块底部金属化结构。
背景技术
自从集成电路发明后，由于各种电子元件(即，晶体管、二极管、电阻、电容等)的集成密度的持续改良，半导体产业历经了持续的快速成长。对于大部分而言，这种改良由于不断地降低最小特征尺寸，这可使更多的元件被整合于一既定的面积中。
在过去的几十年，可以看到许多半导体封装上的改变，冲击了整个半导体产业。引进表面粘着技术(surface mount technology，SMT)以及球栅阵列(ball grid array，BGA)封装为各种IC装置的高产能组装的重要步骤，同时可降低印刷电路板的焊盘间距。传统上，封装后的IC具有基本上以细的金线连接裸片的金属焊盘之间的构造，且电极从成形后的树脂封装延伸而出。另一方面，某些CSP(Chip Scale Package)或BGA封装依赖焊盘提供裸片与基材之间的电性接触，基材为例如封装基材、印刷电路板(PCB)、其他裸片/晶片等等。其他的CSP或BGA封装利用焊球或焊盘形成于一导电柱体上，依靠焊料结合而达成结构的整体性。构成内连线的不同层通常具有不同的热膨胀系数(CTE)，因此在结合区域由于热膨胀系数的差异造成相对大的应力，而经常造成断裂。
发明内容
为了解决上述问题，本发明的一优选实施例提供一种半导体结构，包括一基材以及一柱体，基材包括一导电焊盘，该导电焊盘具有一第一宽度，柱体电性耦接于该导电焊盘，该柱体具有一第二宽度，其中该第一宽度比该第二宽度大了大约6微米或6微米以上。
本发明的另一优选实施例提供一半导体结构，其包括一基材以及一柱体，基材包括一导电焊盘，该导电焊盘具有一第一宽度，柱体电性耦接于该导电焊盘，该柱体具有一第二宽度，其中该导电焊盘朝侧向延伸而超过该柱体大约3微米或3微米以上的距离。
本发明也提供了一种形成半导体装置的方法，该方法包括下列步骤：提供一基材，其具有一导电焊盘，该导电焊盘具有一第一外边界；在该基材以及该导电焊盘上形成一钝化层，该导电焊盘的至少一部分是暴露在外；以及形成一导电柱体，电性接触于该导电焊盘，该导电焊盘具有一第二外边界，从平面观看，该第二外边界与该第一外边界相距至少3微米。
本发明使用凸块底部金属化结构，例如一导电柱体形成于该接触垫上，使下方的接触垫朝侧向延伸而超过该凸块底部金属化结构一足够大的距离，而可以减低应力，而且可以减低和/或消除钝化层及/或保护层的断裂。
为了让本发明的上述和其他目的、特征、和优点能更明显易懂，下文特举一优选实施例，并配合附图，作详细说明如下。
附图说明
图1为本发明实施例的半导体装置的接触焊盘的平面图。
图2～图6表示形成一半导体装置的各种中间步骤，该半导体装置具有本发明实施例的凸块底部金属结构。
上述附图中的附图标记说明如下：
100～基材
102～外部接点
104～保护层
106～开口
108～导电焊盘
110～凸块底部金属化结构
202～基材
204～电路系统
208～层间介电层
210～接点
212～金属层间介电层
214～接点
216～保护层
218～导电焊盘
220～钝化层
310～保护层
410～晶种层
412～掩模
510～导电柱体
512～导电性覆盖层
514～焊料
D～距离
具体实施方式
以下详细说明本发明的实施例的制作及使用。需了解的是这些实施例提供了许多启发性的概念，可应用于各种特定的情况中。此处所探讨的特定的实施例只是用于表示以特定的方式制作及使用该实施例，而并非用于限制本发明。
此处所探讨的实施例是与使用于半导体装置中凸块底部金属化结构(UBM)有关。如以下所探讨，使用凸块底部金属化结构(UBM)是用于将一基材附着于另一基材，其中每一基材可以是裸片、晶片、印刷电路板、封装基材等，而达成裸片附着于裸片、晶片附着于晶片、裸片或晶片附着于印刷电路板或封装基材等。在所述多个实施例中，相同的元件给予相同的符号。
图1为一基材100的平面图，该实施例的基材100具有外部接点102。基材100的外表面由一保护层104所覆盖，例如聚酰亚胺(polyimide)层，以保护基材免于受环境污染。在保护层104中形成开口106，其具有一宽度WPadOpen，而暴露出下方的导电焊盘108，导电焊盘108具有一宽度WPad。
在图1中也显示了一UBM 110的轮廓，UBM 110具有一宽度WUBM。UBM 110可以是例如铜或其他导电材料的柱体结构，其提供了与下方的导电焊盘108的电性连接。UBM 110可以再连接至另一基材，例如裸片、晶片、印刷电路板、封装基材等。
虽然产业的趋势是如以上所探讨的使装置越来越小，但是尺寸的减小在某些区域会产生应力而可能使装置失效。例如，形成半导体装置时，UBM 110的宽度WUBM与下方导电焊盘108的宽度WPad的差异很小，例如2微米或更小，这样可能会对钝化层(未图示，参照以下的附图)和/或保护层104施加足够的应力，而造成其中之一或两者产生破裂。与现在的趋势相反，当WUBM与WPad之间的差增加至6微米或更大(例如在每一方向朝侧向延伸3微米)而非缩小WUBM与WPad之间的差异时，可以减低应力，而且可以减低和/或消除钝化层及/或保护层的断裂。
图2～图6表示形成图1的本发明的实施例的半导体装置的各种中间步骤。参照图2，其表示本实施例中，在基材202的一部分形成电路系统204。基材202可以包括例如块状硅(bulk silicon)、掺杂或无掺杂、或绝缘上覆硅(SOI)基材的主动层。一般而言，SOI基材包括一半导体材料(例如硅)形成于一绝缘层上。该绝缘层可以是例如埋层氧化层(buried oxide layer，BOX)或硅氧化层。该绝缘层提供于一基材上，典型是一硅基材或一玻璃基材。也可以使用其他的基材，例如多层基材或梯度基材(gradient substrate)。
形成于基材202的电路系统204可以是适用于特殊用途的任何形态的电路系统。在一实施例中，电路系统204包括形成于基材202上的多个电子装置，并具有一或多个介电层覆盖于所述多个电子装置上。在介电层之间可形成金属层，用于在所述多个电子装置之间传递信号。电子装置可形成于一或多个介电层上。
例如，电路系统204可包括不同的N型的金属氧化半导体(NMOS)装置和/或P型的金属氧化半导体(PMOS)装置，例如晶体管、电容器、电阻、二极管、光二极管、保险丝等。对于本领域普通技术人员而言可以理解上述例子只是用于图示，以便对一些图示的实施例作更进一步的说明，但并非用于限制本发明，对于一已知的用途而言也可以使用其他的电路系统。
图2表示一层间介电层(ILD层)208。该ILD层208可以用低K值的材料以已知的适当方法形成。该低K值的材料可以是例如磷硅玻璃(PSG)、硼磷硅玻璃(BPSG)、氟硅玻璃(FSG)、SiOxCy、旋涂式玻璃(SOG)、旋涂式聚合物、碳硅材料、上述所述多个物质的化合物、上述所述多个物质的复合物或上述所述多个物质的组合等。该已知的适当方法可以是例如旋转涂布法、化学气相沉积法(CVD)、等离子体辅助化学气相沉积法(PECVD)。需注意的是ILD层208可包含多个个介电层。
接点，例如接点210是穿过ILD层208以提供与电路系统204的电性接触。接点208可以通过使用例如光刻技术将光致抗蚀剂材料沉积于ILD层208并图案化，而使ILD层208的一部分暴露而成为接点210。蚀刻工艺，例如各向异性干蚀刻，可用于在ILD层208上产生开口。该开口可形成扩散阻挡层(diffusion barrier layer)和/或粘着层做为衬层(未图示)，并以导电性材料充填。在一实施例中，扩散阻挡层包括一或多层的TaN、Ta、TiN、Ti、CoW等，而导电性材料包括铜、钨、铝、银以及所述多个物质的组合等，藉此形成如图2所示的接点210。
在ILD层208上形成一或多个金属间介电层(IMD层)212以及相关的金属化层(未图示)。一般而言，该一或多个IMD层212以及相关的金属化层用于电路系统204彼此之间的连接并提供一外部连接。IMD层212可以由低K值的材料，例如FSG以PECVD技术或高密度等离子体化学气相沉积法(HDPCVD)等形成，也可以包括中间蚀刻终止层。接点214由最上层的IMD层提供，以提供外部电性连接。
需注意的是一或多个蚀刻终止层(未图示)可设于相邻的介电层之间，例如ILD层208与IMD层212。一般而言，蚀刻终止层在形成贯孔和/或接点时提供了终止蚀刻工艺的机制。蚀刻终止层形成于介电物质上，并与相邻的层具有不同的蚀刻选择比，例如下方的半导体基材202、上方的ILD层208以及上方的IMD层212。在一实施例中，蚀刻终止层可由SiN、SiCN、SiCO、CN以及所述多个物质的组合而形成，由CVD或PECVD技术沉积形成。
保护层216可由介电材料形成，例如SiN，等离子体辅助氧化物(PEOX)、等离子体辅助SiN(PE-SiN)、等离子体辅助未掺杂硅玻璃(PE-USG)等，并使最上层的IMD层212的表面图案化，以提供接点214上方的开口，以保护下方膜层免于环境污染。因此，导电焊盘218形成于保护层216的上方并经图案化。导电焊盘218提供了与UBM结构的电性连接，例如与铜柱体结构的电性连接，可以作为外部连接。导电焊盘218可由任何适当的导电性材料形成，例如铜、钨、铝、银、或所述多个物质的组合等。
一或多个钝化层，例如钝化层220形成于导电焊盘218上并将之图案化，如图2所示。钝化层220可由介电材料以任何适当的方法形成。介电材料可以是例如PE-USG、PE-SiN或其组合等。适当的方法可以是例如CVD、PVD等。在一实施例中，钝化层具有大约10000埃至15000埃的厚度。在一实施例中，钝化层220包括一多层结构，包含厚度750埃的SiN、6500埃的PE-USG以及6000埃的PE-SiN。
本领域普通技术人员了解单一层的导电焊盘及钝化层只是用于举例说明。如此，其他的实施例可包括任意数量的导电层和/或钝化层。而且，必须了解的是可使用一或多个导电层可以作为重分布层(redistribution layer)，以提供所需的引脚或球的布局。
可使用任何适当的工艺以形成上述的结构，在后面的说明中不再详细讨论。本领域普通技术人员了解以上的叙述是提供了本实施例的一般性的说明，除上述外，尚可寻找其他很多的特征。例如，其他的电路系统、衬层、阻挡层、凸块底部金属化特征等。以上的说明只是提供用于实施例中讨论的内容，而非用于限制这些实施例的范围。
图3显示一保护层310形成于钝化层220上并经过图案化。保护层310可以是以任何适当的工艺所形成的聚酰亚胺材料，例如以CVD、PVD等形成。在一实施例中，保护层310具有大约2.5微米至大约10微米的厚度。
图4表示一顺应性的晶种层410沉积于保护层310的表面。晶种层410为一导电性材料的薄层，其有助于在后续的工艺中形成较厚的层。在一实施例中，晶种层410可以通过沉积一薄导电层而形成，例如使用CVD或物理气相沉积(PVD)法形成Cu、Ti、Ta、TiN、TaN或其组合等的薄层。例如可由PVD工艺沉积Ti层而形成一阻挡膜，可由PVD工艺沉积Cu层而形成一晶种层。
因此，如图4所示，本实施例形成一图案化的掩模412并形成于晶种层410上。图案化的掩模412定义出该导电柱体的侧边界，以便在后续的工艺中可以形成，在后面会详细地说明。图案化的掩模412可以是图案化的光致抗蚀剂掩模、硬掩模或两者的组合等。
图5显示本发明的实施例中形成导电柱体510。导电柱体510可以用任何适当的导电性材料形成，例如包括Cu、Ni、Pt、Al或所述多个物质的组合等，且可经由任意适当的技术形成，例如PVD、CVD、电化学沉积法(ECD)、分子束外延法(MBE)、原子层沉积法(ALD)、电镀等。必须注意的是在某些实施例中，例如在晶片的整个表面上沉积了相同大小的层(例如PVD及CVD)，需要实施蚀刻或平坦化工艺(例如化学机械研磨(CMP)工艺)，以便从图案化掩模412上除去多余的导电性材料。在一实施例中，导电柱体510具有厚度大约在20微米至50微米之间。
图5表示在导电柱体510上形成一非必要的(optional)导电性覆盖层512。如以下的详细说明所述，焊料形成于导电柱体510上。在焊接工艺中，一金属间化合物层(IMC)(未图示)可自然地形成于焊料与基材之间的结合处。某些材料可以产生较其他材料的更强、更耐用的IMC层。因此，需要形成一覆盖层，例如需要导电性覆盖层512，以提供具有更多所需要的特性的金属间化合物层(IMC)。例如，在一实施例中，其导电柱体510由铜形成，导电性覆盖层512由镍形成。其他可以使用的材料例如Pt、Au、Ag或这些物质的组合等。导电覆盖层512可经由数种适当的技术形成，例如PVD、CVD、ECD、MBE、ALD、电镀等。
而且，图5也显示焊料514的形成。在一实施例中，焊料514包括SnPb、高含铅量材料、Sn基焊料、无铅焊料或其他适当的导电性材料。
如上所述，在一实施例中，导电柱体510的尺寸及位置相对于导电焊盘218是有着3微米或3微米以上的距离D。目前已发现，当装置中的导电焊盘218侧向延伸而超过导电柱体510的外边界3微米或3微米以上的距离时，可以降低保护层310和/或钝化层220的应力及破裂。
之后，如图6所示，图案化掩模412可被移除。在实施例中，图案化掩模412由光致抗蚀剂材料形成，此光致抗蚀剂材料可由例如化学溶液或其他光致抗蚀剂去除工艺除去，化学溶液可以是下列成分的混合：乳酸乙酯、苯氧基甲烷、乙酸甲丁酯、乙酸戊酯、邻甲酚环氧树脂以及重氮系感光剂(称为SPR9)。可实施一清洗工艺，例如称为DPP，其为浸泡于磷酸(H3PO4)及过氧化氢(H2O2)并具有2％的氢氟酸的化学溶液中，或实施其他的清洗工艺，以移除晶种层410暴露的部分以及来自钝化层220表面的污染物。
因此，可以实施回焊工艺以及其他适用于特殊用途的半导体后段(BEOL)处理技术。例如，可形成密封胶材，可实施分割工艺，用于分割个别的裸片，可实施晶片等级或裸片等级的堆叠等。需注意的是，所述多个实施例可用于不同的情况。例如，所述多个实施例可用于裸片对裸片的结合、裸片对晶片的结合、晶片对晶片的结合、裸片等级的封装、晶片等级的封装等。
需注意的是，其他实施例中，在基材202结合于其他基材(未图示)之前，焊料不会被置于导电柱体510上。在这些实施例中，焊料可以置于其他的基材上，然后在基材202上的导电柱体510可以与其他基材上的焊料接触，实施回焊工艺而将两基材焊接在一起。
虽然已经详述本实施例及其优点，但在不偏离由权利要求所定义的实施例的精神与范畴的情况下，可做各种的变更、取代以及变化。而且本发明的范畴不受到说明书中所叙述实施例的工艺、机器、生产以及物品的组合、装置、方法及步骤所限制。对于本领域普通技术人员而言，可从现有或未来发展的工艺、机器、生产以及物品的组合、装置、方法及步骤等，根据本发明的实施例达到大体上相同的功效或达到相同的结果。据此，权利要求已经包含了此种工艺、机器、生产以及物品的组合、装置、方法及步骤。此外，每一权利要求构成一实施例，且不同权利要求与实施例的组合是包含于本发明的范畴之内。

Claims (10)

1.一种半导体结构，包括：
一基材，包括一导电焊盘，该导电焊盘具有一第一宽度；以及
一柱体，电性耦接至该导电焊盘，该柱体具有一第二宽度，其中该第一宽度大于该第二宽度约6微米或6微米以上。
2.如权利要求1所述的半导体结构，其还包括一材料层，形成于该柱体上，并与该导电焊盘电性接触，其中该材料层由焊料、镍、铂、金或银形成。
3.如权利要求1所述的半导体结构，其还包括一钝化层覆盖于该导电焊盘的至少一部分，以及一保护层覆盖于该钝化层上。
4.如权利要求3所述的半导体结构，其中该保护层为聚酰亚胺。
5.一种半导体结构，包括：
一基材，包括一导电焊盘，该导电焊盘具有一第一宽度；以及
一柱体，电性耦接至该导电焊盘，该柱体具有一第二宽度，其中该导电焊盘朝侧向延伸而超过该柱体大约3微米或3微米以上的距离。
6.如权利要求5所述的半导体结构，其还包括一焊料，形成于该柱体上，并与该导电焊盘做电性接触。
7.如权利要求5所述的半导体结构，其还包括一覆盖层，形成于该柱体上，其中该覆盖层由镍、铂、金或银形成。
8.如权利要求5所述的半导体结构，其还包括一钝化层覆盖于该导电焊盘的至少一部分，以及一保护层覆盖于该钝化层上。
9.一种形成半导体装置的方法，该方法包括下列步骤：
提供一基材，其具有一导电焊盘，该导电焊盘具有一第一外边界；
在该基材以及该导电焊盘上形成一钝化层，且暴露出该导电焊盘的至少一部分；以及
形成一导电柱体，与该导电焊盘电性接触，该导电焊盘具有一第二外边界，从平面观看，该第二外边界与该第一外边界相距至少3微米。
10.如权利要求9所述的形成半导体装置的方法，其还包括一步骤：形成一材料层于该柱体上，其中该材料层由焊料、镍、铂、金或银形成。
CN2010102510890A 2010-03-16 2010-08-09 半导体结构及形成半导体装置的方法 Pending CN102194760A (zh)

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