CN103247593A - 钝化后互连结构及其形成方法 - Google Patents

钝化后互连结构及其形成方法 Download PDF

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CN103247593A
CN103247593A CN2012101921298A CN201210192129A CN103247593A CN 103247593 A CN103247593 A CN 103247593A CN 2012101921298 A CN2012101921298 A CN 2012101921298A CN 201210192129 A CN201210192129 A CN 201210192129A CN 103247593 A CN103247593 A CN 103247593A
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layer
interconnection
semiconductor device
dielectric layer
substrate
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CN103247593B (zh
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陈宪伟
吴逸文
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

半导体器件包括形成在钝化后互连(PPI)结构的表面上的介电层。聚合物层形成在介电层上方并且将该聚合物层图案化为具有开口以露出介电层的一部分。然后去除介电层的露出部分以露出PPI结构的一部分。然后在PPI结构的第一部分的上方形成焊料凸块并且焊料凸块与PPI结构的第一部分电连接。本发明还提供了钝化后互连结构及其形成方法。

Description

钝化后互连结构及其形成方法
技术领域
本公开涉及半导体器件的制造，更具体地，涉及钝化后互连(PPI)结构的制造。
背景技术
现代集成电路由数百万个有源器件(诸如晶体管和电容器)组成。这些器件开始相互隔离，但是随后互连在一起以形成功能电路。典型的互连结构包括诸如金属线(配线)的横向互连以及诸如通孔和接触件的垂直互连。互连越来越多地确定现代集成电路的性能和密度的限制。在互连结构的顶部，在对应芯片的表面上形成并露出接合焊盘。通过接合焊盘进行电连接以将芯片连接至封装衬底或另一管芯。接合焊盘用于引线接合或倒装芯片封装。倒装芯片封装利用凸块来建立芯片的输入/输出(I/O)焊盘和封装衬底或封装件的引线框之间的电接触。在结构上，凸块实际包含凸块本身以及位于凸块和I/O焊盘之间的“凸块底部金属化层”(UBM)。
晶圆级芯片尺寸封装(WLCSP)目前由于与其他封装工艺相比较低的成本和相对简单的工艺而被广泛使用。在典型的WLCSP中，诸如再分布线(RDL)的钝化后互连(PPI)线被形成在钝化层上方，随后形成聚合物膜和凸块。然而，凸块和聚合物层之间的界面具有较差的粘合性并遭受湿气侵袭，这会引起聚合物层中的分层。
发明内容
为了解决现有技术中所存在的缺陷，根据本发明的一方面，提供了一种半导体器件，包括：半导体衬底；钝化层，覆盖所述半导体衬底；互连层，覆盖所述钝化层；介电层，形成为覆盖所述互连层但不覆盖所述互连层的第一部分，其中，所述介电层包括氮化物；保护层，形成为覆盖所述介电层但不覆盖所述互连层的第一部分；以及凸块，形成为覆盖所述互连层的第一部分并与所述互连层的第一部分电连接。
在该半导体器件中，所述介电层包括氮化硅层。
该半导体器件还包括：金属化层，位于所述凸块和所述互连层的第一部分之间。
在该半导体器件中，所述金属化层包括含钛层和含铜层。
在该半导体器件中，所述保护层包括聚合物层。
在该半导体器件中，所述互连层包括铜层或铜合金层。
该半导体器件还包括：另一保护层，位于所述互连层和所述钝化层之间。
在该半导体器件中，所述另一保护层包括聚合物层。
在该半导体器件中，所述介电层延伸到所述另一保护层的表面。
在该半导体器件中，所述凸块包括直径大于200μm的焊料凸块。
根据本发明的另一方面，提供了一种封装组件，包括通过焊料接合结构电连接至衬底的半导体器件，其中，所述半导体器件包括：钝化后互连(PPI)结构；介电层，形成在所述PPI结构上方，但不覆盖所述PPI结构的第一部分；以及保护层，形成在所述介电层上方，但不覆盖所述PPI结构的第一部分，其中，所述衬底包括导电区域；以及其中，所述焊料接合结构形成在所述PPI结构的第一部分和所述衬底的导电区域之间。
在该封装组件中，所述介电层包括氮化硅层。
在该封装组件中，所述PPI结构包括铜层或铜合金层。
该封装组件还包括：金属化层，位于所述焊料接合结构和所述PPI结构的第一部分之间。
在该封装组件中，所述金属化层包括含钛层和含铜层。
在该封装组件中，所述保护层包括聚合物层。
根据本发明的又一方面，提供了一种方法，包括：形成覆盖半导体衬底的第一聚合物层；形成覆盖所述第一聚合物层的互连层；在所述互连层的露出表面和所述第一聚合物层上方形成介电层；在所述介电层上方形成第二聚合物层；在所述第二聚合物层中形成开口以露出所述介电层的一部分；去除所述介电层的露出部分，以露出所述互连层的第一部分；以及在所述互连层的第一部分的上方形成凸块。
在该方法中，所述介电层包括氮化硅。
该方法还包括：在所述凸块和所述互连层的第一部分之间形成金属化层。
在该方法中，所述互连层包括铜。
附图说明
图1至图6是示出根据示例性实施例的形成具有钝化后互连(PPI)结构的半导体器件的方法的各个中间阶段的截面图；以及
图7是根据示例性实施例的封装组件的截面图。
具体实施方式
以下详细描述本公开内容的实施例的制造和使用。然而，应该理解，实施例提供了许多可以在各种具体环境中实现的可应用发明概念。所讨论的具体实施例仅仅是制造和使用实施例的具体方式而不限制公开内容的范围。本文所描述的实施例涉及用于半导体器件的凸块结构的使用。如以下所讨论的，公开了利用将一个衬底附接至另一衬底的凸块结构的实施例，其中，每个衬底都可以为管芯、晶圆、插入衬底、印刷电路板、封装衬底等，从而实现管芯与管芯、晶圆与管芯、晶圆与晶圆、管芯或晶圆与插入衬底或印刷电路板或封装衬底等的接合。在各个附图和所示实施例中，类似的参考标号用于指定类似的元件。
现在详细参照附图所示的示例性实施例的细节。在任何可能的情况下，在附图和说明书中使用相同的参考标号来表示相同或类似的部件。在附图中，为了清楚和方便可以放大形状和厚度。尤其将针对形成根据本公开的装置的一部分或者更加直接与该装置协作的元件来进行该描述。应该理解，没有具体示出或描述的元件可以采取本领域已知的各种形式。此外，当一层被称为位于另一层上方或位于衬底上方时，则其可以直接位于另一层或衬底上上方，或者可以存在中间层。本说明书中的“一个实施例”或“实施例”是指结合实施例描述的特定部件、结构或特性包括在至少一个实施例中。因此，本说明书中出现的“在一个实施例中”或“在实施例中”不是必须指相同的实施例。此外，可以在一个或多个实施例中以任何适当的方式组合特定部件、结构或特性。应该理解，以下附图没有按比例绘制，并且这些附图仅用于示意的目的。
图1至图6示出了根据一些实施例的形成半导体器件的方法的各个中间阶段。首先参照图1，根据一些实施例，示出了其上形成电路的衬底10的一部分。例如，衬底10可以包括掺杂或未掺杂的体硅、或者绝缘体上半导体(SOI)衬底的有源层。衬底10可以设置为晶圆级规模或芯片级规模。还可以使用其他衬底，诸如多层或梯度衬底。
形成在衬底10上的电路12可以为任何类型的适合于具体应用的电路。在一个实施例中，电路12包括形成在衬底10上方的电子器件，其中，一个或多个介电层覆盖电子器件。金属层可以形成在介电层之间，以在电子器件之间传送电信号。电子器件还可以形成在一个或多个介电层中。例如，电路12可以包括各种N型金属氧化物半导体(NMOS)和/或P型金属氧化物半导体(PMOS)器件，诸如晶体管、电容器、电阻器、二极管、光电二极管、熔丝等，互连这些器件以执行一个或多个功能。功能可以包括存储结构、处理结构、传感器、放大器、配电、输入/输出电路等。本领域的技术人员应该意识到，为了示意的目的提供了上述实例，以进一步解释一些示意性实施例的应用并且不以任何方式来限制本公开。可以针对给定应用适当使用其他电路。
在图1中还示出了层间介电(ILD)层14。例如，ILD层14可以通过任何适当的方法(诸如旋涂、化学汽相沉积(CVD)和/或等离子体增强CVD(PECVD))由低K介电材料(诸如磷硅玻璃(PSG)、硼磷硅玻璃(BPSG)、氟化硅玻璃(FSG)、SiOxCy、旋涂玻璃、旋涂聚合物、硅碳材料、其化合物、其合成物、其组合等)形成。在一些实施例中，ILD层14包括多个介电层。可以形成穿过ILD层14的接触件(未示出)以提供与电路12的电接触。
一个或多个金属间介电(IMD)层16以及相关的金属层形成在ILD层14的上方。通常，一个或多个IMD层16和相关的金属层(诸如金属线18和通孔19)用于使电路12互连并提供外部电连接。IMD层16可以由低K介电材料形成，诸如通过PECVD技术或高密度等离子体CVD(HDPCVD)等形成的FSG，并且可以包括中间蚀刻停止层。在一些实施例中，一个或多个蚀刻停止层(未示出)位于相邻的介电层(例如，ILD层14和IMD层16)之间。通常，蚀刻停止层提供当形成通孔和/接触件时停止蚀刻工艺的机构。蚀刻停止层由介电材料形成，其中，介电材料具有与相邻层(例如，下面的半导体衬底10、上面的ILD层14和上面的IMD层16)不同的蚀刻选择性。在一些实施例中，蚀刻停止层由通过CVD或PECVD技术沉积的SiN、SiCN、SiCO、CN、它们的组合等形成。
在一些实施例中，包括金属线18和通孔19的金属层由铜或铜合金或者其他金属形成。此外，金属化层包括在最上面的IMD层中或上方形成和图案化的顶部金属层20，以提供外部电连接并且保护下面的层免受各种环境污染。在一些实施例中，最上面的IMD层由介电材料形成，诸如氮化硅、氧化硅、未掺杂硅玻璃等。在后面的附图中，没有示出半导体衬底10、电路12、ILD层14以及金属化层18和19。在一些实施例中，顶部金属层20形成为最上面的IMD层上的顶部金属层的一部分。
此后，形成并图案化导电焊盘22以与顶部金属层20接触或者可选地经由通孔电连接至顶部金属层20。在一些实施例中，导电焊盘22由铝、铝铜、铝合金、铜、铜合金等形成。
参照图1，在导电焊盘22的上方形成并图案化诸如钝化层24的一个或多个钝化层。在一些实施例中，通过任何适当的方法(诸如CVD、PVD等)，钝化层24由介电材料形成，诸如未掺杂硅酸盐玻璃(USG)、氮化硅、氧化硅、氮氧化硅或非多孔材料。钝化层24被形成为覆盖导电焊盘22的外围部分，并通过钝化层24中的开口露出导电焊盘22的中间部分。钝化层24可以为单层或叠层。在图1中，仅为了说明的目的示出了导电焊盘22和钝化层24的单层。因此，其他实施例可以包括任何数量的导电层和/或钝化层。
接下来，在钝化层24的上方形成并图案化第一保护层26。在一些实施例中，例如，保护层26为聚合物层，将该保护层图案化以形成开口27，通过开口27露出导电焊盘22。在一些实施例中，聚合物层由诸如环氧树脂、聚酰亚胺、苯并环丁烯(BCB)、聚苯并恶唑(PBO)等的聚合物材料形成，但是还可以使用其他相对较软的有机介电材料。形成方法包括旋涂或其他方法。第一保护层26的厚度在大约1μm和大约10μm之间的范围内。例如，厚度在大约5μm和大约8μm之间。
参照图2，至少一个金属层形成在第一保护层26上方并填充开口27。然后，将至少一个金属层图案化为互连层28，该互连层电连接至导电焊盘22并且可以露出下面的第一保护层26的一部分。在至少一个实施例中，互连层28为钝化后互连(PPI)结构，该互连层还可以用作导线、再分布线(RDL)、电感器、电容器或任何无源部件。PPI结构28包括互连线区域28I和接合焊盘(landing pad)区域28P。在一些实施例中，互连线区域28I和接合焊盘区域28P同时形成，并且由相同的导电材料形成。在后续工艺中，凸块部件形成在接合焊盘区域28P的上方并且与其电连接。在一些实施例中，使用电镀、无电镀、溅射、化学汽相沉积方法等，PPI结构28可以包括铜、铝、铜合金或其它迁移率的导电材料。在一个实施例中，PPI结构28包括铜层或铜合金层。在图2的实施例中，接合区域28P不直接位于导电焊盘22的上方。在其他实施例中，通过PPI结构28的布线，接合焊盘区域28P直接位于导电焊盘22的上方。
参照图3，介电层34随后形成在整个表面上以覆盖PPI结构28和第一保护层26的露出部分。在一些实施例中，介电层34为氮化物层，例如，氮化硅层、氮氧化硅层等。在一些实施例中，介电层34用作抗氧化层以防止PPI结构28的表面在后续工艺期间被氧化，从而避免泄露并增加了器件可靠性。在一些实施例中，在后续蚀刻工艺期间，介电层34还用作蚀刻停止层。在一些实施例中，介电层34的厚度小于或等于大约3μm，例如，从大约0.1μm至大约3μm的厚度。介电层34的形成方法包括化学汽相沉积(CVD)工艺，诸如低压CVD工艺。
参照图4，第二保护层30随后形成在衬底10上方以覆盖介电层34。使用光刻和/或蚀刻工艺，第二保护层30被图案化以在PPI结构28的接合焊盘区域28P内形成露出介电层34的至少一部分的开口32a。开口32a的形成方法包括光刻、湿蚀刻或干蚀刻、激光钻孔等。在一些实施例中，第二保护层30由聚合物层形成，诸如环氧树脂、聚酰亚胺、苯并环丁烯(BCB)、聚苯并恶唑(PBO)等，但是还可以使用其他相对较软的有机介电材料。在一些实施例中，第二保护层30由非有机材料形成，其中，从未掺杂硅酸盐玻璃(USG)、氮化硅、氮氧化硅、氧化硅和它们的组合中选择该非有机材料。
接下来，如图5所示，去除露出的介电层34，使得开口32b露出接合焊盘区域28P的部分28P1。将蚀刻工艺用于通过自对准方式去除露出的介电层34。
如图6所示，在接合焊盘区域28P的露出部分28P1上方顺序形成凸块底部金属化(UBM)层35和凸块36。通过使用金属沉积、光刻和蚀刻方法在开口32b中形成UBM层35。UBM层35可以延伸到第二保护层30上方。在一些实施例中，UBM层35包括至少一个金属化层，其包括钛(Ti)、钽(Ta)、氮化钛(TiN)、氮化钽(TaN)、铜(Cu)、铜合金、镍(Ni)、锡(Sn)、金(Au)或它们的组合。在一些实施例中，UBM层35包括至少一个含Ti层和至少一个含Cu层。
凸块36可以为焊料凸块、Cu凸块或包括Ni或Au的金属凸块。在一些实施例中，凸块36为通过将焊球附接至开口32b中的UBM层35、然后热回流焊球形成的焊料凸块。在一些实施例中，焊料凸块包括无铅预焊料层、SnAg或者包括锡、铅、银、铜、镍、铋或它们的组合的合金的焊料材料。在一些实施例中，通过用光刻技术电镀焊料层然后进行回流工艺来形成焊料凸块。在一些实施例中，凸块36的直径为大约200μm至大约300μm。在其他实施例中，凸块36的直径为大约100μm至大约200μm。在又一些实施例中，凸块36的直径为大约50μm至大约100μm。在又一些实施例中，凸块36的直径为大约10μm至大约50μm。在一些实施例中，凸块36包括“微凸块”。
在凸块形成之后，可以形成密封剂，可以实施分切工艺来切割独立管芯，并且可以执行晶圆级或管芯级堆叠等。然而，应该注意，可以在许多不同的情况下使用实施例。例如，可以在管芯与管芯接合结构、管芯与晶圆接合结构、晶圆与晶圆接合结构、管芯级封装、晶圆级封装等中使用实施例。
图7是示出倒装组件300的示例性实施例的截面图。图6所示器件10上下翻转并附接至另一衬底200上。在一些实施例中，衬底200为封装衬底、板(例如，印刷电路板(PCB))、晶圆、管芯、插入衬底或其它适当的衬底。凸块结构通过各种导电附接点连接至衬底200。例如，在衬底100上形成并图案化导电区域202。导电区域202为接触焊盘或者导电迹线的一部分，通过掩模层204中的开口露出该导电区域。在一些实施例中，掩模层204为衬底200上形成并图案化的阻焊层以露出导电区域202。掩模层204具有掩模开口，该掩模开口提供用于焊点形成的窗。例如，可以在导电区域202上设置包括锡、铅、银、铜、镍、铋或它们的组合的合金的焊料层。在一些实施例中，器件100可以连接至衬底200以在接合焊盘区域28P和导电区域202之间形成接合结构206。在一些实施例中，接合结构206为焊料接合结构。例如，焊料接合结构可以通过包括焊剂应用、芯片放置、熔化焊点的回流和/或焊料残留的清洗的接合工艺来形成。器件100、接合结构206和衬底200可以称为封装组件300，或者在本实施例中为倒装芯片封装组件。
根据示例性实施例的一个方面，一种半导体器件包括：半导体衬底；钝化层，覆盖半导体衬底；互连层，覆盖钝化层；介电层，形成为覆盖互连层但不覆盖互连层的第一部分；保护层，形成为覆盖介电层但不覆盖互连层的第一部分；以及凸块，形成为覆盖互连层的第一部分并与互连层的第一部分电连接。在一些实施例中，介电层包括氮化硅层，并且互连层包括铜。
根据示例性实施例的另一方面，封装组件包括半导体器件，通过焊料接合结构电连接至衬底。半导体器件包括：钝化后互连(PPI)结构；介电层，形成在PPI结构上方但不覆盖PPI结构的第一部分；以及保护层，形成在介电层上方但不覆盖PPI结构的第一部分。衬底包括导电区域；以及焊料接合结构形成在PPI结构的第一部分与衬底的导电区域之间。
根据示例性实施例的其他方面，一种方法包括：形成覆盖半导体衬底的第一聚合物层；形成覆盖第一聚合物层的互连层；在互连层和第一聚合物层的露出表面上方形成介电层；在介电层上方形成第二聚合物层；在第二聚合物层中形成开口以露出介电层的一部分；去除介电层的露出部分以露出互连层的第一部分；以及在互连层的第一部分的上方形成凸块。
在前面的详细描述中，参照其具体示例性实施例描述了本公开内容。然而，应该明白，在不背离本公开内容的精神和范围的情况下可以进行各种修改、结构、工艺和变化。因此，说明书和附图被认为是示意性而不是限制性的。应该理解，本公开内容能够使用各种其他组合情况以及能够在本文所揭示发明概念的范围内进行改变或修改。

Claims (10)

1.一种半导体器件，包括：
半导体衬底；
钝化层，覆盖所述半导体衬底；
互连层，覆盖所述钝化层；
介电层，形成为覆盖所述互连层但不覆盖所述互连层的第一部分，其中，所述介电层包括氮化物；
保护层，形成为覆盖所述介电层但不覆盖所述互连层的第一部分；以及
凸块，形成为覆盖所述互连层的第一部分并与所述互连层的第一部分电连接。
2.根据权利要求1所述的半导体器件，其中，所述介电层包括氮化硅层。
3.根据权利要求1所述的半导体器件，还包括：金属化层，位于所述凸块和所述互连层的第一部分之间。
4.根据权利要求3所述的半导体器件，其中，所述金属化层包括含钛层和含铜层。
5.根据权利要求1所述的半导体器件，其中，所述保护层包括聚合物层。
6.根据权利要求1所述的半导体器件，其中，所述互连层包括铜层或铜合金层。
7.根据权利要求1所述的半导体器件，还包括：另一保护层，位于所述互连层和所述钝化层之间。
8.根据权利要求7所述的半导体器件，其中，所述另一保护层包括聚合物层。
9.一种封装组件，包括通过焊料接合结构电连接至衬底的半导体器件，
其中，所述半导体器件包括：
钝化后互连(PPI)结构；
介电层，形成在所述PPI结构上方，但不覆盖所述PPI结构的第一部分；以及
保护层，形成在所述介电层上方，但不覆盖所述PPI结构的第一部分，
其中，所述衬底包括导电区域；以及
其中，所述焊料接合结构形成在所述PPI结构的第一部分和所述衬底的导电区域之间。
10.一种方法，包括：
形成覆盖半导体衬底的第一聚合物层；
形成覆盖所述第一聚合物层的互连层；
在所述互连层的露出表面和所述第一聚合物层上方形成介电层；
在所述介电层上方形成第二聚合物层；
在所述第二聚合物层中形成开口以露出所述介电层的一部分；
去除所述介电层的露出部分，以露出所述互连层的第一部分；以及
在所述互连层的第一部分的上方形成凸块。
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