CN106409803A - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN106409803A
CN106409803A CN201610023690.1A CN201610023690A CN106409803A CN 106409803 A CN106409803 A CN 106409803A CN 201610023690 A CN201610023690 A CN 201610023690A CN 106409803 A CN106409803 A CN 106409803A
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layer
semiconductor device
chip
dielectric
hard mask
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CN106409803B (zh
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施信益
吴铁将
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Micron Technology Inc
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Inotera Memories Inc
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Abstract

本发明公开了一种半导体装置，包含一芯片，具有一有源面以及一相对于所述有源面的背面；一模塑料，覆盖并包覆所述芯片；以及一重分布层，设于所述有源面以及所述模塑料上，其中所述重分布层是与所述芯片电连接，所述重分布层包含至少一有机介电层以及一无机介电硬掩膜层，设于所述有机介电层上，其中所述重分布层还包含一金属结构，设于所述有机介电层以及所述无机介电硬掩膜层中。

Description

半导体装置
技术领域
本发明是有关于半导体装置，特别是有关于具有细密间距重分布层(redistribution layer,RDL)的半导体装置的晶圆级封装(wafer-level packaging,WLP)及其制作方法。
背景技术
半导体封装领域中所熟知的扇出晶圆级封装(FOWLP)，是通过位于基底上的重分布层(RDL)，例如位于具有穿硅通孔(TSV)的基底，将原本半导体晶粒的接垫重新布线分配至一较大的区域。
重分布层是在晶圆表面上形成介电层与金属导线的叠层，将芯片原本的输入/输出(I/O)接垫重新布线分配至一个间距较宽松的布局范围。上述重布线的制作通常使用薄膜聚合物，例如苯并环丁稀(benzocyclobutene,BCB)、聚亚酰胺(polyimind,PI)，或其他有机聚合物作为介电层材料，再以金属化工艺，例如铝或铜，形成金属导线，将芯片周围的接垫重新布线分配成阵列状连接垫。
晶圆级封装工艺中，通常会在晶圆及安装在晶圆上的芯片表面覆盖一相对较厚的模塑料。此模塑料与集成电路基底的热膨胀系数(CTE)差异，易导致封装翘曲变形，也使得封装整体的厚度增加。晶圆翘曲一直是本技术领域关注的问题。
晶圆翘曲使芯片与晶圆间的接合不易维持，易导致“芯片对晶圆接合”(chip to wafer)的组装失败。翘曲问题在大尺寸晶圆上更是明显，特别是对于具有小间距重分布层的晶圆级半导体封装制，问题更为严重。因此，本技术领域仍需要一个改良的晶圆级封装方法，可以解决上述先前技术的问题。
发明内容
本发明主要目的在提供一种改良的半导体装置，可实现细密间距重分布层，并且避免上述先前技术的翘曲问题。
根据本发明实施例，提供一种半导体装置，包含一芯片，具有一有源面以及一相对于所述有源面的背面；一模塑料，覆盖并包覆所述芯片；以及一重分布层，设于所述有源面以及所述模塑料上，其中所述重分布层是与所述芯片电连接，所述重分布层包含至少一有机介电层以及一无机介电硬掩膜层，设于所述有机介电层上，其中所述重分布层还包含一金属结构，设于所述有机介电层以及所述无机介电硬掩膜层中。
毋庸置疑的，本领域的技术人士读完接下来本发明优选实施例的详细说明与附图后，均可了解本发明的目的。
附图说明
图1至图10为依据本发明一实施例所绘示的制作一具有细密间距重分布层的晶圆级封装的方法示意图。
其中，附图标记说明如下：
1 晶圆级封装
10 晶粒
20 模塑料
30 重分布层
102 凸块
301 载板
302 黏着层
311 有机介电层
311' 图案化的有机介电层
311a 开口
312 无机介电硬掩膜层
312' 图案化硬掩膜
312a 开口
320 光刻胶图案
320a 开口
330 金属结构
410 多层介电堆叠结构
411 有机介电层
412 无机介电硬掩膜层
413 有机介电层
414 无机介电硬掩膜层
430 金属结构
431 金属导线结构
432 金属介层插塞结构
502 金属层
504 锡球
M1 第一金属层
M2 第二金属层
V1 金属介层插塞结构
具体实施方式
接下来的详细说明及叙述，参照相关附图所示内容，共同用来说明可依据本发明而具体实行的实施例。这些实施例已提供足够的细节，使本技术领域中的技术人员能充分了解并具体实行本发明。在不悖离本发明的范围内，可做结构、逻辑和电性上的修改，而应用在其他实施例上。
因此，接下来的详细说明并非用来对本发明加以限制。本发明涵盖的范围由其权利要求界定。与本发明权利要求具同等意义者，也应属本发明涵盖的范围。
本发实施例所参照的附图为示意图，并未按比例绘制，且相同或类似的特征通常以相同的附图标记说明。在本说明书中，“晶粒”、“半导体芯片”与“半导体晶粒”具相同含意，可交替使用。
在本说明书中，“晶圆”与“基板”意指任何包含一暴露面，可依据本发明实施例所示在其上沉积材料，制作集成电路结构的结构物，例如重分布层。须了解的是“基板”包含半导体晶圆，但并不限于此。"基板"在工艺中也意指包含制作于其上的材料层的半导体结构物。
请参阅图1至图10，其为依据本发明一实施例所绘示的制作一具有细密间距重分布层的晶圆级封装的方法示意图。
如图1所示，预备一载板301。载板301例如为可卸式基底材料。载板301上表面可以包含一黏着层302。在一实施例中，载板301可以是一玻璃基板，但是也可以是一晶圆、半导体、金属、合成物、或其他具有合适表面特性及结构刚性的材料。在一实施例中，黏着层302可以是一胶带，或者可以是以一旋涂工艺施加在载板301上的一胶层或环氧树指。
如图2所示，接着于黏着层302上形成至少一有机介电层311。根据本发明实施例，有机介电层311可以包含聚亚酰胺(polyimide,PI)、苯并环丁烯(benzocyclobutene,BCB)、聚苯恶唑(polybenzoxazole PBO)或其他有机绝缘材料。接着在有机介电层311上沉积一无机介电硬掩膜层312。根据本发明实施例，无机介电硬掩膜层312可以包含二氧化硅、氮化硅、氮氧化硅、碳化硅、磷硅玻璃、硼磷硅玻璃或其他无机材料，其相对于下方的有机介电层311具有高蚀刻选择比。
接着，在无机介电硬掩膜层312上形成一光刻胶图案320。光刻胶图案320可以利用公知的光刻工艺形成，包括，但不限于，光刻胶涂布、烘烤、曝光、显影等等步骤。光刻胶图案320包括开口320a，其显露出无机介电硬掩膜层312上预定被蚀刻的区域。
如图3所示，接着进行一干蚀刻工艺，经由光刻胶图案320的开口320a蚀刻无机介电硬掩膜层312被显露出来的区域，如此将光刻胶图案320的线路图案转移至无机介电硬掩膜层312。接着，将剩下的光刻胶图案320去除。此时，形成一图案化硬掩膜312’。图案化硬掩膜312’具有开口312a，显露出有机介电层311上预定被蚀刻的区域。
如图4所示，利用图案化硬掩膜312’作为蚀刻掩膜，进行一干蚀刻工艺，经由开口312a蚀刻显露出的有机介电层311上预定被蚀刻的区域，借此将图案化硬掩膜312’中的线路图案转移至有机介电层311中。如图4所示，在图案化的有机介电层311’中形成开口311a。这些开口311a显露出部分的黏着层302。
如图5所示，接着在开口311a中形成金属结构330。金属结构330可以包含微细间距的介层插塞或金属导线，但不限于此。举例来说，要形成金属结构330，可以先在开口311a中以及图案化的有机介电层311’上沉积一导电材料，例如，氮化钛、钛、钨、铜、铝等等，再进行一抛光工艺，例如，化学机械研磨(CMP)工艺，去除开口311a以外多余的导电材料。在CMP工艺过程中，图案化的有机介电层311’可以做为一研磨停止层。此时，即完成重分布层的第一金属层(M1)。
如图6所示，接着可选择在重分布层的第一金属层(M1)上形成一多层介电堆叠结构410，其中多层介电堆叠结构410，如同前面所说明，同样包含交替层叠的有机介电材料及无机介电材料。举例来说，多层介电叠结构410可以包含一有机介电层411，覆盖在金属结构330以及图案化硬掩膜312’上，一无机介电硬掩膜层412，直接设于有机介电层411上，一有机介电层413，直接设于无机介电硬掩膜层412上，以及一无机介电硬掩膜层414，直接设于有机介电层413上。
形成多层介电堆叠结构410之后，可以重复图2至图5中所说明的步骤，于多层介电堆叠结构410中形成金属结构430。例如，金属结构430可以利用铜双镶嵌工艺，于有机介电层413及无机介电硬掩膜层414中形成一金属导线结构431(第二金属层或M2)，于有机介电层411及无机介电硬掩膜层412中形成一金属介层插塞结构432(V1)，电连接金属导线结构431与重分布层30的第一金属层(M1)。应理解的是，重分布层30可以包含更多金属层，例如，M3、M4，可以利用前面所述的相同方法制作。
如图7所示，接着于重分布层30上安装半导体芯片或晶粒10，如此构成一芯片至晶圆(chip-to-wafer,C2W)堆叠架构。举例来说，半导体芯片或晶粒10可以利用公知的表面黏着技术而设置固定在重分布层30上，但不限于此。为了构成芯片与重分布层30之间的电连结，在芯片10下方可以设有多个凸块102，例如，微凸块(micro-bumps)或铜柱。之后，可选择进行一热工艺，使凸块102回流焊。
如图8所示，在完成芯片接合后，接着形成一模塑料20。模塑料20覆盖并包覆芯片10，并覆盖重分布层30的上表面。之后，可以对模塑料20进行一固化工艺。
根据本发明实施例，例如，模塑料20可以利用转移成型模压法，以热固性树脂化合物构成。当然，也可以利用其他方法形成模塑料20。在升高温度下或室温下呈液体的环氧树脂及化合物亦可被采用。上述模塑料20是一绝缘材料，且可以是热导体。可以通过添加不同的填充材料，改善模塑料20的导热性、刚性或黏着特性。
如图9所示，在形成模塑料20，接着去除或剥除载板301以及黏着层302，藉此显露出重分布层30的底面。
如图10所示，接着进行一晶圆切割工艺，可以沿着晶圆上的切割道进行切割，分隔出个别的晶圆级封装1。在重分布层30的底面上，可以继续形成一绝缘层(图未示)以及一金属层502。然后在金属层502上可以继续形成焊锡凸块或锡球504，以供后续连接使用。本领域技术人员应理解图中所示剖面仅为例示说明。图中某些介电层或钝化层可能被省略。举例来说，在某些实施例中，可以在无机介电硬掩膜层414上设置一钝化层，并且在图案化的有机介电层311’下方可以再设置一钝化层。
以上所述仅为本发明的优选实施例而已，并不用于限制本发明，对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (9)

1.一种半导体装置，其特征在于，包含:
一芯片，具有一有源面以及一相对于所述有源面的背面；
一模塑料，覆盖并包覆所述芯片；以及
一重分布层，设于所述有源面以及所述模塑料上，其中所述重分布层是与所述芯片电连接，所述重分布层包含至少一有机介电层以及一无机介电硬掩膜层，设于所述有机介电层上，其中所述重分布层还包含一金属结构，设于所述有机介电层以及所述无机介电硬掩膜层中。
2.根据权利要求1所述的半导体装置，其特征在于，位于所述有机介电层以及所述无机介电硬掩膜层内的所述金属结构构成所述重分布层的一第一金属层。
3.根据权利要求2所述的半导体装置，其特征在于，在所述无机介电硬掩膜层与所述金属结构上，还包括一多层介电堆叠结构，所述多层介电堆叠结构包含交替层叠的有机介电材料及无机介电材料。
4.根据权利要求3所述的半导体装置，其特征在于，于所述多层介电堆叠结构中，具有一金属导线结构以及一金属介层插塞结构。
5.根据权利要求4所述的半导体装置，其特征在于，所述金属导线结构构成所述重分布层的一第二金属层。
6.根据权利要求1所述的半导体装置，其特征在于，所述有机介电层包含聚亚酰胺、苯并环丁烯或聚苯恶唑。
7.根据权利要求1所述的半导体装置，其特征在于，所述无机介电硬掩膜层包含二氧化硅、氮化硅、氮氧化硅、碳化硅、磷硅玻璃、或硼磷硅玻璃。
8.根据权利要求1所述的半导体装置，其特征在于，所述重分布层是通过多个凸块与所述芯片电连接。
9.根据权利要求1所述的半导体装置，其特征在于，所述重分布层是通过多个铜柱与所述芯片电连接。
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