CN102254897A - 具有中介层的封装系统 - Google Patents

具有中介层的封装系统 Download PDF

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Publication number
CN102254897A
CN102254897A CN2010102949520A CN201010294952A CN102254897A CN 102254897 A CN102254897 A CN 102254897A CN 2010102949520 A CN2010102949520 A CN 2010102949520A CN 201010294952 A CN201010294952 A CN 201010294952A CN 102254897 A CN102254897 A CN 102254897A
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China
Prior art keywords
layer
integrated circuit
mold compound
compound layer
electric connection
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CN2010102949520A
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CN102254897B (zh
Inventor
林咏淇
林俊成
余振华
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种封装系统，包括设置在中介层之上的第一集成电路。该中介层包括至少一个模制化合物层，其包括通过该至少一个模制化合物层的多个电连接结构。第一互连结构设置在该至少一个模制化合物层的第一表面之上并与多个电连接结构电连接。第一集成电路与第一互连结构电连接。

Description

具有中介层的封装系统
技术领域
本发明总的来说涉及半导体封装系统领域，尤其涉及具有中介层(interposer)的封装系统。
背景技术
由于集成电路的发明，半导体工业经历了由于多种电子组件(例如，晶体管、二极管、电阻器、电容器等)集成密度的连续改进而导致的持续快速发展。在很大程度上来说，集成密度的这种改进源自最小部件尺寸的重复减小，从而允许更多组件集成到给定区域。
这些集成改进本质上是二维的(2D)，这是因为集成组件所占用的体积基本上在半导体晶片(wafer)的表面上。虽然光刻的大幅度改善已经导致2D集成电路形成方面相当大的改进，但是还存在对二维可以实现的密度的物理限制。这些限制之一为制造这些组件所需的最小尺寸。而且，当更多的器件被放到一个芯片中时，要求更复杂的设计。
附加限制源于随着器件数量的增加而导致器件之间互连的数量和长度的显著增加。当互连的数量和长度增加时，电路电阻-电容(RC)延迟和功耗增加。
因此，产生三维集成电路(3D IC)来解决上述限制。在传统的3D IC形成处理中，形成两个晶片，每个晶片均包括集成电路。然后，晶片与对准的器件结合。然后，形成深通孔以互连第一和第二晶片上的器件。
已经使用3D IC技术实现了更高的器件密度，并且已经结合了多达六层的晶片。结果，显著减小了总布线长度。还减小了通孔的数量。从而，3D IC技术具有作为下一代主流技术的潜力。
用于形成3D IC的传统方法还包括管芯-晶片结合，其中，独立的管芯(die)被结合至公共晶片。管芯-晶片结合的优点在于，管芯的尺寸可以小于晶片上的芯片的尺寸。
近来，被称为晶片通孔的硅通孔(TSV)越来越多地被用作实现3D IC的方式。通常，底部晶片被结合至顶部晶片。两种晶片都包括衬底之上的集成电路。底部晶片中的集成电路通过互连结构被连接至晶片中的集成电路。晶片中的集成电路通过硅通孔被进一步连接至外部焊盘。堆叠的晶片可以经过切割处理，以提供多个堆叠的晶片结构。
发明内容
根据本发明的一个方面，提供了一种封装系统，包括中介层，该中介层包括：至少一个模制化合物层，包括多个通过至少一个模制化合物层的多个电连接结构；和第一互连结构，设置在至少一个模制化合物层的第一表面之上并与多个电连接结构电连接，该封装系统还包括第一集成电路，设置在中介层之上，第一集成电路与第一互连结构电连接。
优选地，多个电连接结构被设置为径直通过至少一个模制化合物层。
此外，中介层还包括：第二互连结构，设置在至少一个模制化合物层的与第一表面相对的第二表面之下。
优选地，第二互连结构的金属线间距大于第一互连结构的金属线间距。
此外，该系统还包括：第二集成电路，与第一互连结构电连接，其中，至少一个模制化合物层被设置为至少部分地在第二集成电路的至少一个侧边周围。
优选地，第二集成电路被设置在至少一个模制化合物层内。
此外，中介层还包括：多个阻挡结构，每一个均被设置为至少部分地在多个电连接结构中的一个的至少一个侧边周围。
该系统还包括：覆盖层，覆盖第一集成电路，其中，覆盖层的热膨胀系数(CTE)基本等于至少一个模制化合物层的CTE。
根据本发明的第二方面，提供了一种封装系统，包括中介层，该中介层包括：至少一个模制化合物层，包括径直通过至少一个模制化合物层的多个电连接结构；第一互连结构，设置在至少一个模制化合物层的第一表面之上并与多个电连接结构电连接；和第二互连结构，设置在至少一个模制化合物层的与第一表面相对的第二表面之下，该系统还包括第一集成电路，设置在中介层之上，第一集成电路与第一互连结构电连接。
优选地，第二互连结构的金属线间距大于第一互连结构的金属线间距。
此外，该系统还包括：第二集成电路，与第一互连结构电连接，其中，至少一个模制化合物层被设置为至少部分地在第二集成电路的至少一个侧边周围。
优选地，第二集成电路设置在至少一个模制化合物层内。
此外，中介层还包括：多个阻挡结构，每一个均被设置为至少部分地在多个电连接结构的至少一个侧边周围。
封装系统还包括：覆盖层，覆盖第一集成电路，其中，覆盖层的热膨胀系数(CTE)基本等于至少一个模制化合物层的CTE。
根据本发明的又一方面，提供了一种封装系统，包括中介层，该中介层包括：至少一个模制化合物层，包括通过至少一个模制化合物层的多个电连接结构，其中，至少一个模制化合物层具有第一热膨胀系数(CTE)；和第一互连结构，设置在至少一个模制化合物层的第一表面之上并与多个电连接结构电连接。该系统还包括：第一集成电路，设置在中介层之上，第一集成电路与第一互连结构电连接；底部填充材料，设置在中介层和第一集成电路之间，其中，底部填充材料具有第二CTE，并且第二CTE基本等于第一CTE；以及覆盖层，设置在中介层之上，覆盖层覆盖第一集成电路，其中，覆盖层具有第三CTE，并且第三CTE基本等于第一CTE。
优选地，多个电连接结构被设置成径直通过至少一个模制化合物层。
此外，中介层还包括：第二互连结构，设置在至少一个模制化合物层的与第一表面相对的第二表面之下，其中，第二互连结构的金属线间距大于第一互连结构的金属线间距。
该封装系统还包括：第二集成电路，与第一互连接结构电连接，其中，至少一个模制化合物层被设置为至少部分地在第二集成电路的至少一个侧边周围。
优选地，第二集成电路设置在至少一个模制化合物层内。
中介层还包括：多个阻挡结构，每一个均被设置为至少部分地在多个电连接结构中的一个的至少一个侧边周围。
附图说明
当读取附图时，本公开可以从以下详细描述最好地理解。需要强调的是，根据工业中的常规作法，多个部件不按比例绘制并且仅用于说明目的。事实上，为了论述的清楚，多种部件的数量和尺寸可以任意增加或减少。
图1是第一示例性封装系统的示意性截面图。
图2是第二示例性封装系统的示意性截面图。
图3是第三示例性封装系统的示意性截面图。
图4是第四示例性封装系统的示意性截面图。
图5A至图5L是示出形成类似于图1所示中介层的示例性中介层的示例性方法的示意性截面图。
图6A至图6E是示出可以选择性地替换图5E至图5J所示的所有或一些处理步骤以形成类似于图3所示中介层310的结构的多个处理步骤的示意性截面图。
图7是示出包括设置在衬底之上的示例性封装系统的系统的示意图。
具体实施方式
通常，封装系统具有设置在硅管芯和有机衬底之间的硅中介层。硅中介层具有用于硅管芯和有机衬底之间的电连接的多个硅通孔(TSV)结构。TSV结构的形成包括多种处理，诸如TSV蚀刻处理，阻挡/种子层沉积处理、电镀铜处理、用于去除部分铜层和阻挡/种子层的化学机械抛光(CMP)处理和/或其他半导体处理。在硅中介层中形成TSV结构增加了制造封装系统的成本。发现覆盖硅管芯的聚酰亚胺覆盖层被设置在硅中介层之上。申请人还发现，热膨胀系数(CTE)失配存在于聚酰亚胺覆盖层与硅中介层之间，可能导致至少在组装处理和/或可靠性测试期间硅管芯的金属间电介质(IMD)层分层和/或凸块(bump)故障。
基于上面所述，期望用于集成电路的封装系统。
应该明白，以下公开内容提供了许多不同的实施例或实例，用于实现本发明的不同特征。以下描述组件和配置的特定实例以简化本公开。当然，这些仅仅是实例并且不用于限制本发明。另外，本公开可以在各个实例中重复使用参考标号和/或字母。这种重复仅用于简单和清楚的目的，并且其本身不表示所述的各个实施例和/或配置之间的关系。此外，在以下公开中的一个部件形成在另一个部件上、与其连接和/或耦合可以包括部件直接接触形成的实施例，并且还可以包括可插入部件之间形成的附加部件的实施例，使得部件可以不直接接触。另外，诸如“上”、“下”、“水平”、“垂直”、“之上”、“之下”、“向上”、“向下”、“顶部”和“底部”等的空间相对术语及其派生词(例如，“水平地”、“向下地”、“向上地”等)便于披露一个部件与另一个部件的关系。空间相对术语覆盖包括多个部件的器件的不同方位。
图1是第一示例性封装系统的示意性截面图。在图1中，封装系统可以包括至少一个设置在中介层110之上的集成电路，例如集成电路120。集成电路120可以与中介层110电连接。在一些实施例中，覆盖层130可以设置在中介层110之上并覆盖集成电路120。
在一些实施例中，中介层110可包括至少一个模制化合物层，例如模制化合物层113。模制化合物层113可以包括多个电连接结构，例如电连接结构115。电连接结构115可以通过模制化合物层113设置。互连结构117可以设置在模制化合物层113的表面113a之上并与电连接结构115电连接。在一些实施例中，中介层110可以包括至少一个无源器件，例如电容器、电阻器和/或电感器。在其他实施例中，中介层110可以基本不包括任何有源器件，例如金属氧化物半导体(MOS)晶体管、双极结晶体管(BJT)、互补MOS(CMOS)晶体管等。在又一些其他实施例中，中介层110不包括任何有源器件和无源器件。中介层110可以仅被配置用于提供电连接。虽然在图1中仅示出一个模制化合物层113，但本申请的范围不限于此。在其他实施例中，可以使用两个以上的模制化合物层。
在一些实施例中，模制化合物层113可以由至少一种材料制成，诸如基于聚合物的材料。术语“聚合物”可以表示热固性聚合物、热塑性聚合物或任何它们的混合。例如，基于聚合物的材料可包括塑性材料、环氧树脂、聚酰亚胺、聚对苯二甲酸乙二醇酯(PET)、聚氯乙烯(PVC)、聚甲基丙烯酸甲酯(PMMA)、掺杂有特定填充物(包括纤维、黏土、陶瓷、无机颗粒或它们的任何组合)的聚合物组成。在其他实施例中，模制化合物层113可以由环氧树脂制成，诸如甲酚环氧树脂(ECN)、联苯环氧树脂、多功能液晶环氧树脂或任何它们的组合。在又一些其他实施例中，模制化合物层113可由可选地包括一种或多种填充物以提供具有多种期望性能中的任何一种的组成的环氧树脂制成。填充物的实例可以为铝、二氧化钛、炭黑、碳酸钙、高岭土、云母、硅石、滑石、木粉或任何它们的组合。
在一些实施例中，电连接结构115可设置成通过模制化合物层113。例如，电连接结构115可以从模制化合物层113的表面113b连续延伸至表面113a。在其他实施例中，电连接结构115可以被设置为径直通过模制化合物层113。在又一些其他实施例中，至少一个电连接结构115可以在模制化合物层113中具有一个或多个转弯(turn)。电连接结构115的每一个均可以为线、柱、层、一个或多个几何结构或任何它们的组合。
在一些实施例中，电连接结构115可以与多个连接器(例如，凸块135)电连接。在一些实施例中，电连接结构115可以由至少一种材料制成，诸如导电材料(铝、铜、铜铝、多晶硅、其他导电材料和/或任何它们的组合)、适于形成电连接结构115的其他材料和/或它们的组合。
在一些实施例中，互连结构117可包括至少一个电介质层，至少一个电连接结构以及钝化层(未标记)。在一些实施例中，互连结构117可以包括多个电介质层和多层电连接结构。电连接结构的每一层都可以由两个电介质层夹着。在一些实施例中，电介质层和导电结构可以被配置成形成各种无源器件，例如电容器、电阻器和/或电感。
在一些实施例中，电介质层(未标记)可包括至少一种材料，诸如氧化硅、氮化硅、氮氧化硅、低k电介质材料、超低k电介质材料、一种或多种电介质材料或任何它们的组合。电连接结构可包括至少一种结构，诸如通孔插塞、接触插塞、镶嵌结构、双镶嵌结构、金属区、金属线或任何它们的组合。通孔插塞、接触插塞、镶嵌结构、双镶嵌结构、金属区以及金属线(未标记)可以由至少一种材料制成，诸如钨、铝、铜、钛、钽、氮化钛、氮化钽、镍硅化物、钴硅化物、其他合适的导体材料和/或它们的组合。在一些实施例中，至少一种电连接结构可以被称为再分配层(RDL)。
在一些实施例中，互连结构117可包括可以设置在互连结构117的表面上的至少一个焊盘(未标记)。至少一个连接器(诸如凸块125)中的每一个均可以设置在其相应焊盘之上用于与集成电路120的电连接。至少一个焊盘可以由至少一种材料制成，诸如铜(Cu)、铝(Al)、铝铜(AlCu)、铝硅铜(AlSiCu)、或其他导电材料或它们的多种组合。在一些实施例中，至少一个焊盘可包括凸块底层金属(UBM)层。
在一些实施例中，凸块125和135均可以包括至少一种材料，诸如无铅合金(例如，金(Au)、锡/银/铜(Sn/Ag/Cu)合金或其他无铅合金)、含铅合金(例如，铅/锡(Pb/Sn)合金)、铜、铝、铝铜、导电聚合物、其他凸块金属材料或任何它们的组合。通过使用中介层110，凸块125的间距可以通过互连结构117和/或模制化合物层113扩展至凸块135的间距。
再次参考图1，集成电路120可设置在中介层110之上。集成电路120可通过凸块125和互连结构117与电连接结构115电连接。集成电路120可包括至少一个有源器件，例如晶体管、MOS晶体管、BJT、COMS晶体管、其他有源器件或者任何它们的组合。在一些实施例中，集成电路120可包括衬底121和互连结构123。互连结构123可设置为与衬底121的表面相邻。虽然仅示出设置在中介层110之上的单个集成电路120，但本发明的范围不限于此。在一些实施例中，两个以上的集成电路可以水平分离和/或垂直堆叠在中介层110之上。
在一些实施例中，衬底121可以由基本半导体制成，包括晶体、多晶或无定形结构的硅或锗；可以由化合物半导体制成，包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和锑化铟；可以由合金半导体制成，包括SiGe、GaAsP、AlInAs、AlGaAs、GaInP和GaInAsp；可以由其他合适的材料制成；或者可以由它们的组合制成。在一个实施例中，合金半导体衬底可具有梯度SiGe部件，其中，Si和Ge成分从梯度SiGe部件的一个位置的一个比率变为另一个位置的另一比率。在另一实施例中，合金SiGe形成在硅衬底之上。在另一实施例中，SiGe衬底被扭曲(strained)。此外，半导体衬底可以为绝缘体上半导体，诸如绝缘体上硅(SOI)。在一些实例中，半导体衬底可包括掺杂的外延层或埋层。在其他实例中，化合物半导体衬底可具有多层结构，或者衬底可包括多层化合物半导体结构。
在一些实施例中，互连结构123可包括至少一个电介质层、至少一个电连接结构以及至少一个钝化层。在一些实施例中，互连结构123可包括多个电介质层和多层电连接结构。电连接结构的每一层均可以由电介质层夹着。在一些实施例中，电介质层和导电结构可以被配置成形成各种无源器件，例如电容器、电阻器和/或电感。
在一些实施例中，电介质层(未标记)可包括至少一种材料，诸如二氧化硅、氮化硅、氮氧化硅、低k电介质材料、超低k电介质材料、一种或多种其他电介质材料或任何它们的组合。电连接结构可包括至少一种结构，诸如通孔插塞、接触插塞、镶嵌结构、双镶嵌结构、金属区、金属线、或任何它们的组合。通孔插塞、接触插塞、镶嵌结构、双镶嵌结构、金属区、金属线(未标记)可由至少一种材料制成，诸如钨、铝、铜、钛、钽、氮化钛、氮化钽、镍硅化物、钴硅化物、其他合适的导体材料和/或它们的结合。
在一些实施例中，互连结构123可包括可设置为与互连结构123的表面邻近的至少一个焊盘(未标记)。至少一个焊盘可由至少一种材料制成，诸如铜(Cu)、铝(Al)、铝铜(AlCu)、铝硅铜(AlSiCu)、或其他导电材料或它们的各种组合。在一些实施例中，至少一个焊盘可包括凸块底层金属(UBM)层。
在一些实施例中，中介层110可选择性地包括至少一种钝化结构，例如，钝化结构119。钝化结构119可设置在模制化合物层113的表面113b之下。在一些实施例中，钝化结构119可包括至少一个电介质层和/或至少一个钝化层。
在一些实施例中，底部填充材料127可设置在中介层110和集成电路120之间。底部填充材料127可由至少一种材料制成，诸如基于聚合物的材料。术语“聚合物”可表示热固性聚合物，热塑性聚合物或任何它们的混合物。例如，基于聚合物的材料可包括塑性材料、环氧树脂、聚酰亚胺、聚对苯二甲酸乙二醇酯(PET)、聚氯乙烯(PVC)、聚甲基丙烯酸甲酯(PMMA)、掺杂有特定填充物(包括纤维、黏土、陶瓷、无机颗粒或它们的任何组合)的聚合物组成。在其他实施例中，底部填充材料127可以由环氧树脂制成，诸如甲酚环氧树脂(ECN)、联苯环氧树脂、多功能液晶环氧树脂或任何它们的组合。在又一些其他实施例中，底部填充材料127可以由选择性地包括一种或多种填充物以提供具有多种期望性能中的任何一种的组成的环氧树脂制成。填充物的实例可以为铝、二氧化钛、炭黑、碳酸钙、高岭土、云母、硅石、滑石、木粉或任何它们的组合。
在一些实施例中，底部填充材料127的膨胀系数(CTE)可以基本等于模制化合物层113的CTE。语句“底部填充材料127的CTE可以基本等于模制化合物层113的CTE”可以表示底部填充材料127和模制化合物层113之间的CTE失配不导致至少在装配处理和/或可靠性测试期间集成电路120的金属间电介质(IMD)层分层和/或凸块125故障。
参考图1，覆盖层130可设置在中介层110之上并覆盖集成电路120。覆盖层130可以由至少一种材料制成，诸如基于聚合物的材料。术语“聚合物”可表示热固性聚合物，热塑性聚合物或任何它们的混合物。例如，基于聚合物的材料可包括塑性材料、环氧树脂、聚酰亚胺、聚对苯二甲酸乙二醇酯(PET)、聚氯乙烯(PVC)、聚甲基丙烯酸甲酯(PMMA)、掺杂有特定填充物(包括纤维、黏土、陶瓷、无机颗粒或它们的任何组合)的聚合物组成。在其他实施例中，覆盖层130可以由环氧树脂制成，诸如甲酚环氧树脂(ECN)、联苯环氧树脂、多功能液晶环氧树脂或任何它们的组合。在又一些其他实施例中，覆盖层130可以由选择性地包括一种或多种填充物以提供具有多种期望性能中的任何一种的组成的环氧树脂制成。填充物的实例可以为铝、二氧化钛、炭黑、碳酸钙、高岭土、云母、硅石、滑石、木粉或任何它们的组合。
在一些实施例中，覆盖层130的膨胀系数(CTE)可以基本等于模制化合物层113的CTE。语句“覆盖层130的CTE可以基本等于模制化合物层113的CTE”可以表示覆盖层130和模制化合物层113之间的CTE失配不导致至少在装配处理和/或可靠性测试期间集成电路120的低k金属间电介质(IMD)层分层和/或凸块125故障。
图2是第二示例性实施例的示意性截面图。图2与图1中相同或相似的项由相同的参考标号加100来表示。在图2中，封装系统200可包括在模制化合物层213的表面213b之下的互连结构240。在一些实施例中，互连结构240的金属线间距可以大于互连结构217的金属线间距。互连结构217的金属线间距可以被扩展至互连结构240的金属线间距。
在一些实施例中，互连结构240可包括至少一个电介质层、至少一个电连接结构以及至少一个钝化层。在一些实施例中，互连结构240可包括多个电介质层和多层电连接结构。电连接结构的每一层均可以由电介质层夹着。在一些实施例中，电介质层和导电结构可以被配置成形成各种无源器件，例如电容器、电阻器和/或电感。
在一些实施例中，电介质层(未标记)可包括至少一种材料，诸如氧化硅、氮化硅、氮氧化硅、低k电介质材料、超低k电介质材料、一种或多种电介质材料或任何它们的组合。电连接结构可包括至少一种结构，诸如通孔插塞、接触插塞、镶嵌结构、双镶嵌结构、金属区、金属线或任何它们的组合。通孔插塞、接触插塞、镶嵌结构、双镶嵌结构、金属区以及金属线(未标记)可由至少一种材料制成，诸如钨、铝、铜、钛、钽、氮化钛、氮化钽、镍硅化物、钴硅化物、其他合适的导体材料和/或它们的组合。
在一些实施例中，互连结构240可包括可设置为与互连结构240的表面邻近的至少一个焊盘(未标记)。至少一个连接器(诸如凸块235)的每一个均可以设置在其相应焊盘之上用于与一个或多个衬底(未示出)的电连接。至少一个焊盘可以由至少一种材料制成，诸如铜(Cu)、铝(Al)、铝铜(AlCu)、铝硅铜(AlSiCu)、或其他导电材料或它们的多种组合。在一些实施例中，至少一个焊盘可以包括凸块底层金属(UBM)层。
图3是第三示例性实施例的示意性截面图。图3中与图2相同或相似的项由相同参考标号加100来表示。在图3中，封装系统300可包括集成电路320和350。集成电路320可通过至少一个连接器(例如凸块325)与互连结构317电连接。集成电路350可通过至少一个连接器(例如凸块(未标记))与互连结构317电连接。在一些实施例中，集成电路350可通过互连结构317和凸块325与集成电路320电连接。在其他实施例中，集成电路350可通过互连结构317和340以及电连接结构315与例如凸块335的至少一个连接器电连接。在一些实施例中，集成电路320可以被称为1级管芯，以及集成电路350可以被称为2级管芯。
在一个实施例中，至少一个模制化合物层(例如，模制化合物层313)可设置为至少部分地在集成电路350的至少一个侧边(例如，侧边350a)周围。在该示例性实施例中，模制化合物层313的表面313b可以高于集成电路的表面350b。在其他实施例中，模制化合物层313的表面313b可以基本与集成电路350的表面350b一样高。在又一些其他实施例中，集成电路350可以设置在如图3所示模制化合物层313内。集成电路350可以基本上完全被模制化合物层313包围。
在一些实施例中，集成电路350可包括至少一个有源器件，例如晶体管、MOS晶体管、BJT、CMOS晶体管、其他有源器件或任何它们的组合。在一些实施例中，集成电路350可包括衬底(未标记)和互连结构(未标记)。互连结构可设置为邻近衬底的表面。在一些实施例中，集成电路350的互联结构的金属线间距可以小于互连结构317的金属线间距。集成电路350的互连结构的金属线间距可以扩展至互连结构317的金属线间距。
在一些实施例中，集成电路350的衬底和互连结构可以由与以上结合图1分别描述的衬底121和互连结构123类似的材料制成。在其他实施例中，设置在集成电路350和互连结构317之间的连接器可以由与以上结合图1描述的凸块125相同或类似的材料制成。
图4是第四示例性实施例的示意性截面图。图4中与图1相同或相似的项由相同参考标号加300来表示。在图4中，封装系统可包括多个阻挡结构，例如阻挡结构416，每一个均设置在一个电连接结构415的至少一个侧边(例如，侧边415a)周围。阻挡结构416可以防止电连接结构415和至少一个模制化合物层(例如，模制化合物层413)之间的反应。在一些实施例中，阻挡结构416可以由至少一种材料制成，诸如阻挡材料(例如，钛、氮化钛、钽、氮化钽、其他阻挡材料和/或任何它们的结合)。注意，阻挡结构416可用于以上结合图1至图3分别描述的封装系统100至300。
图5A至图5L是示出形成类似于图1所示中介层的示例性中介层的示例性方法的示意性截面图。图5A至图5L中与图1相同或相似的项由相同参考标号加400来表示。虽然仅示出了单个中介层的形成，但本发明的范围不限于此。在一些实施例中，可以通过以下描述的方法限定多个中介层。
在图5A中，电介质层551可形成在衬底550之上。在一些实施例中，电介质层551可以被称为蚀刻停止层。衬底550可以为晶片衬底，例如，8英寸、12英寸、更大的晶片衬底或另一晶片衬底，并具有与电介质层551的蚀刻选择性不同的蚀刻选择性。在一些实施例中，电介质层551可以为互连结构517(在图5B中示出)的一部分。
在一些实施例中，衬底550可以由基本半导体制成，包括晶体、多晶或无定形结构的硅或锗；可以由化合物半导体制成，包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和锑化铟；可以由合金半导体制成，包括SiGe、GaAsP、AlInAs、AlGaAs、GaInP和GaInAsp；可以由其他合适的材料制成；或者可以由它们的组合制成。电介质层551可由至少一种材料制成，诸如氧化硅、氮化硅、氮氧化硅(SiON)、碳氧化硅(SiOC)、氮碳化硅(SiCN)、氮氧碳化硅(SiCON)、碳化硅(SiC)、其他电介质材料或任何它们的组合。例如，电介质层551可通过化学气相沉积(CVD)(例如，低压CVD(LPCVD)、原子层CVD(ALCVD)、超高真空CVD(UHCVD)、减压CVD(RPCVD))或任何合适的处理来形成。
参考图5B，互连结构517可形成在衬底550之上。互连结构517可包括至少一个电连接结构，例如，电连接结构518。电连接结构可包括至少一个接触插塞、通孔插塞、金属线或任何它们的组合。在一些实施例中，电连接结构518可以被称为再分配层(RDL)。互连结构517可以通过至少一个沉积处理、光刻处理、蚀刻处理、化学机械抛光(CMP)处理、清洗处理、其他已知半导体处理或任何它们的组合形成。
在一些实施例中，多个焊盘(未标记)可形成为邻近互连结构517的表面。在其他实施例中，焊盘可选择性地在焊盘的暴露表面上经过用于形成ENIG或Im-Sn材料的非电镀镍沉金(ENIG)处理或浸镀锡(Im-Sn)处理。ENIG或Im-Sn材料可用作焊盘和连接器(例如凸块525)之间的结合界面。
参考图5C，图5B所示的结构被翻转并设置在例如玻璃衬底的载体555之上。在一些实施例中，图5B所示的结构可以附着至设置在载体555之上的粘着层。粘着层560可以包括诸如热固性树脂的材料，以便于载体555和衬底550之间的连接。
参考图5D，去除处理可以去除衬底550(图5C所示)。去除处理可包括湿蚀刻处理、干蚀刻处理或任何它们的组合。在一些实施例中，去除处理可包括对衬底550的蚀刻选择性高于对电介质层551的蚀刻选择性的湿蚀刻处理。电介质层551可用作蚀刻停止层来用于去除处理。在其他实施例中，去除处理可以在湿蚀刻台中执行。湿蚀刻台在单个去除处理期间可以处理多个晶片衬底。
参考图5E，可以在电介质层551中限定多个开口(未标记)，露出电连接结构518的至少多个一些。例如UBM层555的至少一个UBM层可基本共形地形成在电介质层551之上。UBM层565可以由至少一种材料制成，诸如铝、铜、钛、镍、钨、金、铬、钒、由它们制成的一种或多种合金或者任何它们的组合。例如，UBM层565可通过物理气相沉积(PVD)、CVD、电镀、无电镀或任何它们的组合制成。在一些实施例中，形成UBM层565的处理可包括用于在UBM层565的表面上形成ENIG或Im-Sn材料的非电镀镍沉金(ENIG)处理或浸镀锡(Im-Sn)处理。
参考图5F，可以在UMB层565之上形成例如干膜或光刻胶(PR)层的图案化膜570。图案化膜570可包括露出UBM层565的多个部分的开口571。
参考图5G，电连接结构515可分别形成在一个开口571中。在一些实施例中，形成电连接结构515的处理可包括从UBM层565的暴露表面选择性地电镀电连接结构515。由于电连接结构515可以从底部生长到开口571的顶部，所以每个电连接结构515均可以在其中不具有间隙。
参考图5H，去除处理可以去除图案化膜570。另一种去除处理可去除UBM层565未被电连接结构515覆盖的部分。可露出电连接结构515的侧壁。去除处理可包括至少一种干蚀刻处理、至少一种湿蚀刻处理或任何它们的组合。
在一些实施例中，阻挡结构416(如图4所示)可选地形成在电连接结构515的侧壁周围。电连接结构515的暴露侧壁可选地经过电镀或无电镀，以形成每个均围绕一个电连接结构515的阻挡结构416。
参考图5I，可形成模制化合物材料512，覆盖电连接结构515。在一些实施例中，液体或半流体模制化合物材料512可以通过任何已知装置或方法施加在电连接结构之间的空隙中以及电连接结构之上。
参考图5J，去除处理可去除电连接结构515之上的液体或半流体模制化合物材料512的部分，以形成模制化合物层513。去除处理可露出电连接结构515的表面。模制化合物层513可形成在电连接结构515之间的空间中。在一些实施例中，去除部分模制化合物材料512的处理可包括研磨处理、蚀刻处理、抛光处理、一个或多个其他去除步骤和/或任何它们的组合。在一些实施例中，在去除部分模制化合物材料512之后，模制化合物层513可以通过任何已知热固化技术被固化和/或硬化。
在一些实施例中，互连结构240(如图2所示)可选地形成在图5J所示的结构之上。互连结构240可通过电连接结构515与互连结构517电连接。互连结构240可通过至少一个沉积处理、光刻处理、蚀刻处理、化学机械抛光(CMP)处理、清洁处理、其他已知半导体处理或任何它们的组合形成。
参考图5K，焊盘(未标记)和连接器(例如凸块535)可形成在电连接结构515之上。凸块535可通过互连结构517和电连接结构515与凸块525电连接。焊盘和凸块535可以由与以上结合图5B描述的焊盘和凸块525相同或类似的材料制成。
参考图5L，载体555(如图5K所示)可以被去除，并且其余结构可以被翻转。在一些实施例中，去除载体555可包括去除设置在互连结构517和载体555之间的粘着层560。去除粘着层560可包括机械处理、热处理、湿蚀刻处理、干蚀刻处理、用于去除粘着层560的其他已知处理或任何它们的组合。
在一些实施例中，图5L所示的结构可经过切割处理，用于限定多个中介层。在一些实施例中，切割处理可包括锯切处理和/或激光锯处理。在形成封装系统的一些实施例中，至少一个集成电路(未示出)可被设置在中介层之上。在又一些其他实施例中，可形成覆盖层，覆盖集成电路以形成以上结合图1至图4描述的任何封装系统。注意，以上结合图5A至图5L描述的中介层可以被修改，以分别实现以上结合图1至图4描述的中介层110至410。还应该注意，以上结合图5A至图5L描述的处理不包括用于形成硅通孔结构的处理。可通过本申请来降低用于形成封装系统的成本。
图6A至图6E是示出可选地代替图5E至图5J所示的所有或一些处理步骤以形成类似于图3所示中介层310的结构的多个处理步骤的示意性截面图。图6A至图6E中与图5E至图5J中相同或相似的项由相同参考标号加100来表示。在图6A中，被配置成容纳集成电路的凸块的开口675可以限定在电介质层651中。至少一个BUM层可基本共形地形成在电介质层651之上。
在图6B中，例如干膜或光刻胶(PR)层的图案化膜670可形成在UBM层665之上。图案化膜670可包括露出部分UBM层665的开口671。
参考图6C，电连接结构615可分别形成在一个开口671中。在一些实施例中，形成电连接结构615的处理可包括从UBM层665的暴露表面选择性地电镀电连接结构615。由于电连接结构615可以从开口671的底部生长到顶部，所以每个电连接结构615均可以在其中没有间隙。
参考图6D，去除处理可去除图案化膜670。另一去除处理可去除UBM层665未被集成电路650的电连接结构615和凸块覆盖的部分。集成电路650的凸块可设置在开口675中并通过电连接结构618与凸块625电连接。
参考图6E，可以形成模制化合物层613，覆盖集成电路650。模制化合物层613可形成在电连接结构615之间的空间中。在形成模制化合物层613之后，可执行以上结合图5K至图5L描述的处理步骤。
图7是示出包括设置在衬底板之上的示例性封装系统的系统的示意图。在图7中，系统700可包括设置在衬底板701之上的封装系统702。衬底板701可包括印刷电路板(PCB)、印刷布线板和/或能够承载封装系统的其他载体。封装系统702可类似于以上结合图1至图4分别描述的封装系统100至400。封装系统702可以与衬底板701电连接。在一些实施例中，封装系统702可通过凸块705与衬底701电连接和/或热连接。系统700可以为电子系统的一部分，诸如显示器、面板、照明系统、自动控制机构、娱乐装置等。在一些实施例中，包括封装系统702的系统700可以在一个IC中提供整个系统，所谓的芯片上系统(SOC)或集成电路器件上系统(SOIC)。
上面论述了多个实施例的部件，使得本领域普通技术人员可以更好地理解本公开的各个方面。本领域普通技术人员应该理解，可以很容易地使用本公开作为基础以设计或修改用于执行与在此介绍的实施例相同的目的和/或实现相同优点的其他处理和结构。本领域普通技术人员还应该意识到，这种等效构造并不背离本公开的精神和范围，并且在不脱离本发明的精神和范围的情况下，可以进行多种变化、替换以及改变。

Claims (10)

1.一种封装系统，包括：
中介层，包括：
至少一个模制化合物层，包括多个通过所述至少一个模制化合物层的多个电连接结构；和
第一互连结构，设置在所述至少一个模制化合物层的第一表面之上并与所述多个电连接结构电连接；以及
第一集成电路，设置在所述中介层之上，所述第一集成电路与所述第一互连结构电连接。
2.根据权利要求1所述的封装系统，其中，所述多个电连接结构被设置为径直通过所述至少一个模制化合物层。
3.根据权利要求1所述的封装系统，其中，所述中介层还包括：
第二互连结构，设置在所述至少一个模制化合物层的与所述第一表面相对的第二表面之下；
多个阻挡结构，每一个均被设置为至少部分地在所述多个电连接结构中的一个的至少一个侧边周围，
其中，所述第二互连结构的金属线间距大于所述第一互连结构的金属线间距。
4.根据权利要求1所述的封装系统，还包括：
第二集成电路，与所述第一互连结构电连接，其中，所述至少一个模制化合物层被设置为至少部分地在所述第二集成电路的至少一个侧边周围；
覆盖层，覆盖所述第一集成电路，其中，所述覆盖层的热膨胀系数(CTE)基本等于所述至少一个模制化合物层的CTE，
其中，所述第二集成电路被设置在所述至少一个模制化合物层内。
5.一种封装系统，包括：
中介层，包括：
至少一个模制化合物层，包括径直通过所述至少一个模制化合物层的多个电连接结构；
第一互连结构，设置在所述至少一个模制化合物层的第一表面之上并与所述多个电连接结构电连接；和
第二互连结构，设置在所述至少一个模制化合物层的与所述第一表面相对的第二表面之下；以及
第一集成电路，设置在所述中介层之上，所述第一集成电路与所述第一互连结构电连接。
6.根据权利要求5所述的封装系统，其中，所述第二互连结构的金属线间距大于所述第一互连结构的金属线间距。
7.根据权利要求5所述的封装系统，还包括：
第二集成电路，与所述第一互连结构电连接，其中，所述至少一个模制化合物层被设置为至少部分地在所述第二集成电路的至少一个侧边周围；
覆盖层，覆盖所述第一集成电路，其中，所述覆盖层的热膨胀系数(CTE)基本等于所述至少一个模制化合物层的CTE，
其中，所述第二集成电路设置在所述至少一个模制化合物层内。
所述中介层还包括：多个阻挡结构，每一个均被设置为至少部分地在所述多个电连接结构的至少一个侧边周围。
8.一种封装系统，包括：
中介层，包括：
至少一个模制化合物层，包括通过所述至少一个模制化合物层的多个电连接结构，其中，所述至少一个模制化合物层具有第一热膨胀系数(CTE)；和
第一互连结构，设置在所述至少一个模制化合物层的第一表面之上并与所述多个电连接结构电连接；
第一集成电路，设置在所述中介层之上，所述第一集成电路与所述第一互连结构电连接；
底部填充材料，设置在所述中介层和所述第一集成电路之间，其中，所述底部填充材料具有第二CTE，并且所述第二CTE基本等于所述第一CTE；以及
覆盖层，设置在所述中介层之上，所述覆盖层覆盖所述第一集成电路，其中，所述覆盖层具有第三CTE，并且所述第三CTE基本等于所述第一CTE。
9.根据权利要求8所述的封装系统，其中，所述多个电连接结构被设置成径直通过所述至少一个模制化合物层。
10.根据权利要求8所述的封装系统，其中，所述中介层还包括：
第二互连结构，设置在所述至少一个模制化合物层的与所述第一表面相对的第二表面之下，其中，所述第二互连结构的金属线间距大于所述第一互连结构的金属线间距；
多个阻挡结构，每一个均被设置为至少部分地在所述多个电连接结构中的一个的至少一个侧边周围，
其中，所述封装系统，还包括：
第二集成电路，与所述第一互连接结构电连接，其中，所述至少一个模制化合物层被设置为至少部分地在所述第二集成电路的至少一个侧边周围，
其中，所述第二集成电路设置在所述至少一个模制化合物层内。
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