CN106876364A - 半导体封装件及其制造方法 - Google Patents

半导体封装件及其制造方法 Download PDF

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CN106876364A
CN106876364A CN201710153211.2A CN201710153211A CN106876364A CN 106876364 A CN106876364 A CN 106876364A CN 201710153211 A CN201710153211 A CN 201710153211A CN 106876364 A CN106876364 A CN 106876364A
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substrate
semiconductor package
dielectric layer
package part
wire structures
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李轶楠
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Samsung Semiconductor China R&D Co Ltd
Samsung Electronics Co Ltd
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Samsung Semiconductor China R&D Co Ltd
Samsung Electronics Co Ltd
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Priority to CN201710153211.2A priority Critical patent/CN106876364A/zh
Publication of CN106876364A publication Critical patent/CN106876364A/zh
Priority to KR1020170117222A priority patent/KR102391517B1/ko
Priority to US15/786,676 priority patent/US10319611B2/en
Priority to US16/393,752 priority patent/US10796930B2/en
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Abstract

提供了半导体封装件及其制造方法。所述半导体封装件包括：基板，包括第一表面、与第一表面背对的第二表面以及在基板中延伸以连接第一表面和第二表面的导电柱；介质层，位于基板的第一表面上；再布线结构，设置在介质层中并电连接到导电柱；半导体芯片，设置在介质层上方并电连接到再布线结构；包封层，位于介质层上并包封半导体芯片，其中，基板和包封层中的每个由模塑材料形成。

Description

半导体封装件及其制造方法
技术领域
本发明涉及半导体封装领域，尤其涉及一种防止翘曲的半导体封装件及其制造方法。
背景技术
随着诸如手机、平板电脑、数码相机等电子产品的迅速普及，半导体封装件得到越来越广泛的应用。通常，倒装芯片式球栅阵列(Flip-Chip Ball Grid Array,FCBGA)半导体封装件是一种典型的封装结构。在该封装结构中，至少一个半导体芯片的有效表面可以经由多个导电凸块(bump)而电连接至基板的一个表面。在半导体芯片与基板之间填充底部填料(underfill)，使得半导体芯片的底部填料包围各导电凸块并填充各导电凸块之间的空间，以增强导电凸块的强度并且支撑半导体芯片。同时，在基板的另一个表面上设置多个焊球作为输入/输出端。这样的设计可以大幅度减小半导体封装件的体积，因此已成为当今电子元件的主流封装技术。
由于电子产品的小型化需求，半导体封装件的整体尺寸变薄，半导体封装件中的不同元件在热膨胀系数(coefficent of thermal expansion,CTE)上的差异会导致在制造半导体封装件时容易发生翘曲(warpage)现象，从而影响基板与半导体封装件或半导体芯片的导电凸块与基板的电连接。另外，在经过回流焊(reflow)工艺使导电凸块焊接于基板之后，基板因收缩引起翘曲也会造成导电凸块的开裂(crack)，造成电性连接不良，使产品质量劣化。
美国发明专利申请US2015/0303158A1公开了一种够能防止翘曲并提高粘附性的半导体封芯片装件。如图1所示，传统的FCBGA半导体封装件120包括裸片121、穿过封装件通孔(TPV)122、模塑化合物123和128、第一再分布结构124、第二再分布结构125、焊球126和连接件127。元件之间的CTE不同导致半导体封装件120容易从边缘处向上翘曲。如图2所示，根据该美国发明专利申请的半导体封装件120′利用可提供压应力的材料212来形成第二再分布结构125，以平衡在半导体封装件120中产生的翘曲。图3是图2中的矩形部分P的放大图。如图3所示，压应力层212设置在具有层叠结构的第二再分布结构125的下层，覆盖在模塑化合物123和TPV 122上并暴露TPV 122的一部分。钝化层214覆盖在压应力层212上方。第二再分布布线213埋置在压应力层212和钝化层214内。
然而，该设计虽然能够减少半导体封装件的翘曲，但是因为半导体封装件的再分布结构的厚度有限，所以通过被设置在再分布结构中的压应力层来平衡翘曲的能力有限，而且不能够精确地控制由环氧树脂模塑料(EMC)产生的翘曲缺陷。
发明内容
本发明致力于解决上述至少一个技术问题。为此，本发明的实施例提供一种能够有效防止翘曲的半导体封装件及其制造方法。
本发明的一方面提供了一种半导体封装件。所述半导体封装件包括：基板，包括第一表面、与第一表面背对的第二表面以及在基板中延伸以连接第一表面和第二表面的导电柱；介质层，位于基板的第一表面上；再布线结构，设置在介质层中并电连接到导电柱；半导体芯片，设置在介质层上方并电连接到再布线结构；包封层，位于介质层上并包封半导体芯片，其中，基板和包封层中的每个由模塑材料形成。
根据本发明的实施例，包封层的厚度和基板的厚度可以被形成为抵消彼此之间的应力以防止翘曲。
根据本发明的实施例，半导体芯片可以通过设置在有效表面上的导电凸块而电连接到再布线结构。
根据本发明的实施例，包封层可以填充半导体芯片的有效表面与介质层之间的空间。
根据本发明的实施例，半导体芯片的导电凸块可以连接到设置在介质层的顶表面上的再布线结构。
根据本发明的实施例，所述半导体封装件还可以包括设置在基板的第二表面上并电连接到导电柱的焊球。
本发明的另一方面提供了一种制造半导体封装件的方法。所述方法包括：准备基板，所述基板包括第一表面和与第一表面背对的第二表面；在基板中形成导电柱；在基板的第一表面上形成介质层和再布线结构，所述再布线结构设置在介质层中并电连接到导电柱；将半导体芯片设置在再布线结构上并使彼此电连接；在介质层上形成包封层以包封半导体芯片，其中，基板和包封层中的每个由模塑材料形成。
根据本发明的实施例，可以将包封层的厚度和基板的厚度形成为抵消彼此之间的应力以防止翘曲。
根据本发明的实施例，在形成导电柱时，可以通过钻孔工艺在基板中形成孔隙，可以利用导电材料填充孔隙以形成导电柱。
根据本发明的实施例，可以将导电柱形成为靠近基板的第一表面并使导电柱的顶表面与基板的第一表面处于同一水平。
根据本发明的实施例，可以通过设置在半导体芯片的有效表面上的导电凸块而将半导体芯片电连接到再布线结构。
根据本发明的实施例，在形成包封层时，可以使包封层填充半导体芯片的有效表面与介质层之间的空间。
根据本发明的实施例，可以将半导体芯片的导电凸块连接到设置在介质层的顶表面上的再布线结构。
根据本发明的实施例，所述方法还可以包括：对基板执行抛光工艺以暴露导电柱，在基板的第二表面上设置电连接到导电柱的焊球。
根据本发明的实施例的半导体封装件具有由模塑材料形成的基板和包封层以及置于两者之间的介质层的三明治结构。将该结构应用于扇出型晶圆级封装件(Fan-outWLP)可以有效控制封装件的翘曲，还可以解决玻璃基板在剥离过程中造成的模塑材料与半导体芯片不平整的问题，从而提高封装工艺的良率，提高半导体封装件的耐用性。
附图说明
下面结合附图详细描述本发明的实施例。在整个说明书中，同样的附图标记始终指示同样的元件。附图不一定按照比例绘制，而是将重点放在示出发明构思的原理。
图1是根据现有技术的半导体封装件的示意图。
图2是根据现有技术的半导体封装件的示意图。
图3是图2中的矩形部分P的放大图。
图4是根据本发明的实施例的半导体封装件的示意图。
图5是根据本发明的实施例的半导体封装件的三明治结构示意图。
图6A至图6G是根据本发明的实施例的半导体封装件的制造方法的各个步骤的示意图。
具体实施方式
在下文中，将结合附图详细描述本发明的实施例。在附图中，为了清楚地表示与发明构思有关的主要元件，可夸大层或区域的形状，并且可以省略次要的元件以避免表述不清楚。发明构思不局限于下述实施例，在各个实施例或相应的方法描述中涉及到的特征、元件或结构均可以单独或组合地应用于其他实施例。
图4是根据本发明的实施例的半导体封装件的示意图。如图4所示，半导体封装件100包括基板110、介质层120、再布线结构130、半导体芯片140以及包封层150。基板110由模塑材料形成。在一个实施例中，基板110可以由环氧树脂模塑料(EMC)形成。基板110包括第一表面111、与第一表面111背对的第二表面112以及在基板110中延伸以连接第一表面111和第二表面112的导电柱113。在一个实施例中，基板110可以具有由EMC形成的薄板形状。第一表面111可以是其上形成多层布线结构的表面，第二表面112可以是与外部电路相连接的表面。
在一个实施例中，导电柱113可以从基板110的第一表面111竖直地延伸到第二表面112，以在贯穿基板110的同时，使第一表面111连接到第二表面112。在一个实施例中，导电柱113可以由诸如铜的金属形成，但实施例不限于此，还可以由其他导电材料来形成导电柱。当半导体封装件100为三维半导体封装件时，导电柱113还可以被设计成穿过基板通孔(TSV)。
介质层120位于基板110的第一表面111上。再布线结构130设置在介质层120中并电连接到导电柱113。具体地，再布线结构130可以设置在基板110的第一表面111上并与第一表面111接触(例如，直接接触)。介质层120可以位于再布线结构130上方并覆盖再布线结构130的一部分，再布线结构130的没有被介质层120覆盖的部分可以暴露于介质层120外部，以用作与半导体芯片或外部电路连接的焊盘。在一个实施例中，介质层120可以包括至少一个钝化层或绝缘层。具体地，介质层120可以由氧化硅、氮化硅或氮氧化硅等材料形成。在一个实施例中，再布线结构可以由诸如铜的金属或合金形成，但实施例不限于此。可以利用本领域满足条件的任何材料来形成介质层和再布线结构。
在一个实施例中，介质层120可以包括由多个层形成的层叠结构。再布线结构130可以与基板110的第一表面111接触。例如，再布线结构130可以直接位于第一表面111上。再布线结构130可以埋置在介质层120中并在介质层120中延伸以电连接到介质层120上的半导体芯片或外部电路。再布线结构130可以包括暴露于介质层120外部的部分130a，该部分可以设置在介质层120的顶表面上并用作与半导体芯片140电连接的焊盘。
半导体芯片140设置在介质层120上方并电连接到再布线结构130。在一个实施例中，半导体芯片140可以包括有效表面141。有效表面141上可以设置多个导电凸块(未示出)。半导体芯片140可以通过设置在有效表面141上的导电凸块而电连接到再布线结构130。在一个实施例中，半导体芯片140的导电凸块可以连接到设置在介质层120的顶表面上的再布线结构130。半导体芯片可以以倒装芯片的方式设置在介质层120的表面上。设置在半导体芯片140的有效表面141上的导电凸块可以与再布线结构130的被暴露在介质层120外部且被用作焊盘的部分130a电连接。在一个实施例中，多个导电凸块可以由诸如铜的金属或合金形成，但不限于此。
包封层150位于介质层120上并包封半导体芯片140。包封层150由模塑材料形成。包封层150和基板110可以由相同的材料形成。在一个实施例中，包封层150可以由环氧树脂模塑料(EMC)形成。在一个实施例中，除了有效表面141之外，半导体芯片140还可以包括无效表面142和围绕半导体芯片四周的侧表面143。包封层150可以围绕半导体140的侧表面143并覆盖无效表面142。在该实施例中，包封层150可以填充半导体芯片140的有效表面141与介质层120之间的空间S。在传统的半导体封装件中，可以利用诸如底部填充料来填充空间S。根据本发明的实施例的半导体封装件利用模塑材料在形成包封层150时填充空间S，可以省略底部填充工艺。
在一个实施例中，半导体封装件100还可以包括设置在基板110的第二表面112上并电连接到导电柱113的焊球114。具体地，焊球114可以形成为与导电柱113叠置。半导体芯片140可以通过设置在其有效表面141上的导电凸块(未示出)、设置在介质层120中的再布线结构130以及设置在基板110中的导电柱113而与焊球114电连接，使得从外部电路或装置接收的数据或信号可以从焊球114传输到半导体芯片140。
由于半导体封装件中的不同构成元件在热膨胀系数(CTE)上的差异会导致在制造半导体封装件时容易发生翘曲现象，从而影响基板与半导体封装件或半导体芯片的导电凸块与基板的电连接。另外，在经过回流焊工艺使导电凸块焊接于基板之后，基板因收缩引起翘曲也会造成导电凸块的开裂，造成电性连接不良，使产品质量劣化。根据本发明的实施例的半导体封装件的基板和包封层中的每个由模塑材料形成，从而构成了使介质层设置在中间的三明治结构。这样的三明治结构可以平衡在制造期间产生的应力，抑制半导体封装件的翘曲。
图5是根据本发明的实施例的半导体封装件的三明治结构示意图。在一个实施例中，包封层150的厚度和基板110的厚度可以被形成为抵消彼此之间的应力以防止翘曲。如图5所示，可以将包封层150的厚度形成为与基板110的厚度基本相同，并且介质层120置于它们之间，使得半导体封装件100具有对称的结构。由于包封层与基板在结构上对称，在材料上相同，在厚度上相似，从而可以抵消相互间的应力，达到平衡翘曲的目的。
图6A至图6G是根据本发明的实施例的半导体封装件的制造方法的各个步骤的示意图。在下文中，将结合图6A至图6G详细描述制造根据本发明的实施例的半导体封装件100的方法。
首先，如图6A所示，准备基板110。基板110由模塑材料形成。在一个实施例中，基板110可以由环氧树脂模塑料(EMC)形成。基板110包括第一表面111和与第一表面111背对的第二表面112。
接下来，如图6B所示，在基板110中形成导电柱113。导电柱113可以被形成为靠近基板110的第一表面111。在一个实施例中，可以通过钻孔工艺在基板110的第一表面111上形成孔隙113a，所述钻孔工艺可以包括激光钻孔、机械钻孔、化学腐蚀、离子刻蚀等，但是本发明构思不限于在此列举的钻孔工艺。该孔隙113a可以具有小于基板110的深度并且不贯穿基板110。然后，利用诸如铜的金属填充孔隙113a，再执行诸如化学机械抛光(CMP)的抛光工艺，以去除位于基板110的第一表面111上的多余的金属，从而形成导电柱113。另外，导电柱113可以完全填充孔隙113a。导电柱113的上表面可以与基板110的第一表面111位于同一水平处。
接下来，如图6C所示，在形成导电柱113之后，再在基板110的第一表面111上形成介质层120和再布线结构130。在一个实施例中，可以首先在基板110上形成再布线结构130，然后在再布线结构130上形成介质层120以覆盖再布线结构130。具体地，可以利用掩模，通过曝光和显影工艺在基板110上形成再布线图案，再通过诸如光刻的工艺形成再布线结构130，然后利用化学气相沉积(CVD)或旋涂工艺在再布线结构130上形成介质层120。最终使再布线结构130设置在介质层120中并电连接到导电柱113。
在一个实施例中，可以将介质层120形成为覆盖再布线结构130的一部分，并且使再布线结构130的另一部分130a暴露于介质层120的外部以用作焊盘。
接下来，如图6D所示，将半导体芯片140设置在再布线结构130上并使彼此电连接。在一个实施例中，半导体芯片140可以包括有效表面141。在有效表面141上形成有多个导电凸块。在这种情况下，可以通过设置在半导体芯片140的有效表面141上的导电凸块而将半导体芯片140电连接到再布线结构130。具体地，可以将半导体芯片140的导电凸块连接到设置在介质层120的顶表面上的再布线结构130。即，通过使导电凸块与再布线结构130的被用作焊盘的部分130a接触，使得半导体芯片140被电连接到布线结构130。
接下来，如图6E所示，在介质层120上形成包封层150以包封半导体芯片140。包封层150由模塑材料形成。在一个实施例中，包封层150可以由环氧树脂模塑料(EMC)形成。可以利用相同的模塑材料来形成包封层150和基板110。可以将包封层150的厚度和基板110的厚度形成为抵消彼此之间的应力以防止翘曲。在一个实施例中，除了有效表面141之外，半导体芯片140还可以包括无效表面142和围绕半导体芯片150四周的侧表面143。在该实施例中，可以在形成包封层150时，利用模塑材料填充位于半导体芯片140的有效表面141与介质层120之间的空间S。在传统的半导体封装件中，可以利用诸如底部填充料来填充空间S。根据本发明的实施例的半导体封装件的制造方法可以省略底部填充工艺。
接下来，如图6F所示，可以对基板110的第二表面112执行抛光工艺以使基板110的厚度减薄并暴露导电柱113。在一个实施例中，抛光工艺可以为化学机械抛光或研磨抛光中的至少一种工艺。可以执行抛光工艺直到刚刚暴露导电柱113为止。
接下来，如图6G所示，可以在基板110的第二表面112上设置电连接到导电柱113的焊球114。在一个实施例中，可以将焊球114形成为与导电柱113叠置。因此，半导体芯片140可以通过设置在其有效表面141上的导电凸块(未示出)、设置在介质层120中的再布线结构130以及设置在基板110中的导电柱113而与焊球114电连接，使得来自外部电路或装置的数据或信号可以从焊球114传输到半导体芯片140。
根据本发明的实施例的制造方法，半导体封装件具有由模塑材料形成的基板和包封层并且介质层设置在它们之间的三明治结构。该结构应用于扇出型晶圆级封装件(Fan-out WLP)可以有效控制封装件的翘曲，还可以解决玻璃基板在剥离过程中造成的模塑材料与半导体芯片不平整的问题，从而提高封装工艺的良率，并提高半导体封装件的耐用性。
虽然已经示出和描述了本发明的示例性实施例，但是本领域技术人员将理解的是，发明构思不限于这些实施例。在不脱离本发明的精神和原理的情况下，可以对上述实施例进行各种修改和变化。

Claims (10)

1.一种半导体封装件，所述半导体封装件包括：
基板，包括第一表面、与第一表面背对的第二表面以及在基板中延伸以连接第一表面和第二表面的导电柱；
介质层，位于基板的第一表面上；
再布线结构，设置在介质层中并电连接到导电柱；
半导体芯片，设置在介质层上方并电连接到再布线结构；
包封层，位于介质层上并包封半导体芯片，
其中，基板和包封层中的每个由模塑材料形成。
2.根据权利要求1所述的半导体封装件，其中，包封层的厚度和基板的厚度被形成为抵消彼此之间的应力以防止翘曲。
3.根据权利要求1所述的半导体封装件，其中，半导体芯片通过设置在有效表面上的导电凸块而电连接到再布线结构。
4.根据权利要求3所述的半导体封装件，其中，包封层填充半导体芯片的有效表面与介质层之间的空间。
5.根据权利要求3所述的半导体封装件，其中，半导体芯片的导电凸块连接到设置在介质层的顶表面上的再布线结构。
6.根据权利要求1所述的半导体封装件，所述半导体封装件还包括设置在基板的第二表面上并电连接到导电柱的焊球。
7.一种制造半导体封装件的方法，所述方法包括以下步骤：
准备基板，所述基板包括第一表面和与第一表面背对的第二表面；
在基板中形成导电柱；
在基板的第一表面上形成介质层和再布线结构，所述再布线结构设置在介质层中并电连接到导电柱；
将半导体芯片设置在再布线结构上并使彼此电连接；
在介质层上形成包封层以包封半导体芯片，
其中，基板和包封层中的每个由模塑材料形成。
8.根据权利要求7所述的方法，其中，将包封层的厚度和基板的厚度形成为抵消彼此之间的应力以防止翘曲。
9.根据权利要求7所述的方法，其中，在形成导电柱时，通过钻孔工艺在基板中形成孔隙，利用导电材料填充孔隙以形成导电柱。
10.根据权利要求9所述的方法，其中，将导电柱形成为靠近基板的第一表面并使导电柱的顶表面与基板的第一表面处于同一水平。
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