CN102768962A - 一种集成电路封装及其组装方法 - Google Patents

一种集成电路封装及其组装方法 Download PDF

Info

Publication number
CN102768962A
CN102768962A CN2012100203153A CN201210020315A CN102768962A CN 102768962 A CN102768962 A CN 102768962A CN 2012100203153 A CN2012100203153 A CN 2012100203153A CN 201210020315 A CN201210020315 A CN 201210020315A CN 102768962 A CN102768962 A CN 102768962A
Authority
CN
China
Prior art keywords
wafer
substrate
integrated circuit
encapsulation
semiconductor crystal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN2012100203153A
Other languages
English (en)
Inventor
雷泽厄·拉曼·卡恩
爱德华·洛沃
肯·建明·王
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Broadcom Corp
Zyray Wireless Inc
Original Assignee
Zyray Wireless Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Zyray Wireless Inc filed Critical Zyray Wireless Inc
Publication of CN102768962A publication Critical patent/CN102768962A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/147—Semiconductor insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/5442—Marks applied to semiconductor devices or parts comprising non digital, non alphanumeric information, e.g. symbols
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02379—Fan-out arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02381—Side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
    • H01L2224/0345—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/0346—Plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05569—Disposition the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1401—Structure
    • H01L2224/1403—Bump connectors having different sizes, e.g. different diameters, heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1418—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/14181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83193—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06568—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1032—III-V
    • H01L2924/10329—Gallium arsenide [GaAs]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1431—Logic devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Wire Bonding (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

本发明涉及一种改进集成电路封装的方法、系统及装置。集成电路封装包括半导体基底和半导体晶片。半导体基底含有相对的第一和第二表面、多个穿过半导体基底的通孔和半导体基底一个或两个表面的布线。晶片贴装在半导体基底的第一表面。封装材料封装在半导体基底的第一表面上的晶片。

Description

一种集成电路封装及其组装方法
技术领域
本发明涉及集成电路封装。
背景技术
通常使用可以贴在电路板的封装将集成电路(IC)芯片或晶片与其他电路连接。一种这样类型的IC晶片封装(IC die package)是球栅阵列(BGA)封装。BGA封装比许多其他如今可获得的封装解决方案提供更小的脚印底面积。一种类型的BGA封装含有一个或多个贴在封装基底的第一表面的IC晶片，并且含有一系列位于封装基底的第二表面的焊球垫。焊球贴在焊球垫上。焊球回流以使封装贴在电路板上。
一种先进类型的BGA封装是晶圆级BGA封装。晶圆级BGA封装在业界有几个名字，包括晶圆片级芯片规模封装(WLCSP)等等。在晶圆级BGA封装中，当IC晶片还没有从其晶圆制造独立出来(singulate)时，焊球直接贴装在IC晶片上。这样，晶圆级BGA封装不包括封装基底。因此，相对包括传统BGA封装的其他IC封装类型，晶圆级BGA封装可以制造得很小，具有高脚位(high pin out)。
对于用于晶圆级BGA封装的IC晶片，通常直接在晶片上形成布线。布线在晶片的表面形成，以按布线将晶片衬垫的信号发送至焊球贴在晶片上的位置。扇入布线和扇出布线是可在晶片上形成的两种不同类型的布线方式。扇入布线是一类仅在每个半导体晶片的区域之内形成的布线。扇出布线是一类在半导体晶片的区域之外延伸(扩展到包围晶片的材料)的布线。
这样，扇出布线在较晶片区域更大的区域内传递IC晶片的信号，从而为产生的集成电路封装提供额外的互连(例如，焊球)空间。然而，形成晶圆级封装的传统技术由于使用扇出布线比较昂贵，且使用较多的组装步骤。这样，需要使能制造芯片规模封装的集成电路封装的组装技术，且该技术不昂贵并使用更少的处理步骤。
发明内容
本发明描述了通过将集成电路晶片贴装到半导体基底来形成集成电路封装的方法、系统和装置，该半导体基底具有多层布线和通过半导体基底的通孔(vias)，结合至少一幅附图进行了详细描述，并在权利要求中得到了更完整的阐述。
根据本发明的一个方面，提供一种方法，所述方法包括：
在第一半导体晶圆的多个半导体基底区域中形成穿过所述第一半导体晶圆的多个通孔；
将多个从第二半导体晶圆独立出来的晶片贴在所述第一半导体晶圆的表面；
在所述第一半导体晶圆的所述表面对所述晶片进行封装；及
将所述第一半导体晶圆独立出来以分离多个半导体区域，以形成多个集成电路封装，每个集成电路封装包括至少一个所述晶片和与基底区域相对应的基底，每个基底包括扇出布线。
优选地，所述第一半导体晶圆为硅晶圆，所述通孔为硅穿孔。
优选地，所述方法还包括：
在所述独立之前，测试所述第一半导体晶圆中的所述基底区域，以确定一套工作基底(working substrate)。
优选地，所述方法还包括：
在每个所述半导体区域的所述第一半导体晶圆的表面形成布线。
优选地，所述贴包括：
使用一系列焊接凸点将每个晶片贴装在基底区域。
优选地，所述方法还包括：
在所述独立之前，在所述第一半导体晶圆的第二表面上形成多个互连凸点(interconnect ball)；
其中每个集成电路封装包括所述多个互连凸点中的互连凸点，所述多个互连凸点用于连接所述集成电路封装和电路板。
优选地，每个集成电路封装表面的一系列导电衬垫用于将所述集成电路封装与电路板连接为触点阵列封装。
根据本发明的一个方面，提供一种方法，所述方法包括：
在第一半导体晶圆的多个半导体基底区域形成穿过所述第一半导体晶圆的多个通孔；
将所述第一半导体晶圆独立出来以形成与所述多个基底区域相对应的多个基底；
将所述基底贴在载体表面；
将多个从第二半导体晶圆独立出来的晶片贴到所述基底；
使用封装材料对所述载体所述基底上的所述晶片进行封装；
从封装好的晶片和基底中将所述载体分离出来，以形成模制组件，所述模制组件包括用于封装所述晶片和所述基底的封装材料；及
将所述模制组件独立出来以形成多个集成电路封装，每个集成电路封装包括所述晶片的至少一个和所述基底的至少一个，每个基底包括扇出布线。
优选地，所述第一半导体晶圆为硅晶圆，所述通孔为硅穿孔。
优选地，所述方法还包括：
在所述将所述第一半导体晶圆独立之前，测试所述第一半导体晶圆中的所述基底区域，以确定一套工作基底。
优选地，所述方法还包括：
在每个所述半导体区域的所述第一半导体晶圆表面形成布线。
优选地，所述贴包括：
使用一系列焊接凸点将每个晶片贴装在基底上。
优选地，所述方法还包括：
在所述从所述第一半导体晶圆独立之前，在所述第一半导体晶圆的第二表面上形成多个互连凸点；
其中每个集成电路封装包括所述多个互连凸点的互连凸点，所述多个互连凸点用于连接所述集成电路封装和电路板。
优选地，每个集成电路封装表面的一系列导电衬垫用于将所述集成电路封装与电路板连接为触点阵列封装。
根据本发明的一个方面，提供一种集成电路封装，所述集成电路封装包括：
含有相对的第一和第二表面的硅基底、多个穿过所述硅基底的通孔和至少在所述硅基底的所述第一表面的布线；
贴装在所述硅基底的所述第一表面的晶片；
封装所述硅基底的所述第一表面上的所述晶片的封装材料。
优选地，所述封装还包括：
多个焊接凸点，用于将所述晶片贴到所述硅基底的所述第一表面。
优选地，所述封装还包括：
多个互连凸点，其贴在所述硅基底的所述第二表面。
优选地，所述封装还包括：
所述硅基底的所述第二表面上的一系列导电衬垫，所述导电衬垫用于将所述集成电路封装和电路板连接为触点阵列封装。
优选地，所述通孔为硅穿孔。
优选地，所述硅基底包括有源集成电路逻辑。
附图说明
本文所包含的并形成部分说明书的附图阐述本发明，并结合具体实施方式进一步解释本发明的原理，以使本领域技术人员能够制造和使用本发明。
图1和2是示例性传统的晶圆级集成电路封装的剖面图；
图3是根据本发明实施例的集成电路封装的侧面剖面图；
图4是根据本发明实施例的组装集成电路封装的示例性过程的流程图；
图5是根据本发明实施例的第一半导体晶圆的平面图；
图6是根据本发明实施例的测试第一半导体晶圆的基底区域的可选过程的示意图；
图7是根据本发明实施例的第二半导体晶圆的平面图；
图8是根据本发明实施例的图5中具有贴在晶圆的每个基底区域的晶片的半导体晶圆的示意图；
图9是根据本发明实施例的图5中半导体晶圆的一部分的侧面剖面图，其中第一和第二晶片贴装在各自的基底区域；
图10是根据本发明实施例的图9所示的具有封装晶片的晶圆的一部分的侧面剖视图；
图11是根据本发明实施例的IC封装从图10中的封装晶圆独立(singulate)出来的示意图；
图12是根据本发明实施例的使用载体组装集成电路封装的示例性过程的流程图；
图13是根据本发明实施例的贴有半导体内插器基底的载体表面的示意图；
图14是根据本发明实施例的图13中具有贴在半导体基底上的晶片的示意图；
图15是根据本发明实施例的在载体上贴有半导体基底的晶片的侧面剖面图；
图16是根据本发明实施例的图15中贴装有半导体基底和晶片的载体的侧面剖视图，所述载体使用封装材料封装半导体基底和晶片；
图17是根据本发明实施例的图16的侧面剖视图，其中将载体从封装材料、半导体基底和晶片中分离出来而形成模制组件；
图18是根据本发明实施例的从图17的模制组件独立出来的第一和第二IC封装的示意图；
图19是根据本发明实施例的具有多层布线半导体基底的IC封装的一部分的侧面剖面图；
图20-22是根据本发明实施例的包括半导体内插器基底的IC封装的示意图。
下面将结合附图对本发明进行详细描述。在附图中，相同标号一般表示相同或功能相似的部件。另外，附图标记最左边的数字表明该附图标记首次出现时的那幅附图的编号。
具体实施方式
I、引言
本说明书公开了一个或多个包含本发明特点的实施例。公开的实施例仅仅用于举例说明。本发明的保护范围并不限于所公开的实施例。本发明由所附权利要求来限定。
说明书中针对“一个实施例”、“实施例”、“示例实施例”等的引用，指的是描述的该实施例可包括特定的特征、结构或特性，但是不是每个实施例必须包含这些特定特征、结构或特性。此外，这样的表述并非指的是同一个实施例。进一步，在结合实施例描述特定的特征、结构或特性时，不管有没有明确的描述，已经表明将这样的特征、结构或特性结合到其它实施例中是在本领域技术人员的知识范围内的。
此外，应当理解，本发明所使用的空间描述(例如，“在…上面”、“在…下面”、“向上”、“左边”、“右边”、“向下”、“顶部”、“底部”、“垂直”、“水平”等)仅仅为了说明的目的。本发明描述的结构的实施例可以以任何方向或方式进行空间设置。
II、示例实施例
通常使用可以贴在电路板的封装将集成电路(IC)芯片或晶片与其他电路连接。一种这样类型的IC晶片封装是球栅阵列(BGA)封装。BGA封装比许多其他如今可获得的封装解决方案提供更小的脚印底面积。一种类型的BGA封装含有一个或多个贴在封装基底的第一表面的IC晶片，并且含有一系列位于封装基底的第二表面的焊球垫。焊球贴在焊球垫上。焊球回流以使封装贴在电路板上。
一种先进类型的BGA封装是晶圆级BGA封装。晶圆级BGA封装在业界有几个名字，包括晶圆片级芯片规模封装(WLCSP)等等。在晶圆级BGA封装中，当IC晶片还没有从其晶圆制造独立出来时，焊球直接贴装在IC晶片上。这样，晶圆级BGA封装不包括封装基底。因此，相对包括传统BGA封装的其他IC封装类型而言，晶圆级BGA封装可以制造得很小，具有高脚位。
例如，图1所示为传统的晶圆级集成电路封装100的剖面图。如图1所示，封装100包括晶片106、第一电介质层102a、第二电介质层102b和一系列焊球104。晶片106含有多个晶片106的活性表面上的晶片终端(die terminal)，该晶片终端是晶片106信号的I/O衬垫(I/O pad)。第一电介质层102a越过各终端在晶片106的表面上形成，而第二电介质层102b在第一电介质层102a的表面上形成。焊球104在第二电介质层102b的第二表面上形成。在第一和第二电介质层102a和102b与通孔之间的布线层中的布线连接晶片终端与焊球104，所述通孔穿过第一电介质层102a和第二电介质层102b。例如，图1显示晶片106的终端112通过布线层中的迹线110和穿过第二电介质层102b的通孔114与焊球108连接。
图1中的封装100使用扇入布线，因为布线层的布线(例如，迹线110)仅在图1的晶片106的底面区域内形成。图2是传统的使用扇出布线的晶圆级集成电路封装200的剖面图。扇出布线是一类在半导体晶片区域之外延伸(扩展到包围晶片的材料)的布线。例如，如图2所示，封装200包括晶片106、第一电介质层102a、第二电介质层102b、一系列焊球104和绝缘材料204。绝缘材料204包围晶片106，覆盖晶片的四周表面和图2中晶片的顶面，仅仅没有覆盖晶片终端所在的晶片106的活性表面。类似于图1中的封装100，晶片106含有多个晶片106的活性表面上的晶片终端，该晶片终端是晶片106的信号的I/O衬垫。第一电介质层102a越过终端在晶片106的表面上形成，而第二电介质层102b在第一电介质层102a的表面上形成。焊球104在第二电介质层102b的第二表面上形成。
在第一电介质层102a和第二电介质层102b与通孔之间的布线层中的布线连接晶片终端与焊球104，该通孔穿过第一电介质层102a和第二电介质层102b。例如，图2所示的晶片106的终端210通过布线层中的迹线202和穿过第二电介质层102b的通孔208与焊球206连接。迹线202是扇出布线的一个例子，因为迹线202通过围绕晶片106提供的绝缘材料204在半导体晶片区域之外(在晶片106的活性表面的区域之外)延伸。这样，扇出布线在较晶片106的区域更大的区域内传播晶片106的信号，从而为封装200的互联提供额外空间。然而，使用扇出布线的、形成晶圆级封装的传统技术(如封装200)很昂贵，且使用较多的组装步骤。
根据本发明的实施例，将活性半导体器件(例如，晶片)贴在含有通孔的半导体内插器基底(interposer substrate)上，且半导体内插器基底用于连接半导体器件和电路板。内插器基底可以包括多层电路布线区域，其提供扇出布线并与活性半导体器件互连。通过封装材料(例如，模塑料(molding compound))封装活性半导体器件和内插器基底。各种类型的集成电路封装，包括触点阵列(LGA)封装、球栅阵列(BGA)封装、倒装芯片LGA封装、倒装芯片BGA封装等，它们都包括活性半导体器件和半导体内插器基底。例如，互连(例如，焊球)可以贴在内插器基底的表面来形成BGA封装。
本发明的实施例克服了传统的扇出布线封装的局限性。例如，传统的扇出布线封装技术受限于单金属层布线能力，而本发明中具有内插器基底、使用通孔(如硅穿孔(TSV))的实施例可以在内插器基底上设置多层布线层。
例如，图3所示为根据本发明实施例的集成电路封装300的侧面剖面图。如图3所示，封装300包括晶片106、半导体基底306和封装材料304。如图3所示，半导体基底306含有相对的第一表面312和第二表面314。半导体基底306含有多个穿过半导体基底306的通孔310。此外，半导体基底306包括至少一层布线层。布线层可以包括在晶片106的区域之外通过基底306延伸的扇出布线。晶片106贴装在半导体基底306的第一表面312上。封装材料304在半导体基底306的第一表面312上封装晶片106。
半导体基底306可以由半导体材料构成，例如硅或镓砷化物。例如，半导体基底306可以由半导体晶圆制造，并从晶圆中独立出来。半导体基底306可以是有源的(active)(例如，包含有源集成电路逻辑)、或可以是无源的(passive)(不包含逻辑)。如图3所示，半导体基底306可以包括由半导体材料构成的核心半导体层302b，该核心半导体层302b的第一表面312上覆盖有第一绝缘层302a(例如，保护层或阻焊层)、第二表面314上覆盖有第二绝缘层302c(例如，保护层或阻焊层)。在核心半导体层302b具有导电特征(例如，迹线、通孔垫等)的第一表面312上形成的第一布线层可由第一绝缘层302a覆盖、或通过第一绝缘层302a的开口暴露出来。此外，在核心半导体层302b具有导电特性(例如，迹线、通孔垫等)的第二表面314上形成的第二布线层可由第二绝缘层302c覆盖、或通过第二绝缘层302c的开口暴露出来。当按照标准的半导体制造/处理技术(例如，使用光刻法等)形成晶圆时，可以在核心半导体层302b上形成第一绝缘层302a、第二绝缘层302c和许多布线层。本发明所描述的布线层的布线(例如，迹线)和其他导电特征可以由导电材料构成，所述导电材料例如金属或金属/合金混合物，所述金属包括铜、铝、锡、镍、金、银、焊锡等。
当形成晶圆时可形成穿过半导体基底306的通孔310。例如，如图3所示，可以完全穿过核心半导体层302b来形成通孔310。当半导体基底306是硅基底(例如，由硅晶圆形成)，通孔310可以称为硅穿孔(TSV)。
通孔310可以填满或覆盖导电材料(例如金属或金属/合金混合物，所述金属包括铜、铝、锡、镍、金、银、焊锡等)。如图3所示，通孔310包括通孔316。通孔316包括在半导体基底306的第一表面312的第一布线层中形成的第一通孔垫318、和在半导体基底306的第二表面314的第二布线层中形成的第二通孔垫308。通孔316为晶片106的终端320连通基底306形成电连接。终端320是晶片106的电信号(例如，输入-输出信号、电源信号、地面信号、测试信号等)的接入点(例如，又称“晶片衬垫”、“I/O衬垫”等)。在晶片106的表面上可以有许多终端320，包括10s、100s和甚至更多数量的终端320。
如图3所示，终端320与通孔垫308(例如，通过导电黏合材料)连接。这样，终端320通过通孔垫318和通孔316与基底306的第二表面314的通孔垫308电连接。当封装300贴装在电路板时，通孔垫308可以直接或间接地与电路板的焊盘(land pad)连接，从而将终端320的信号与电路板的焊盘电连接。另外，晶片106的终端可能以类似方式与电路板的焊盘电连接。
可能以不同方式形成图3的封装300和本发明另外的封装实施例。例如，接下来分段描述不使用中间载体来形成含有半导体基底的集成电路封装的过程，接着又分段描述使用中间载体来形成半导体基底的集成电路封装的过程。本发明提供的分段描述对半导体内插器基底布线的不同例子和含有半导体内插器基底的IC封装的不同例子进行了描述。应当注意的是，本领域技术人员在本发明的示教下可以任何方式组合本发明所描述的实施例。
A.不使用载体形成封装的实施例
可能以多种方式形成包括半导体内插器基底的集成电路封装，例如，图3中的封装300。例如，图4所示为根据本发明实施例的组装集成电路封装的过程的流程400。为了说明目的，参考图5-11对流程图400进行描述。根据本发明所提供的描述，其他结构和可使用的实施例对本领域技术人员来说是显而易见的。流程图400描述如下。
参考流程图400，在步骤402中，在第一半导体晶圆的多个半导体基底区域中穿通第一半导体晶圆形成多个通孔。例如，图5所示为根据本发明实施例的第一半导体晶圆500的平面图。晶圆500可以是硅晶圆、镓砷化物晶圆或其他类型的晶圆。如图5所示，晶圆500含有由多个半导体基底区域(图5所示的虚线矩形)限定的表面504。每个半导体基底区域502用于按照流程400的过程各自封装成独立的IC封装。晶圆500可以包括任一数量的基底区域502，包括10s、100s、1000s和甚至更多。
按照步骤402，在每个区域502中穿通晶圆500形成多个通孔。例如，每个区域502可以包括多个类似于图3所示的通孔310的通孔。每个通孔可以是圆柱形、可以是如图3所示的圆锥形、或者可以是其他形状。此外，每个通孔可以填充和/或镀上导电材料，并含有形成的通孔垫(例如，类似于图3中所示的通孔垫318和308)。此外，在晶圆上形成一个或多个布线层(和可选绝缘层)，从而提供至穿过晶圆500的导电通孔的导电布线、和从穿通晶圆500的导电通孔至其他导电特征(例如，晶片终端的导电焊盘、焊球垫等)的导电布线。
此外，图6所示为根据本发明实施例的图4的流程图400中执行的可选步骤602。在步骤602，在第一半导体晶圆中测试基底区域以确定一套工作基底。在实施例中，在晶圆500中测试基底区域502以确定工作基底(例如，图3的基底306已通过测试)和非工作基底(未通过测试的基底)。如本领域技术人员所知悉的，在基底区域502上可以执行各种类型和数量的测试。例如，可以执行功能测试(例如，通过探测基底区域502的导电特征来提供测试信号和估量测试结果)，可以执行环境测试等。
在一实施例中，可以对按照步骤602确定为非工作的、晶圆500中的基底区域502做标记。例如，油墨、激光打标或其他类型的标记都可以应用到非工作的基底区域以标示它们不可用。用这种方式，可以识别出任何非工作的基底区域，从而无需对其做进一步处理/使用。
返回参考图4，在步骤404中，多个从第二半导体晶圆独立出来的晶片贴在第一半导体晶圆的表面。例如，图7所示为第二半导体晶圆700的平面图。晶圆700可以是硅晶圆、镓砷化物晶圆或其他类型的晶圆。如图7所示，晶圆700含有由多个集成电路区域(图7所示的小矩形)限定的表面704。可以按照流程图400的过程将一个或多个集成电路区域702封装成独立的IC封装。晶圆700可以包括任一数量的集成电路区域702，包括10s、100s、1000s和甚至更多。
可选地，可通过晶圆减薄(backgrinding)使晶圆700变薄。例如，如果需要和/或有必要的话，可以在晶圆700上执行晶圆减薄处理，从而将晶圆700的厚度减小至所需数值。然而，不一定需要在所有的实施例中都使晶圆700变薄。本领域的技术人员知悉，可能以任何方式使晶圆700变薄。晶圆700可以尽可能地薄，从而帮助使产生的、包括集成电路区域702的封装的厚度最小化。此外，可以在晶圆700中测试每个集成电路区域702。例如，可以在晶圆700的终端320(图7未示出)应用测试探针，其提供测试输入信号和接收测试输出信号、以测试每个集成电路区域702。
本领域技术人员知悉，可能以任何恰当的方式将晶圆700独立/切成粒，以使集成电路区域相互地物理分开。例如，可能以传统的或其他方式，通过锯、刨槽机、激光等将晶圆700独立出来。晶圆700的独立可以形成10s、100s、1000s、或更多的晶片106(图3的)，其与晶圆700的集成电路区域702的数量相对应。
根据图4的步骤404，从第二半导体晶圆(如图7的晶圆700)独立出来的一个或多个晶片可以贴装第一半导体晶圆500(图5所示)的表面504上，这样每个基底区域502含有至少一个贴在其上的晶片。例如，图8所示为根据本发明实施例的具有晶片106的晶圆500表面504的示意图，这样晶片106贴在每个基底区域502上。图9所示为根据本发明实施例的晶圆500的一部分的侧面剖面图，所示的第一晶片106a和第二晶片106b分别贴装第一基底区域502a和第二基底区域502b上。晶片106可以以任何方式位于和/或置于基底区域502上，包括通过使用拾取与放置装置(pick-and-place apparatus)、自对准处理或其他技术。晶片106的终端可以与基底区域502上的导电焊盘对准，以使基底区域502的布线与晶片106的信号连接。例如，焊锡或其他导电材料(例如，金属或金属/合金混合物)可用于连接终端与导电衬垫。在基底区域502上放置晶片106之前，在基底区域502的表面和/或晶片106的活性表面可以使用黏合材料，和/或在粘贴(例如，填充材料)之后可在晶片106和基底区域502之间插入黏合材料。黏合材料可用于帮助将晶片106黏合到基底区域502上。可使用任何合适的黏合材料，包括传统的晶片材料(die-attach material)、环氧树脂、粘性膜等。
此外，应当注意的是，晶片106的终端包括晶片的信号/晶片衬垫，且包括一个或多个在晶片衬垫上形成的金属层，将其称为凸点下金属(UBM)层。UBM层通常是由一个或多个金属层形成(例如，金属沉积——电镀、溅射等)，从而在晶片衬垫与额外布线和/或封装互联机构之间(例如，管脚(stud)或焊球)提供鲁棒连接。
返回参考图4，在步骤406中，在第一半导体晶圆的表面上封装晶片。例如，图10所示为根据本发明实施例的图9所示的具有封装晶片的晶圆500的一部分的侧面剖视图。图9所示的具有封装晶片的晶圆500可以称作“模制组件”1000。如图10所示，应用于晶圆500表面504的模塑料1002将贴在基底区域502a的晶片106a和贴在基底区域502b的晶片106b封装起来。模塑料1002是可用于封装晶圆500上的晶片106的封装材料的一个例子。可以任何方式将模塑料1002应用于晶圆500，包括按照真空模塑处理等。例如，在一实施例中，所制造的模塑位于晶圆500(贴有晶片106)表面504，且模塑料1002可插入到模塑中(例如，以液态形式)，并凝固从而封装晶圆500上的晶片106。本领域的技术人员知悉合适的封装材料(例如模塑料)，包括松香、环氧树脂等。
返回参考图4，在步骤408中，将第一半导体晶圆独立出来，从而分成多个基底区域以形成多个集成电路封装，每个集成电路封装包括至少一个晶片。例如，图11所示为根据本发明实施例的、从图10中的模制组件1000独立出来的第一IC封装1100a和第二IC封装1100b的示意图。可从模制组件独立出来任一数量的IC封装1100，其包括10s、100s、或甚至上千个IC封装1100。如图11所示，IC封装1100a包括贴装在基底306a的晶片106a和在基底306a上封装晶片106a的模塑料1002。此外，IC封装1100b包括贴装在基底306b的晶片106b和在基底306b上封装晶片106b的模塑料1002。通过将基底区域502a从晶圆500中独立出来而形成基底306a，通过将基底区域502b从晶圆500中独立出来而形成基底306b。
本领域的技术人员知悉，可以任何恰当的方式将IC封装1100从模制组件1000独立出来，以使它们相互地物理分开。例如，可能以传统方式或其他方式，通过锯、刨槽机、激光等来将IC封装1100独立出来。可以通过切割模塑料1002来将图11的IC封装1100a和IC封装1100b从模制组件1000中独立出来，以使IC封装1100a和IC封装1100b相互分开，并与其它IC封装1100(图10未示出)分开。
B、使用载体形成封装的实施例
可使用载体以各种方式形成包括半导体内插器基底的集成电路封装，如图3的封装300。例如，图12所示为根据本发明实施例的组装集成电路封装的示例性过程的流程图。为了说明的目的，参考图13-18对流程图1200进行描述。根据本发明所提供的描述，其他结构和可使用的实施例对本领域的技术人员来说是显而易见的。流程图1200描述如下。
参考流程图1200，在步骤1202中，在第一半导体晶圆的多个半导体基底区域中形成穿过第一半导体晶圆的多个通孔。例如，如参考图5所描述的，在每个区域502中形成穿过晶圆500的多个通孔，其类似于图3所示的通孔310。此外，类似于上面提供的描述，可在流程图1200中执行图6所示的可选步骤602，从而测试在晶圆500的基底区域502，以确定一套工作基底。
在步骤1204中，将第一半导体晶圆独立出来以形成与多个基底区域相一致的多个基底。例如，参考图5，本领域的技术人员知悉，可能以任何恰当的方式将晶圆500独立/切成粒，以使基底区域502相互地物理分开，从而形成多个单独的基底。例如，可能以传统方式或其他方式，通过锯、刨槽机、激光等来将晶圆500独立出来。晶圆500的独立可以形成10s、100s、1000s、或更多的晶片306(图3的)，其与晶圆500的基底区域502的数量相对应。
返回参考图12，在步骤1206中，将基底贴在载体的表面上。在一实施例中，将基底(例如上述从晶圆500独立出来的基底306)贴在载体表面。在一实施例中，将从晶圆500独立出来的、通过测试的一组基底(例如，如上所述的工作基底)贴在载体上。未通过测试的基底(例如，非工作基底)则不会贴在载体上。
例如，图13所示为根据本发明实施例的贴有多个基底306的、含有平坦表面的载体1302的示意图。基底306可能以任何方式位于/置于载体1302的表面1304，包括通过使用拾取与放置装置、自对准处理或其他技术。在表面1304上放置基底306之前，在表面1304和/或基底306表面可以使用黏合材料，以将基底306粘附在表面1304上。可使用任何合适的黏合材料，包括环氧树脂、黏合膜等。
在图13的示例中，所示的25个基底306贴在载体1302的表面1304上。然而，在实施例中，可以将任一数量的基底306贴在载体表面，包括几十、几百、或甚至几千个基底306。在一个实施例中，基底306可以在载体1302的表面1304上互相毗连(例如，互相接触)放置。在另一个实施例中，如图13所示，基底306可以在载体1302的表面1304上分开放置。在特殊应用中，基底306可能以任何距离分开放置。
任何合适类型的载体都可以用于接收分离的基底，包括由陶瓷、玻璃、塑料、半导体材料(例如硅、镓砷等)、金属或其他材料制成的载体。载体可以具有接收基底306的平坦表面。这样的载体可以具有任何外形，包括圆形、矩形或其他形状。例如，图13所示为具有矩形(例如，正方形)形状的载体1302。在一个实施例中，载体1302可以是半导体晶圆(例如硅、镓砷等)，或可以由其他材料如塑料、陶瓷、玻璃、金属等制成。
返回参考图12，在步骤1208中，从第二半导体晶圆独立出来的多个晶片贴在基底上。例如，如上所述，图7显示第二半导体晶圆700的平面图。可选地，可通过晶片减薄使晶圆700变薄，并且可在晶圆700中测试晶圆700的每个集成电路区域702。如上所述，可能以任一恰当方式对晶圆700进行独立/切成粒，从而使集成电路区域彼此分开来形成单独的晶片。
图14所示为根据本发明实施例的贴有基底306的载体1302的表面1304的示意图，其中在每个基底306上都贴有IC晶片106。可能以任何方式使晶片106位于/置于基底306上，包括通过使用拾取与放置装置、自对准处理或其他技术。晶片106的终端可以与基底306上的导电焊盘对准，以连接晶片106的信号与基底306的布线。例如，焊锡或其他导电材料(例如，金属或金属/合金混合物)可以用于连接终端与导电衬垫。在基底306上放置晶片106之前，在基底306的表面和/或晶片106的非活性表面可以使用黏合材料，和/或在粘贴(例如，填充材料)之后，在晶片106和基底306之间可插入黏合材料。黏合材料可以用于帮助将晶片106黏合到基底306。可使用任何合适的黏合材料，包括环氧树脂、黏合膜等。
例如，图15所示为根据本发明实施例的载体1302的一部分的剖面图。如图15所示，基底306a和基底306b贴在载体1302的表面1304上。如图3所示，每个基底306含有相对的第一表面312和第二表面314，其中，将第二表面314贴在载体1302的表面1304上。晶片106贴在基底306a的第一表面312，以及晶片106b贴在基底306b的第一表面312。如本发明所描述，可以使用导电镀层、管脚或凸点(bumps)将晶片106贴在基底306上，从而作为每个晶片106和基底306之间的信号互连。此外，如上面所描述，晶片106的终端包括晶片106的信号垫，以及可包括一个或多个在晶片衬垫上形成的金属层，将其称为UBM层。
此外，应当注意的是，晶片106的终端包括晶片的信号/晶片衬垫，且包括一个或多个在晶片衬垫上形成的金属层，将其称为凸点下金属(UBM)层。UBM层通常是由一个或多个金属层形成(金属沉积——电镀、溅射等)，从而在晶片衬垫与额外布线和/或封装互联机构之间(例如，管脚或焊球)提供鲁棒连接。
返回参考图12，在步骤1210中，使用封装材料在载体上封装晶片。例如，图16所示为根据本发明实施例的含有封装晶片和基底的载体1302的侧面剖面图。如图16所示，基底306a和基底306b贴在载体1302的表面1304，以及晶片106a和晶片306b分别贴在基底306a和基底306b上。此外，模塑料1602封装载体1302上的基底306a、基底306b、晶片106a和晶片106b。模塑料1602是用于封装载体1302上的基底306a、基底306b、晶片106a和晶片106b的封装材料的一个例子。模塑料1002可能以任何方式应用于载体1302，包括按照真空模塑处理等。例如，在一实施例中，所制造的模塑位于载体1302(具有基底和晶片)的表面1304上，且模塑料1602可插入到模塑(例如，以液态形式)中，并凝固以封装载体1302上的基底306和晶片106。本领域技术人员知悉合适的封装材料，例如包括松香、环氧树脂等的模塑料。
在步骤1212中，从封装好的晶片和基底中将载体分离出来，以形成模制组件，该模塑组件包括用于封装晶片和基底的封装材料。例如，图17所示为根据本发明实施例的、从封装好的基底和晶片中移走/分离出来的载体1302剖面图。在图17中，基底306a和306b、晶片106a和106b以及模塑料1602形成从载体1302分离出来的模制组件1702。基底306a和306b的底面与模制组件1702的表面(图17中的底面)齐平或暴露在模制组件1702的表面。否则，在模制组件1702中通过模塑料1602将晶片106a和106b以及基底306a和306b封装起来。载体1302可能以任何方式从模制组件1702中分离出来。例如，模制组件1702可以从载体1302中剥落下来，可以加热或冷冻模制组件1702和/或载体1302，从而引起或使得载体1302从模制组件1702分离出来等。在一实施例中，相比黏附载体1302，模塑料1602对基底306a和306b的黏附更牢固(例如，比黏合材料将基底306a和306b黏附到载体1302更牢固)，以使得基底306a和306b能与模塑料1602一起从载体1302中分离出来，而不是使得基底306a和306b在分离后留在载体1302上。
返回参考图12，在步骤1214中，模制组件从多个集成电路封装中独立出来，每个集成电路封装包括至少一个晶片和至少一个基底。例如，图18所示为根据本发明实施例的从图17的模制组件1700中独立出来的第一IC封装1800a和第二IC封装1800b的示意图。可以从模塑组件独立出任一数量的IC封装1800，包括10s、100s、或者甚至几千个IC封装1800。如图18所示，IC封装1800a包括贴装在基底306a的晶片106a、和在基底306a上封装晶片106a的模塑料1702。此外，IC封装1800b包括贴装在基底306b的晶片106b、和在基底306b上封装晶片106b的模塑料1702。
本领域的技术人员知悉，可能以任何恰当的方式将IC封装1800从模制组件1700中独立出来，以使它们相互地物理分开。例如，可能以传统方式或其他方式，通过锯、刨槽机、激光等来将IC封装1800独立出来。可以通过切割模塑料1602来将图18的IC封装1800a和IC封装1800b从模制组件1700中独立出来，以使IC封装1800a和IC封装1800b相互分开，并与其它IC封装1800(图17未示出)分开。在一个实施例中，可以直接在基底306的四周边缘的邻近进行切割，使得模塑料1702不会留在IC封装1800a的基底306a和IC封装1800b的基底306b的四周边缘(即如图18所示，基底四周边缘暴露)。可选择地，可以远离基底306a和基底306b的四周边缘进行切割，使得一些模塑料1702留下以覆盖IC封装1800a的基底306a和IC封装1800b的基底306b的四周边缘(基底四周边缘未暴露)。
C、示例性封装实施例
如上所述，根据本发明实施例，可能以各种方式形成IC封装，(例如，图3的封装300、图11的封装1100a和1100b、以及图18的封装1800a和1800b)。这样的封装包括半导体基底，例如基底306，其包括将贴装晶片的信号与封装互连连接的通孔和布线。这样的通孔和布线可能以任何方式构造，包括任一数量的通孔和任一数量的布线层。
例如，图19所示为根据本发明实施例的IC封装1900的一部分的侧面剖面图。封装1900示出了布线的示例，本领域的技术人员知悉，通过本发明的示教可能以各种方式对该布线进行修改。如图19所示，封装1900包括晶片106、半导体基底1902、焊接凸点1904、以及互连凸点1906。焊接凸点是将晶片的终端1940贴在基底1902上。互连凸点1906是将基底1902贴到电路板上(图19未示出)。在本实施例中可以有任一数量的焊接凸点1904和/或互连凸点1906。下面将进一步对封装1900进行描述。
如图19所示，在基底1902的表面1938上形成布线，以按路线从焊接凸点1904向穿过基底1902的通孔1918传递信号。例如，如图19所示，基底1902包括核心半导体层1922、在第一表面1938的核心半导体层1922上形成的第一绝缘层1924、在第一绝缘层1924上形成的第一布线层1934、以及在布线层1934上形成的第二绝缘层1926。通孔1918是完全穿过核心半导体层1922的通孔。通孔1918含有在核心半导体层1922的第一表面的第一通孔垫1916、以及在核心半导体层1922的第二表面的第二通孔垫1920。迹线1912是在布线层1934中形成的，布线层1934通过在迹线1912的第一末端的第一绝缘层1924中的开口连接至通孔垫1916。迹线1912也可以被称为重分布层(redistribution layer)或重分布互连(redistribution interconnect)。通过在迹线1912的第二末端或其附近的第二绝缘层1926的开口1910、在迹线1912上形成焊盘1908。焊接凸点1904贴在焊盘1908上。焊盘1908可包括多层导电材料。例如，焊盘1908可能是UBM层，UBM层通常是由一个或多个金属层形成(金属沉积——电镀、溅射等)，以在终端1940与额外布线和/或封装互连机构之间(例如，管脚或焊球)提供鲁棒连接。金属层可以由不同的金属和/或合金形成，以使得包括第一金属/合金的焊接凸点1904黏附可由不同的第二金属/合金制成的迹线1912。
如图19所示，迹线1912是由基底1902提供的晶片106的扇出布线。这是因为迹线1912越过基底1902在面向基底1902的晶片106的活性表面(晶片106的表面1942)区域之外延伸。换言之，迹线1912越过基底1902的第一表面1938在晶片和基底1902之间的区域之外延伸。这样，迹线1912从晶片106扇出，而为了通过相应的迹线按路线发送晶片106终端的信号，基底1902提供比晶片106区域更大的表面积，使得封装1900更加容易地贴装在电路板上(使其有较大的焊盘空间)。如图19所示，在晶片106下面的焊球1906部分地延伸至晶片106区域之外(至图19的右边)。在另一实施例中，焊球1906可以全部位于晶片106的区域之外(例如，进一步至图19的右边)。
如图19所示，在基底1902的第二表面1940上形成布线，从而从通孔1918向焊球1906按路线发送信号。例如，如图19所示，基底1902包括在第二表面1940的核心半导体层1922上形成的第二布线层1936，以及在布线层1936上形成的第三绝缘层1928。布线层1936包括通孔1918的通孔垫1920、迹线1932和焊球垫1930。迹线1932连接通孔垫1920和焊球垫1930。通孔垫1920、迹线1932和焊球垫1930通过第三绝缘层1928中的开口暴露出来。互连焊球1906在焊球垫1930上形成。这样，形成了通过半导体基底1902的电连接，所述电连接从焊接凸点1904、通过焊盘1908、迹线1912，通孔垫1916、通孔1918、通孔垫1920、迹线1932、焊球垫1930、到达互连焊球1906。该电连接使晶片106终端1940的信号与贴装有封装1900的电路板上的焊盘电连接。可能以类似方式通过基底1902形成任一数量的电连接。
应当注意的是，虽然所示的信号布线层1934在基底1902的第一表面1938、所示的信号布线层1936在基底1902的第二表面1940，但任一数量的额外布线层可存在于表面1938和1940的其中一个或两个，从而通过基底1902将信号按路线发送至焊接凸点1904和/或焊球1906。此外，在实施例中，互连焊球1906可以直接在通孔垫1920上形成、和/或焊接凸点1904可以直接在通孔垫1916上形成。在实施例中，可存在或可不存在形成各种封装类型的焊接凸点1904和/或互连焊球1906。
例如，图3和图20-22示出了根据本发明实施例的包括半导体内插器基底的IC封装。上述图3的封装300是触点阵列(LGA)封装的一个示例。LGA封装(例如封装300)是一类集成电路(IC)的表面贴装(surface-mount)封装，该集成电路(IC)含有一系列用于将封装贴装在电路板上的衬垫。可通过使用插口(socket)(含有管脚)或通过将衬垫直接焊至电路板使LGA封装与印制电路板(PCB)电连接。
图20所示为球栅阵列(BGA)封装2000的侧面剖面图。BGA封装2000类似于图3的封装300，其具有额外的一系列焊球2002，焊球2002贴在基底306的第二表面314的焊球垫上。焊球2002回流以使BGA封装2000贴在电路板上。当形成晶圆时(例如，流程图400的附加步骤的晶圆500)，或在基底306从晶圆分离出来之后，可以将焊球2002贴在基底306上。
图21所示为触点阵列(LGA)封装2000的侧面剖面图。LGA封装2100类似于图3的封装300的一类LGA封装，其具有额外的一系列焊接凸点2104，焊接凸点2104贴在晶片106的终端，以将晶片106贴装在基底306的第一表面312的焊垫上。图21的LGA封装2100可以称为倒装芯片LGA封装。
图22所示为球栅阵列(BGA)封装2200的侧面剖面图。类似于图20的封装2000，BGA封装220具有额外的一系列焊接凸点2104，焊接凸点2104贴在晶片106的终端，以将晶片106贴装在基底306的第一表面312的焊垫上。图22的BGA封装2200可以称为倒装芯片BGA封装。
在实施例中，可在基底306的第二表面314上形成各种互连形式以将封装贴到电路板上。这样的互连的示例包括BGA封装的球形互连(例如，焊球2002)、管脚(例如，管脚阵列封装(PGA))、贴或其他类型的互连。这样的互连可能以任何方式应用于基底，包括按照传统技术和有专利权的技术。
应当注意的是，在实施例中，包含于IC封装(例如，封装300、封装1100a和1100b、封装1800a和1800b等)的半导体基底可以是有源的或无源的。例如，图19所示的基底1902可选地包含有源集成电路逻辑1950。当其存在时，有源集成电路逻辑1950使基底1902成为有源半导体基底。当其不存在时，基底1902是无源半导体基底。逻辑1950可包含任一形式的逻辑(例如，晶体管、逻辑门等形式)，例如用于执行任一逻辑功能的处理逻辑。逻辑1950可与基底1902中的通孔和/或布线连接，从而与晶片106的信号电连接。
推论
尽管以上对本发明的各个实施例进行了描述，但应该理解的是，它们仅用于示例说明而非限制目的。对本领域技术人员而言显而易见的是，在不背离本发明的精神和范围的情况下可对其形式和细节作出各种改变。因此，本发明的宽度和范围并不应受限于上述任一示例性实施例，而仅应该依照以下所附的权利要求及其等效替换来限定。

Claims (10)

1.一种集成电路封装的组装方法，其特征在于，所述方法包括：
在第一半导体晶圆的多个半导体基底区域中形成穿过所述第一半导体晶圆的多个通孔；
将多个从第二半导体晶圆独立出来的晶片贴在所述第一半导体晶圆的表面；
在所述第一半导体晶圆的所述表面对所述晶片进行封装；及
将所述第一半导体晶圆独立出来以分离多个半导体区域，以形成多个集成电路封装，每个集成电路封装包括至少一个所述晶片和与基底区域相对应的基底，每个基底包括扇出布线。
2.根据权利要求1所述的集成电路封装的组装方法，其特征在于，所述第一半导体晶圆为硅晶圆，所述通孔为硅穿孔。
3.根据权利要求1所述的集成电路封装的组装方法，其特征在于，所述方法还包括：
在所述独立之前，测试所述第一半导体晶圆中的所述基底区域，以确定一套工作基底。
4.根据权利要求1所述的集成电路封装的组装方法，其特征在于，所述方法还包括：
在每个所述半导体区域的所述第一半导体晶圆的表面形成布线。
5.根据权利要求1所述的集成电路封装的组装方法，其特征在于，所述贴包括：
使用一系列焊接凸点将每个晶片贴装在基底区域。
6.根据权利要求1所述的集成电路封装的组装方法，其特征在于，所述方法还包括：
在所述独立之前，在所述第一半导体晶圆的第二表面上形成多个互连凸点；
其中每个集成电路封装包括所述多个互连凸点中的互连凸点，所述多个互连凸点用于连接所述集成电路封装和电路板。
7.根据权利要求1所述的集成电路封装的组装方法，其特征在于，每个集成电路封装表面的一系列导电衬垫用于将所述集成电路封装与电路板连接为触点阵列封装。
8.一种集成电路封装的组装方法，其特征在于，所述方法包括：
在第一半导体晶圆的多个半导体基底区域形成穿过所述第一半导体晶圆的多个通孔；
将所述第一半导体晶圆独立出来以形成与所述多个基底区域相对应的多个基底；
将所述基底贴在载体表面；
将多个从第二半导体晶圆独立出来的晶片贴到所述基底；
使用封装材料对所述载体所述基底上的所述晶片进行封装；
从封装好的晶片和基底中将所述载体分离出来，以形成模制组件，所述模制组件包括用于封装所述晶片和所述基底的封装材料；及
将所述模制组件独立出来以形成多个集成电路封装，每个集成电路封装包括所述晶片的至少一个和所述基底的至少一个，每个基底包括扇出布线。
9.根据权利要求8所述的集成电路封装的组装方法，其特征在于，所述方法还包括：
在所述将所述第一半导体晶圆独立之前，测试所述第一半导体晶圆中的所述基底区域，以确定一套工作基底。
10.一种集成电路封装，其特征在于，所述集成电路封装包括：
含有相对的第一和第二表面的硅基底、多个穿过所述硅基底的通孔和至少在所述硅基底的所述第一表面的布线；
贴装在所述硅基底的所述第一表面的晶片；
封装所述硅基底的所述第一表面上的所述晶片的封装材料。
CN2012100203153A 2011-01-24 2012-01-29 一种集成电路封装及其组装方法 Pending CN102768962A (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201161435648P 2011-01-24 2011-01-24
US61/435,648 2011-01-24
US13/173,109 2011-06-30
US13/173,109 US20120187545A1 (en) 2011-01-24 2011-06-30 Direct through via wafer level fanout package

Publications (1)

Publication Number Publication Date
CN102768962A true CN102768962A (zh) 2012-11-07

Family

ID=46543579

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2012100203153A Pending CN102768962A (zh) 2011-01-24 2012-01-29 一种集成电路封装及其组装方法

Country Status (3)

Country Link
US (1) US20120187545A1 (zh)
CN (1) CN102768962A (zh)
TW (1) TW201250872A (zh)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106876364A (zh) * 2017-03-15 2017-06-20 三星半导体(中国)研究开发有限公司 半导体封装件及其制造方法
CN109564902A (zh) * 2016-08-01 2019-04-02 康宁股份有限公司 基于玻璃的电子件封装及其形成方法
CN112385024A (zh) * 2018-10-11 2021-02-19 深圳市修颐投资发展合伙企业（有限合伙） 扇出封装方法及扇出封装板

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9137903B2 (en) * 2010-12-21 2015-09-15 Tessera, Inc. Semiconductor chip assembly and method for making same
US8772058B2 (en) * 2012-02-02 2014-07-08 Harris Corporation Method for making a redistributed wafer using transferrable redistribution layers
US20130214408A1 (en) * 2012-02-21 2013-08-22 Broadcom Corporation Interposer Having Conductive Posts
TWI534965B (zh) * 2012-09-17 2016-05-21 矽品精密工業股份有限公司 半導體封裝件及其製法
US9087777B2 (en) * 2013-03-14 2015-07-21 United Test And Assembly Center Ltd. Semiconductor packages and methods of packaging semiconductor devices
KR101514137B1 (ko) * 2013-08-06 2015-04-21 앰코 테크놀로지 코리아 주식회사 반도체 패키지 제조 방법 및 이를 이용한 반도체 패키지
US9418924B2 (en) * 2014-03-20 2016-08-16 Invensas Corporation Stacked die integrated circuit
US9972593B2 (en) 2014-11-07 2018-05-15 Mediatek Inc. Semiconductor package
WO2017107174A1 (en) * 2015-12-25 2017-06-29 Intel Corporation Flip-chip like integrated passive prepackage for sip device
KR102482700B1 (ko) * 2016-03-11 2022-12-28 삼성전자주식회사 반도체 패키지 테스트 방법
US10593630B2 (en) 2018-05-11 2020-03-17 Advanced Semiconductor Engineering, Inc. Semiconductor package and method for manufacturing the same
US11282777B2 (en) * 2019-12-31 2022-03-22 Advanced Semiconductor Engineering, Inc. Semiconductor package and method of manufacturing the same

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030092217A1 (en) * 2001-02-02 2003-05-15 Coyle Anthony L. Flip chip semiconductor device in a molded chip scale package (CSP) and method of assembly
CN1716587A (zh) * 2004-06-30 2006-01-04 新光电气工业株式会社 内插器及其制造方法以及使用该内插器的半导体器件
CN1722412A (zh) * 2004-01-07 2006-01-18 三星电子株式会社 封装电路板和包括封装电路板的封装及其方法
US20080211089A1 (en) * 2007-02-16 2008-09-04 Broadcom Corporation Interposer for die stacking in semiconductor packages and the method of making the same
CN101728363A (zh) * 2008-10-31 2010-06-09 日月光半导体制造股份有限公司 晶片封装结构及其制作方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8103996B2 (en) * 2008-06-24 2012-01-24 Cadence Design Systems, Inc. Method and apparatus for thermal analysis of through-silicon via (TSV)
US8895440B2 (en) * 2010-08-06 2014-11-25 Stats Chippac, Ltd. Semiconductor die and method of forming Fo-WLCSP vertical interconnect using TSV and TMV
US8518746B2 (en) * 2010-09-02 2013-08-27 Stats Chippac, Ltd. Semiconductor device and method of forming TSV semiconductor wafer with embedded semiconductor die

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030092217A1 (en) * 2001-02-02 2003-05-15 Coyle Anthony L. Flip chip semiconductor device in a molded chip scale package (CSP) and method of assembly
CN1722412A (zh) * 2004-01-07 2006-01-18 三星电子株式会社 封装电路板和包括封装电路板的封装及其方法
CN1716587A (zh) * 2004-06-30 2006-01-04 新光电气工业株式会社 内插器及其制造方法以及使用该内插器的半导体器件
US20080211089A1 (en) * 2007-02-16 2008-09-04 Broadcom Corporation Interposer for die stacking in semiconductor packages and the method of making the same
CN101728363A (zh) * 2008-10-31 2010-06-09 日月光半导体制造股份有限公司 晶片封装结构及其制作方法

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109564902A (zh) * 2016-08-01 2019-04-02 康宁股份有限公司 基于玻璃的电子件封装及其形成方法
CN106876364A (zh) * 2017-03-15 2017-06-20 三星半导体(中国)研究开发有限公司 半导体封装件及其制造方法
US10319611B2 (en) 2017-03-15 2019-06-11 Samsung Electronics Co., Ltd. Semiconductor device package with warpage prevention
US10796930B2 (en) 2017-03-15 2020-10-06 Samsung Electronics Co., Ltd. Semiconductor device with decreased warpage and method of fabricating the same
CN112385024A (zh) * 2018-10-11 2021-02-19 深圳市修颐投资发展合伙企业（有限合伙） 扇出封装方法及扇出封装板
US11710646B2 (en) 2018-10-11 2023-07-25 Shenzhen Xiuyi Investment Development Partnership (Limited Partnership) Fan-out packaging method and fan-out packaging plate
CN112385024B (zh) * 2018-10-11 2023-11-10 深圳市修颐投资发展合伙企业（有限合伙） 扇出封装方法及扇出封装板

Also Published As

Publication number Publication date
TW201250872A (en) 2012-12-16
US20120187545A1 (en) 2012-07-26

Similar Documents

Publication Publication Date Title
KR102637279B1 (ko) 매립된 인덕터 또는 패키지를 갖는 집적 sip 모듈을 형성하는 반도체 소자 및 방법
CN102768962A (zh) 一种集成电路封装及其组装方法
KR102711657B1 (ko) 양-측 몰딩을 갖는 시스템-인-패키지
KR102259482B1 (ko) 3d 인터포저 시스템-인-패키지 모듈을 형성하기 위한 반도체 소자 및 방법
KR101402868B1 (ko) 재구성 패널 처리 포맷에 의한 칩 스케일 패키지 어셈블리
US7741156B2 (en) Semiconductor device and method of forming through vias with reflowed conductive material
TW201916186A (zh) 半導體裝置與形成嵌入式晶粒基板的方法以及具有其之系統級封裝模組
TWI523126B (zh) 在包含膠封或包含在具有與晶圓級晶片尺寸封裝的大型陣列中的熱膨脹係數相似的熱膨脹係數的空白晶粒之印刷電路板中形成孔穴的半導體裝置和方法
US10121736B2 (en) Method of fabricating packaging layer of fan-out chip package
CN103715166A (zh) 用于部件封装件的装置和方法
US20170186711A1 (en) Structure and method of fan-out stacked packages
US20160204082A1 (en) Method of manufacturing semiconductor device
CN114497019A (zh) 一种多芯片立体集成结构及制作方法
KR20160041581A (ko) 적층형 반도체 패키지 및 이의 제조 방법
CN115527972A (zh) 高密度互联三维集成器件封装结构及其制造方法
TWI768874B (zh) 封裝結構及其製作方法
US6855573B2 (en) Integrated circuit package and manufacturing method therefor with unique interconnector
TW201911501A (zh) 電子封裝件及其製法
US20050093170A1 (en) Integrated interconnect package
KR20230036986A (ko) 양면 부분 몰딩된 sip 모듈
KR101375818B1 (ko) 직접 관통하는 비아 웨이퍼 레벨 팬아웃 패키지
KR101502428B1 (ko) 반도체 패키지 및 이의 제조 방법
US12068260B2 (en) Semiconductor die package with ring structure and method for forming the same
US20240363551A1 (en) Semiconductor die package with ring structure and method for forming the same
US11676826B2 (en) Semiconductor die package with ring structure for controlling warpage of a package substrate

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
REG Reference to a national code

Ref country code: HK

Ref legal event code: DE

Ref document number: 1175030

Country of ref document: HK

C12 Rejection of a patent application after its publication
RJ01 Rejection of invention patent application after publication

Application publication date: 20121107