TW201250872A - Direct through via wafer level fanout package - Google Patents

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Publication number
TW201250872A
TW201250872A TW101102428A TW101102428A TW201250872A TW 201250872 A TW201250872 A TW 201250872A TW 101102428 A TW101102428 A TW 101102428A TW 101102428 A TW101102428 A TW 101102428A TW 201250872 A TW201250872 A TW 201250872A
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TW
Taiwan
Prior art keywords
wafer
substrate
integrated circuit
package
semiconductor
Prior art date
Application number
TW101102428A
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English (en)
Inventor
Rezaur Rahman Khan
Edward Law
Ken Jian Ming Wang
Original Assignee
Broadcom Corp
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Application filed by Broadcom Corp filed Critical Broadcom Corp
Publication of TW201250872A publication Critical patent/TW201250872A/zh

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    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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Description

201250872 六、發明說明： 【發明所屬之技術領域] 本發明涉及積體電路封裝。 【先前技術】 通系使用可以貼在電路板的封裂將積體電路⑻）曰 片或晶片與其他電路連接。—贿__ ic晶片封二 die package)是球柵陣列（BGA)縣。bga封裝比又 其他如今可獲得的封料決方案提供更小的腳印底面積了 -種類t^BGA封裝含有—個❹個貼在封裝基底的第一 表面的1C晶片’並且含有—系列位於封裝基底的第二表面 的焊球塾。焊賴在焊輕上。焊球回流賤封裝貼在電 路板上。 -種先進類型的BGA縣是晶圓級BGA封裳。 級BGA封裝在業界有幾個名字，包括晶圓片級晶片規模封 裝（WLCSP)等。在晶圓級BGA封裝中，當lc晶片還沒 有從其晶圓製造獨立出來（singulate)時，焊球直接貼裝在 1C晶片上。這樣’晶圓級BGA封裝不包括封裝基底。因此， 相對包括傳統BGA封褒的其他1〇封裝類型，晶圓級BGA 封裝可以製造得彳艮小，具有高腳位（highpin〇ut)。 對於用於晶圓級BGA封裝的ic晶片，通常直接在晶 片上形成佈線。佈線在口的表面形成，以按佈線將晶片 襯塾的信號發送至焊球貼在晶片上的位置。扇人佈線和扇 出佈線是可在晶片上形成的兩種不同類型的佈線方式。扇 入佈線是一類僅在每個半導體晶片的區域之内形成的佈 線。扇出佈線是一類在半導體晶片的區域之外延伸（擴展 到包圍晶片的材料）的佈線。 3/36 201250872 這樣’扇出佈線在較晶片區域更大的區域内傳遞j c曰 片的信號’從而為產生的積體電路封裝提供額外的互= 如’焊球）如。然而’形成晶圓級封裝的傳統技術由於 使用扇出佈線比較昂貴，且使用較多的組裝步驟。這樣， 需要使能製造晶片規模封I的積體電路封裝的組裝技術， 且該技術不昂貴並使用更少的處理步驟。 【發明内容】 本發明描述了通過將積體電路晶片貼裝到半導體基底 來形成積體電_裝的方法、系統和U，該半導體基底 具有多層佈線和通過半導體基底的通孔（vias)，結合至少 -幅附圖進彳了了詳細描述，並在申料利範财得到了更 完整的闡述。 •根據本發明的-個方面’提供—種方法，所述方法包 括· 在第一半導體晶®的多個半導體基底區域中形成穿過 所述第一半導體晶圓的多個通孔； 將多個從第二半導體晶圓獨立出來的晶片貼在所述第 一半導體晶圓的表面； 在所述第一半導體晶圓的所述表面對所述晶片進行封 装；及 ^將所述第一半導體晶圓獨立出來以分離多個半導體區 ^ 乂幵7成夕個積體電路封裝，每個積體電路封裝包括至 少一個所述晶片和與基底區域相對應的基底，每個基底包 括扇出佈線。 車又佳地，所述第一半導體晶圓為矽晶圓，所述通孔為 矽穿孔。 4/36 201250872 較佳地，所述方法還包括： 在所述獨立之前，測試所述第一半導體晶圓中的所述 基底區域’以確疋一套工作基底（w〇rking substrate)。 較佳地，所述方法還包括： 在每個所述半導體區域的所述第一半導體晶圓的表面 形成佈線。 較佳地，所述貼包括： 使用一系列焊接凸點將每個晶片貼裝在基底區域。 較佳地，所述方法還包括： 在所述獨立之前，在所述第一半導體晶圓的第二表面 上形成多個互連凸點（interconnect ); 其中每個積體電路封裝包括所述多個互連凸點中的互 連凸點’所料個互連凸點躲連賴述積體電路封裝和 電路板。 幸父佳地，每個積體電路封裝表面的一系列導電襯墊用 於將所述積體電路封裝與電路板連接為_陣列封褒。 .根據本發明的-個方面，提供—種方法，所述方法包 括： 、、在第一半導體晶圓的多個半導體基底區域形成穿過所 述第一半導體晶圓的多個通孔； 將所述第-半導體晶圓獨立出來以形成與所述多 底區域相對應的多個基底； 土 將所述基底貼在载體表面； 將夕個攸第二半導體晶圓獨立出來的晶片貼到所述基 底， 使用封裝材料對所述载體所述基底上的所述晶片進行 5/36 201250872 封骏； 從封裝好的晶片 成模制元件，所述模 基底的封裝材料；及 和基底.中將所述戴體分離出來，以衫 制組件包括用於封骏所述晶片和所述 每個I制組件獨立出來以形❹個積體電路封裝， 至+ ^，封裝包㈣述晶片的至少—個和所述基底的 至個，每個基底包括扇出佈線。 石夕穿t佳地，所述第—半導體晶圓切晶®，所述通孔為 圓獨立之前，測試所述第 ，以確定一套工作基底。 較佳地，所述方法還包括： 在所述將所述第一半導體晶 一半導體晶圓中的所述基底區域 較佳地，所述方法還包括： 一半導體晶圓表面形 在每個所述半導體區域的所述第 成佈線。 較佳地’所述貼包括·· 使用一糸列焊接凸點將每個晶片貼裝在基底上。 較佳地，所述方法還包括： 在所述從所述第一半導體晶圓獨立之前，在所述第一 半導體晶圓的第二表面上形成多個互連凸點； 其中每個積體電路封裝包括所述多個互連凸點的互連 凸點，所述多個互連凸點用於連接所述積體電路封裝和電 路板。 較佳地，每個積體電路封裝表面的一系列導電襯墊用 於將所述積體電路封裝與電路板連接為觸點陣列封裝。 根擄本發明的一個方面，提供一種積體電路封裝，所 6/36 201250872 述積體電路封裝包括： 石々其广有相對的帛和第二表面的硬基底、多個穿過所过、 =底_孔和至少麵述絲細所料—表面的伟 貼裝在所述絲底的所述第—表面的晶片； ㈣封裝物基底的㈣4面上的所述晶片⑽ 較佳地，所述封裝還包括： 述第=接凸點，用於將所述晶片貼到所述雜底的所 較佳地，所述封裝還包括： 夕個互連凸點，其貼在所述石夕基底的所述第二表面。 較佳地，所述封裝還包括： 、十、道^边:夕基底的所述第二表面上的一系列導電襯塾，所 :::用於將所述積體電路封裝和電路板連接為觸: 較佳地，所述通孔為矽穿孔。 車乂也，所述石夕基底包括有源積體 。 【實施方式】 k科 並社含的並形成部分說明書_酬述本發明， 並U財财歧—步_本㈣㈣理，以 域技術人員能夠製造和使用本發明。 〃 項 下面將結合附圖對本發明進行 .W41_ , 相同標號-般表示相同或功能相似在附圖中， =左邊的數位表明該附圖標記首次出現時的那幅附4 7/36 201250872 i、引言 本δ兒明書公開了 一個或多個包含本發明特點的實於 例。公開的實施例僅僅用於舉例說明。本發明的保護範^ 並不限於所公開的實施例。本發明由所附申請專利範 限定。 來 說明書中針對“一個實施例”、“實施例”、“示例實施 例”等的引用，指的是描述的該實施例可包括特定的特徵、 、’-α構或特性，但疋不是每個實施例必須包含這些特定特徵 結構或特性。此外，這樣的表述並非指的是同一個實施例。 進一步，在結合實施例描述特定的特徵、結構或特性時， 不官有沒有明確的描述，已經表明將這樣的特徵、結構或 特性結合到其它實補巾是在本賴技術人貞的知 内的。 岡 ‘此外，應當理解，本發明所使用的空間描述（例如， “在…上面”、“在…下面，，、“向上，，、“左邊’，、“右邊”、“向 下”、“頂部”、“底部”、“垂直”、“水準，，等）僅僅為了說 明的目的。本發明描述的結構的實施例可以以任何方向 方式進行空間設置。 一 π、示例實施例 通常使用可以貼在電路板的封裝將積體電路（ic)晶 片或晶片與其他電路連接。一種這樣類型的1C晶片封裝= 球栅陣列（BGA)封裝。BGA封紐許多其他如今可^得 勺封裝解決方案提供更小的腳印底面積。—種類型的BGA 封裝含有-個或多個貼在封裝基底的第一表面的忙晶片， 並且^有-系列位於封裝基底的第二表面的焊球塾。焊球 、占在桿球塾上。焊球回流以使封裝貼在電路板上。 8/36 201250872 一種先進_的輪縣是㈣級職 級碰封裝在業界有幾個名字，包括 J = 裝（WLCSP)等等。在晶圓級BGA封裝中，當CU 沒有從其㈣f销Μ树料雜崎在icf片還 =樣’晶圓級BGA封裝不包括封裝基底。因此， H封衷的其他Ic封裝類型而言，晶圓級bcu封Ϊ 可以衣造得很小，具有高腳位。 、 例如，圖1所示為傳統的晶圓級積體電路封裝1〇 剖面圖。如圖1所示’封裝⑽包括晶片106、第-電介曾 層102a、第二電介質層職和一系列焊球刚。晶片刚 含有多個晶片106的活性表面上的晶片終端（die terminal)， 該晶片終端是晶片]〇6信號的1/〇概塾（1/〇_)。第一電 介質層102a越過各終端在晶片的表面上形成，而第二 電介質層102b在第-電介質層臟的表面上形成。焊球 1〇4 ^第二電介質層刪的第二表面上形成。在第一和第 二電介質層102a和l〇2b與通孔之間的佈線層中的佈線連 接晶片終端與焊球1〇4,所述通孔穿過第一電介質層l〇2a 和第二電介質層102b。例如，圖i顯示晶片106的終端112 通過佈線層中的跡線110和穿過第二電介質層1〇2b的通孔 114與焊球108連接。 圖1中的封装100使用扇入佈線，因為佈線層的佈線 (例如’跡線110)僅在圖[的晶片106的底面區域内形成。 圖2是傳統的使用扇出佈線的晶圓級積體電路封裝2〇〇的 剖面圖。扇出佈線是一類在半導體晶片區域之外延伸（擴 展到包圍晶片的材料）的佈線。例如，如圖2所示，封裝 2⑻包括晶片106、第一電介質層102a、第二電介質層i〇2b、 9/36 201250872 糸列焊球104和絕緣材料2〇4。絕緣材料2〇4包圍晶片 μ’覆蓋晶片的四周表面和圖2中晶片的頂面，僅僅沒有 覆蓋晶片終端所在的晶片1〇6的活性表面。類似于圖j中 的^裝1〇0，晶片1〇6含有多個晶片1〇6的活性表面上的晶 片終鳊，該晶片終端是晶片106的信號的I/O襯墊。第一電 =質層102a越過終端在晶片1〇6的表面上形成，而第二電 介質層嶋在第-電介質層隐的表面上形成。焊球1〇4 在第二電介質層l〇2b的第二表面上形成。 在第一電介質層l〇2a和第二電介質層1〇21?與通孔之 1的佈線層中的佈線連接晶片終端與焊球，該通孔穿過 第一電介質層lG2a和第二電介質層1G2b。例如，圖2所示 的曰曰片106的終端210通過佈線層中的跡線2〇2和穿過第 二電介質層102b的通孔208與焊球206連接。跡線202是 扇出佈線的-個例子’因為跡線搬通過圍繞晶片1〇6提 供的絕緣材料204在半導體晶片區域之外（在晶片1〇6的 活性表面的區域之外）延伸。這樣’扇出佈線在較晶片106 的區域更大的區域内傳播晶片1〇6的信號，從而為封裝綱 的互聯提供額外m然而，使關出佈線的、形成晶圓 級封裝的傳統技術（如封裝2〇〇)很昂貴，且使用較多的組 裝步驟。 根據本發明的實施例，將活性半導體器件（例如，晶片） 貼在$有通孔的半導體内插器基底（&鄉s咖财e ) 上，且半導體内插器基底用於連接半導體器件和電路板。 内插器基底可以包括多層電路佈線區域，其提供扇出佈線 並與活性半導體器件互連。通過封裝材料（例如，模塑膠 (mo丨ding compound))封裝活性半導體器件和内插器基底。 10/36 201250872 ^種，型的積體電路封裝，包 球柵陣列（BGA)封裝、倒 j CLGA)封裝、 BGA封裝寺，它們都包括活 j曰曰片 基底。例如，互連（例如，J :讀和+導體内播器 表面來形成遍封裝。㈣）可以貼在_器基底的 本發明的實施例克服了傳統的扇出佈線封裝的局限 性。例如，傳統的扇出佈線封裝技 能力，而本發明中呈有則me t早至屬層佈線 ♦ & ΛΙ U内插益基底、使用通孔（如矽穿孔 (TSV))的實施例可以在内插絲底上設置多層佈線層。 例如，圖3所不為根據本發明實施例的積體電路封裝 300的側面剖面圖。如圖3所示，封裝300包括晶片廳: 半導體基底306和封裝材料304。如圖3所示，半導體基底 306含有相對的第一表面312和第二表面314。半導體基底 306含有多個穿過半導體基底306的通孔31〇。此外，半導 體基底306包括至少一層佈線層。佈線層可以包括在晶片 106的區域之外通過基底306延伸的扇出佈線。晶片1〇6貼 裝在半導體基底306的第一表面312上。封裝材料304在 半導體基底306的第一表面312上封裝晶片1〇6。 半導體基底306可以由半導體材料構成，例如矽或鎵 砷化物。例如，半導體基底306可以由半導體晶圓製造， 並從晶圓中獨立出來。半導體基底306可以是有源的 (active)(例如’包含有源積體電路邏輯）、或可以是無源 的（passive)(不包含邏輯）。如圖3所示，半導體基底306 可以包括由半導體材料構成的核心半導體層3〇2b，該核心 半導體層302b的第一表面312上覆蓋有第一絕緣層302a (例如，保護層或阻焊層）、第二表面314上覆蓋有第二絕 11/36 201250872 緣層302c(例如’保護層或阻焊層）。在核心半導體層搬b 具有導電特徵（例如，跡線、通孔墊等）的第-表面312 上形成的第-佈線層可由第—絕緣層施覆蓋、或通過第 一絕緣層302a的開口暴露出來。此外，在核心半導體層 302b 具有導電特性（例如’跡線、通孔㈣）的第二表面314 上形成的第二佈線層可由第二絕緣層3〇2c覆蓋、或通過第 -絕緣層3G2e的暴露出來。當按照標軸半導體製造 /處理技術（例如’使用光刻法等）形成晶圓時，可以在核 心半導體層302b上形成第一絕緣層3Q2a、第二絕緣層3〇2c 和許多佈線層。本發明所描述的佈線層的佈線（例如，跡 線）和其他導電特徵可以由導電材料構成，所述導電材料 例如金屬或金屬/合金混合物，所述金屬包括銅、鋁、錫、 鎳、金、銀、焊錫等。 當形成晶圓時可形成穿過半導體基底3〇6的通孔31〇。 例如，如圖3所示，可以完全穿過核心半導體層3〇2b來形 成通孔310。當半導體基底306是矽基底（例如，由矽晶圓 升>成），通孔310可以稱為石夕穿孔（τ$ν)。 通孔310可以填滿或覆蓋導電材料（例如金屬或金屬/ 合金混合物’所述金屬包括鋼、鋁、錫、鎳、金、銀、焊 錫等）。如圖3所示，通孔310包括通孔316。通孔316包 括在半導體基底306的第一表面312的第一佈線層中形成 的第一通孔墊318、和在半導體基底3〇6的第二表面314的 第二佈線層中形成的第二通孔墊3〇8。通孔316為晶片1〇6 的終端320連通基底306形成電連接。終端32〇是晶片1〇6 的電信號（例如，輸入-輸出信號、電源信號、地面信號、 測試信號等）的接入點（例如，又稱“晶片襯墊”、“ 1/()襯 12/36 201250872 墊”等）。在晶片106的表面上可以有許多終端320,包括 10s、100s和甚至更多數量的終端32〇。 如圖3所示’終端320與通孔墊308 (例如，通過導電 黏合材料）連接。這樣，終端320通過通孔墊318和通孔 316與基底306的第二表面314的通孔墊308電連接。當封 裝300貼裝在電路板時，通孔墊3〇8可以直接或間接地與 電路板的焊盤（landpad)連接，從而將終端320的信號與 電路板的焊盤電連接。另外，晶片1〇6的終端可能以類似 方式與電路板的焊盤電連接。 可能以不同方式形成圖3的封裝300和本發明另外的 封裝實施例。例如，接下來分段描述不使用中間載體來形 成含有半導體基底的積體電路封裝的過程，接著又分段描 述使用巾間紐來形成半導體基底的積體電路封敕的過 程。本發雜供的分段贿對半導體㈣$基底佈線的不 同例子和含有半導體峨器基底的IC封裝的不同例子進行 了描述。應當注意的是’本領域技術人貢在本發明的示教 下可以任何方式組合本發明所描述的實施例。 八·个优用戰體形成封裝的實施例 可能以多種方式形成包括半導體内插器基底的積體電 ，封\例如’圖3中的封裝3GG。例如，圖4所示為根據 士、發明實施_組裝频電路封裝的過程的流程彻。為了 明^的，考圖5-U對流程圖侧進行描述。根據本發 T又吕3(、^田述’其他結構和可使用的實施例對本領域技 何員來說是顯而易見的。流程圖描述如下。 參考流程圖400，名:牛既！ μ。山上 多個半導體基底區域^ 體晶_ -场1Τ穿通第一半導體晶圆形成多個通 13/36 201250872 孔。例如，圖5所示為根據本發明實施例的第一半導體晶 圓500的平面圖。晶圓5〇〇可以是矽晶圓、鎵砷化物晶圓 或其他類型的晶圓。如圖5所示，晶圓5〇〇含有由多個半 導體基底區域（圖5所示的虛線矩形）限定的表面5〇4。每 個半導體基底區域502用於按照流程400的過程各自封裝 成獨立的1C封裝。晶圓500可以包括任一數量的基底區域 502，包括i〇s、i00s、1〇〇〇s和甚至更多。 按照步驟402，在每個區域5〇2中穿通晶圓5〇〇形成多 個通孔。例如，每個區域5〇2可以包括多個類似於圖3所 示的通孔310的通孔。每個通孔可以是圓柱形、可以是如 圖3所示的圓錐形、或者可以是其他形狀。此外，每個通 孔可以填充和/或鍍上導電材料，並含有形成的通孔墊（例 如，類似於圖3中所示的通孔墊318和3〇8)。此外，在晶 圓上形成一個或多個佈線層（和可選絕緣層），從而提供至 穿過晶圓500的導電通孔的導電佈線、和從穿通晶圓5〇〇 的導電通孔至其他導電特徵（例如，晶片終端的導電焊盤、 焊球墊等）的導電佈線。 此外’圖6所示為根據本發明實施例的圖4的流程圖 400中執行的可選步驟6〇2。在步驟602，在第一半導體晶 圓中測試基底區域以確定一套工作基底。在實施例中，在 晶圓500中測試基底區域502以確定工作基底（例如，圖3 的基底306已通過測試）和非工作基底（未通過測試的基 底）。如本領域技術人員所知悉的，在基底區域5〇2上可以 執行各種類型和數量的測試。例如，可以執行功能測試（例 如’通過探測基底區域502的導電特徵來提供測試信號和. 估量測試結果），可以執行環境測試等。 14/36 201250872 在一實施例中，可以對按照步驟602確定為非工作的、 晶圓500中的基底區域502做標記。例如，油墨、鐳射打 標或其他類型的標記都可以應用到非工作的基底區域以標 示它們不可用。用這種方式，可以識別出任何非工作的基 底區域，從而無需對其做進一步處理/使用。 返回參考圖4，在步驟404中，多個從第二半導體晶圓 獨立出來的晶片貼在第一半導體晶圓的表面。例如，圖7 所示為第二半導體晶圓700的平面圖。晶圓7〇〇可以是矽 晶圓、鎵砷化物晶圓或其他類型的晶圓。如圖7所示，晶 圓700含有由多個積體電路區域（圖7所示的小矩形）限 定的表面704。可以按照流程圖4〇〇的過程將一個或多個積 體電路區域702封裝成獨立的IC封裝。晶圓7〇〇可以包括 任一數董的積體電路區域7〇2，包括1〇s、1〇〇s、1〇〇〇s和 甚至更多。 枝“可選地，可通過晶圓減薄（backgrinding)使晶圓7〇〇 二,專例如’如果需要和/或有必要的話，可以在晶圓7〇〇 ^行晶圓減薄處理，從而將晶圓的厚度減小至所需 掛一丄 而要在所有的貫施例中都使晶圓700 "又溽。本領域的技術人員知朵 變薄。晶圓可以盡可二^以任;1方式使晶圓7〇0 J此地溥，從而幫助使產生的、句 括積體電路區域702的封# ώ a 1 曰i ^ 封裝的厚度最小化。此外，可以在 =700中測試每個積體電路區域702。例如，可以在曰圓 =的終端320 (圖7未示出）應用測試探針， =信號和接收測顺_、明__電路區域 15/36 201250872 本領域技術人員知悉，可能以任何恰當的方式將晶圓 700獨立/切成粒，以使積體電路區域相互地物理分開。例 如，可能以傳統的或其他方式，通過鋸、刨槽機、鐳射等 將晶圓700獨立出來。晶圓700的獨立可以形成1〇s、1〇〇s、 1000s、或更多的晶片106 (圖3的），其與晶圓7〇〇的積體 電路區域702的數量相對應。 根據圖4的步驟404，從第二半導體晶圓（如圖7的晶 圓700)獨立出來的一個或多個晶片可以貼裝第一半導體晶 圓500 (圖5所示）白勺表面504上’這樣每個基底區域5〇2 含有至少-個貼在其上的晶片。例如’圖8所示為根據本 發明實施例的具有晶片106的晶圓500表面504的示意圖， 這樣晶片106貼在每個基底區域5〇2上。圖9所示為根據 本發明實施例的晶圓500的一部分的側面剖面圖，所示的 第一晶片106a和第二晶片i〇6b分別貼裝第一基底區域 502a和第二基底區域5〇2b上。晶片1〇6可以以任何方式位 於和/或置於基底區域502上，包括通過使用拾取與放置裝 置（pick-and-placeapparatus)、自對準處理或其他技術。晶 片106的終端可以與基底區域502上的導電焊盤對準，以 使基底區域502的佈線與晶片i〇6的信號連接。例如，焊 錫或其他導電材料（例如，金屬或金屬/合金混合物）可用 於連接終端與導電襯墊。在基底區域502上放置晶片106 之前，在基底區域502的表面和/或晶片106的活性表面可 以使用黏合材料，和/或在粘貼（例如，填充材料）之後可 在晶片106和基底區域502之間插入黏合材料。黏合材料 *T用於幫助將晶片106黏合到基底區域502上。可使用任 16/36 201250872 何合適的黏合材料，—^ & + . 1、 » Λ- I括傳統的晶片材料（die-attach mateml)、環氧樹脂、點性膜等。 I die attach
此外’應當注音的e R 號/晶片襯塾，且包H二片106的終端包括晶片的信 層，將JL稱;^U個在一缝上形成的金屬 個或多個，層， 從而在晶片概_額外^金屬沉積——钱、騎等）’ 管腳㈣或焊球互聯機構之間(例如’ 面上二，在步驟_中，在第—半導體晶圓的表 9所示的^如’ ® 1G所示為根據本發明實施例的圖 圖9所-晶片的晶圓5 〇〇的一部分的側面剖視圖。 圖斤不的具有封裝晶片白勺晶圓500可以稱作“模制元件” 咖圖，示’應用於晶圓表面5〇4的模塑膠臓 曰只域咖的晶片騎和貼在基底區域502b的 Γ起來。模塑勝1002是可用于封裝晶圓500 、曰a 6的縣材料的-個例子。可以任何方式將模 f膠〗應用於晶81 ’包括按照真空模麟理等。例 t只施例中，所製造的模塑位於晶圓(貼有“ 6)表面504，且模塑膠臟可插入到模塑中(例如，以 ，心开M)，並凝固從而封裝晶圓上的晶片觸。本領 7技術人員知悉合適的封裝材料（例如模塑膠），包 香、環氧樹脂等。 返回參考圖4，在步驟稱中，將第一半導體晶圓獨立 ，來，從而分成多健錢域以形❹個積體電路封裝， 體電路封裝包括至少-個晶片。例如，圖u所示為 根據本發明實施例的、從圖1〇中的模制組件勵獨立出 17/36 201250872 來的第一 1C封裝ii〇〇a和第二ic封裝ll〇〇b的示意圖。可 從模制組件獨立出來任一數量的IC封裝1100唭包括1〇s、 loos、或甚至上千個IC封裝1100。如圖丨〗所示，IC封裝 1100a包括貼裝在基底306a的晶片106a和在基底306a上 封裝晶片106a的模塑膠1〇〇2。此外，1C封裝u〇〇b包括 貼裝在基底306b的晶片i〇6b和在基底306b上封裝晶片 106b的模塑膠1002。通過將基底區域5〇2a從晶圓5〇〇中 獨立出來而形成基底306a，通過將基底區域5〇2b從晶圓 5〇〇中獨立出來而形成基底3〇6b。 本領域的技術人員知悉，可以任何恰當的方式將IC封 ^ 11〇〇從模制組件1000獨立出來，以使它們相互地物理 分開。例如，可能以傳統方式或其他方式，通過鋸、刨槽 機、鐳射等來將1C縣聊獨立出來。可以通過切割模 塑膠1002來將圖11的1(：封们驗和1(：封裝丨職從模 制組件100G中獨立出來，以使IC封裝麗a和IC封袭 uoob相互分開，並與其它IC封裝n〇〇 (圖1〇未示 分開。 B、使用載體形成封裝的實施例 可使用載體以各種方式形成包括半導體内插器基 撼，電路ϋ裝’如圖3的封裝。例如，圖12所示為根 發明實施例的組裝積體電路封裝的示例性過程的流程 為了说明的目的，參考圖13-18對流程圖1200進行描 ^根據本發明所提供的描述，其他結構和可使用的實施 •、本領域的技術人員來說是顯而易見的。流程圖12⑻插 18/36 201250872 參考流程圖1200，在步驟1202中，在第一半導體晶圓 的多個半導體基底區域中形成穿過第一半導體晶圓的多個 通孔。例如，如參考圖5所描述的，在每個區域502中形 成穿過晶圓500的多個通孔，其類似於圖3所示的通孔310。 此外’類似於上面提供的描述，可在流程圖12〇〇中執行圖 6所示的可選步驟602，從而測試在晶圓500的基底區域 502 ’以確定一套工作基底。 在步驟1204中，將第一半導體晶圓獨立出來以形成與 多個基底區域相一致的多個基底。例如，參考圖5，本領域 的技術人員知悉’可能以任何恰當的方式將晶圓5〇〇獨立/ 切成粒’以使基底區域502相互地物理分開，從而形成多 個單獨的基底。例如，可能以傳統方式或其他方式，通過 鑛、刨槽機、鐳射等來將晶圓500獨立出來。晶圓500的 獨立可以形成、100s、1000s、或更多的晶片306 (圖3 的）’其與晶圓500的基底區域502的數量相對應。 返回參考圖12，在步驟1206中，將基底貼在載體的表 面上。在一實施例中’將基底（例如上述從晶圓500獨立 出來的基底306)貼在載體表面。在一實施例中，將從晶圓 500獨立出來的、通過測試的一組基底（例如，如上所述的 工作基底）貼在載體上。未通過測試的基底（例如，非工 作基底）則不會貼在載體上。 例如，圖13所示為根據本發明實施例的貼有多個基底 306的、含有平坦表面的载體13〇2的示意圖。基底3〇6可 能以任何方式位於/置於載體13〇2的表面13〇4，包括通過 使用拾取與放置裝置、自對準處理或其他技術。在表面13〇4 上放置基底306之前’在表面13〇4和/或基底306表面可以 19/36 201250872 使用黏合材料’以將基底3G6 _在表面讓上。可使用 任何合適的黏合材料，包括環氧樹脂、黏合膜等。 在圖13的示例中，所示的25個基底3〇6貼在載體13〇2 的表面1304上。然而，在實施例中，可以將任一數量的基 底306貼在載體表面，包括幾十、幾百、或甚至幾千個基 底306。在一個實施例中，基底3〇6可以在載體13〇2的表 面1304上互相田比連（例如，互相接觸）放置。在另一個實 知例中’如圖13所示，基底306可以在載體13〇2的表面 1304上分開放置。在特殊應用中，基底3〇6可能以任何距 離分開放置。 任何合適類型的載體都可以用於接收分離的基底，包 括由陶瓷、玻璃、塑膠、半導體材料（例如矽、鎵砷等）、 金屬或其他材料製成喊體。麵可以具有接收基底3〇6 的平坦表面。這樣的載體可以具有任何外形，包括圓形、 矩形或其他形狀。例如，圖13所示為具有矩形（例如，正 方形）形狀的載體1302。在一個實施例中，載體丨3〇2可以 疋半導體晶圓（例如矽、鎵砷等）’或可以由其他材料如塑 膠、陶瓷、玻璃、金屬等製成。 返回參考圖12，在步驟1208中，從第二半導體晶κ獨 立出來的多個晶片貼在基底上。例如，如上所述，圖7顯 示第二半導體晶圓700的平面圖。可選地，可通過晶片減 薄使晶圓700變薄，並且可在晶圓7〇〇令測試晶圓7〇〇的 母個積體電路區域702。如上所述，可能以任一恰當方式對 晶圓700進行獨立/切成粒，從而使積體電路區域彼此分開 來形成單獨的晶片。 20/36 201250872 圖Η所不為根據纟發明實施例的貼有基底獨的載體 的表面13〇4的示意圖，其中在每個基底摘上都貼有 日曰片106。可祀以任何方式使晶片1〇6位於/置於基底邓6 士 括通過使用拾取與放置褒置、自對準處理或其他技 術、。晶^ 106的終端可以與基底郷上的導電焊盤對準， 、連接as片106的信號與基底3〇6的佈線。例如，焊錫或 其他導電材料（例如，金屬或金屬/合金混合物）可以用於 連接終端與導電襯替。在基底遍上放置晶片應之前， $基底306的表面和/或晶片1〇6的非活性表面可以使用黏 口材料’和/或在點貼（例如，填充材料）之後，在晶片腸 牙，底306之間可插入黏合材料。黏合材料可以用於幫助 將曰曰片106黏合到基底3〇6。可使用任何合適的黏合材料， 包括環氧樹脂、黏合膜等。 例如，圖15所示為根據本發明實施例的載體1302的 一部分的剖面圖。如圖15所示，基底3G6a和基底306b貼 在載體1302的表面13G4上。如圖3所示，每個基底3〇6 含有相對的第一表面312和第二表面314，其中，將第二表 面314貼在載體1302的表面1304上。晶>{ 106貼在基底 3〇6a的第一表面312’以及晶片1〇6b貼在基底如讣的第 一表面312。如本發明所描述，可以使用導電鍍層、管腳或 &點（bumps)將晶片106貼在基底3〇6上’從而作為每個 晶片106和基底306之間的信號互連。此外，如上面所描 述，晶片106的終端包括晶片1〇6的信號墊，以及可包括
一個或多個在晶片襯塾上形成的金屬層，將其稱為UBM 層。 21/36 201250872 此外’應當注意的是，晶片雨的終端包括晶片的信 號/晶片襯墊，且包括一個或多個在晶片襯墊上形成的金屬 層，將其稱為凸點下金屬（UBM)層。UBM層通常是由一 個或多個金屬層形成（金屬沉積--電鐘、_等），從而 在晶片襯墊與額外佈線和/或封裝互聯機構之間（例如，管 腳或焊球）提供魯棒連接。 返回參考圖12，在步驟121〇令，使用封褒材料在载體 上封裝晶片。例如，圖16所示為根據本發明實施例的含有 封裝晶片和基底的載體13〇2的側面剖面圖。如圖16所示， 基底306a和基底306b貼在載體1302的表面1304，以及晶 片106a和晶片306b分別貼在基底306a和基底3〇6b上。 此外模塑膠1602封裝載體1302上的基底306a、基底306b、 晶片106a和晶片i〇6b。模塑膠16〇2是用於封裝載體13〇2 上的基底306a、基底306b、晶片1〇6a和晶片1〇汕的封裝 材料的-個例子。模塑膠膽可能以任何方式應用於載體 1302，包括按照真空模塑處理等。例如，在一實施例中， 所製造的模塑位於載體13们（具有基底和晶片）的表面13〇4 上，且模塑膠1602可插入到模塑（例如，以液態形式）中， 並凝固以封裝載體13〇2上的基底306和晶片1〇6。本領域 技術人員知悉合適的封裝材料，例如包括松香、環氧樹脂 等的模塑膠。 在步驟1212中，從封裝好的晶片和基底中將載體分離 出來，以形成模制元件，該模塑元件包括用於封裝晶片和 基底的封裝材料。例如，圖17所示為根據本發明實施例的、 棱封裝好的基底和晶片中移走/分離出來的載體1302剖面 圖。在圖17中，基底3〇6a和306b、晶片i〇6a和l〇6b以 22/36 201250872
及模歸腿形成從載體13G2分離出來的 基底遞和的底面與模制元件17〇2的表面件 中的底面）齊平或暴露在模制元件咖的表面則 模制元件Π02中通過模塑膠_將晶〇 〇 J 及基底遍和獅封裝起來。載體聰可能以任何^ 從模制元件削2中分離出來。例如，模制元件17Q2 $ 從載體㈣中剝洛下來，可以加熱或冷雜制元件廣 和/或載體13〇2，從而引起或使得載體_從模制元件體 分離出來等。在-實施例中，相比黏附載體ι地，模塑膠 1602對基底306a和306b的黏附更牢固（例如，比^材 料將基底306a和306b黏附到載體13〇2更牢固），二二得 基底306a和3〇6b能與模塑膠職一起從載體13〇 : 離出來，而不是使得基底306a和屬在分 ^ 1302上。 田π料祖 返回參考圖12,在步驟1214中，模制組件從多個積體 電路封裝中獨立出來，每個積體電路封裝包括至少一個晶 片和至少-個基底。例如，圖18所示為根據本發明實施二 的從圖17的模制組件i 700中獨立出來的第一 1(：封裝i驗 和第二1C封裝l_b的示意圖。可以從模塑元件獨立出任 -數量的1C封裝誦，包括1〇s、職、或者甚至幾千個 1C封裝1800。如圖18所示’ IC封裝18〇〇a 底遍的晶片106a、和在基底306a上封裝晶片== ^膠1702。此外’ IC封裝麵b包括貼裝在基底遍的 b曰片106b命在基底3〇6b上封裝晶片i〇6b的模塑膠1702。 本領域的技術人員知悉’可能以任何恰當的方式將IC封裝 1800從模制組件17⑻中獨立出來，以使它們相互地物理^ 23/36 201250872 1，如’可如傳統方式或其他方式，通祕、创槽機、 在田射等來將ic封裝18⑻獨立出來。可以通過切割模塑膠驗 來將圖18的1C封裝丨_和IC封裝誦b從模制組件17〇〇 中獨立出來’以使IC封裝l_a*IC聽18_相互分開， ^…口、匕1C封裝1800 (圖17未示出）分開。在一個實施例 可以直接在基底306的四周邊緣的鄰近進行切割，使 模塑膠1702不會留在IC封裝18〇〇&的基底3〇如和忙封農 1800b的基底306b的四周邊緣（即如圖18所示，基底四周 緣暴露）。可選擇地’可以遠離基底驗和基底鳩的四周 邊緣進行切割’使得—些模_ 留下以覆蓋1C封裝 l_a的基底3G6a和1C封裝聊b的基底3_的四周邊緣 (基底四周邊緣未暴露）。 C、示例性封裝實施例 如上所述，根據本發明實施例，可能以各種方式形成 IC封裝，（例如’ ® 3的封裳300、圖11的封裝11〇〇&和 11〇〇b、以及圖18的封裝⑽加和1800b)。這樣的封裝包 括半導體基底，例如基底鳥，其包括將賴“的信號與 封裝互連連接的通孔和佈線。這樣的通孔和佈線可能以任 何方式構造’包括任―數量的通孔和任—數量的佈線詹。 例如，圖19所示為根據本發明實施例的忙封裝a⑻ 的-部分的側面剖面圖。封裝膽示出了佈線的示例，本 領域的技術人貞知悉，通過本發_示教可能以各種方式 對該佈線騎修改。如圖19所示，封裝觸包括晶片娜、 半導體基底1902、焊接凸點簡、以及互連凸點觸。焊 接凸點是將晶片的終端聊貼在基底膽上。互連凸點 1906是將赫職㈣電路板上（圖19未示⑴。在本實 24/36 201250872 施例中可以有任一數量的焊接凸點1904和/或互連凸點 1906。下面將進一步對封裝1900進行描述。 如圖19所示，在基底1902的表面1938上形成佈線， 以按路線從焊接凸點1904向穿過基底1902的通孔1918傳 遞信號。例如，如圖19所示，基底1902包括核心半導體 層1922 '在第一表面1938的核心半導體層1922上形成的 第一絕緣層1924、在第一絕緣層1924上形成的第一佈線層 1934、以及在佈線層1934上形成的第二絕緣層1926。通孔 1918是完全穿過核心半導體層1922的通孔。通孔1918含 有在核心半導體層1922的第一表面的第一通孔墊1916、以 及在核心半導體層1922的第二表面的第二通孔墊1920。跡 線1912是在佈線層1934中形成的，佈線層1934通過在跡 線1912的第一末端的第一絕緣層1924中的開口連接至通 孔塾1916。跡線1912也可以被稱為重分佈層（re(jistributi〇n layer)或重分佈互連（代出也化此加interconnect)。通過在 跡線1912的第二末端或其附近的第二絕緣層1926的開口 1910、在跡線1912上形成焊盤19〇8。焊接凸點19〇4貼在 焊盤1908上。焊盤19〇8可包括多層導電材料。例如，焊 盤1908可能是UBM層，UBM層通常是由一個或多個金屬 層形成（金屬沉積電鍍、濺射等），以在終端1940與 額外佈線和/或封|互連鶴之間（例如，㈣或焊球）提 供魯棒連接。金屬層可以由不同的金屬和/或合金形成，以 使知包括第-金屬/合金的焊接凸.點19〇4黏附可由不同的 第一金屬/合金製成的跡線1912。 如圖19所示’跡線19]2是由基底1902提供的晶片106 的扇出佈線。這是因為跡線1912越過基底1902在面向基 25/36 201250872 底1902的晶片106的活性表面（晶片106的表面1942)區 域之外延伸》換言之，跡線1912越過基底19〇2的第一表 面1938在晶片和基底19〇2之間的區域之外延伸。這樣， 跡線1912從晶片1〇6扇出，而為了通過相應的跡線按路線 發送晶片106終端的信號，基底1902提供比晶片1〇6區域 更大的表面積，使得封裝1900更加容易地貼裝在電路板上 (使其有較大的焊盤空間）。如圖19所示，在晶片1〇6下 面的焊球1906部分地延伸至晶片106區域之外（至圖19 的右邊）。在另一實施例中，焊球1906可以全部位於晶片 106的區域之外（例如，進一步至圖19的右邊）。 如圖19所示，在基底19〇2的第二表面1940上形成佈 線，從而從通孔1918向焊球1906按路線發送信號。例如， 如圖19所示，基底1902包括在第二表面1940的核心半導 體層1922上形成的第二佈線層1936，以及在佈線層1936 上形成的第三絕緣層1928。佈線層1936包括通孔1918的 通孔墊1920、跡線1932和焊球墊1930。跡線1932連接通 孔墊1920和焊球墊1930。通孔墊1920、跡線1932和焊球 墊1930通過第三絕緣層1928中的開口暴露出來。互連焊 球1906在焊球塾1930上形成。這樣，形成了通過半導體 基底1902的電連接’所述電連接從焊接凸點1904、通過焊 盤1908、跡線1912,通孔墊1916、通孔1918、通孔墊192〇、 跡線1932、焊球墊1930、到達互連焊球19〇6。該電連接使 晶片106終端1940的信號與貼裝有封裝19〇〇的電路板上 的焊盤電連接。可能以類似方式通過基底19〇2形成任一數 量的電連接。 應當注意的是’雖然所示的信號佈線層丨934在基底 26/36 201250872 1902的第一表面i93 的第二表面194〇，但#二的信號佈線層1936在基底1902 1938和1940的政中量的額外佈線層可存在於表面 號按路線發送至焊接:或兩個’從而通過基底驗將信 實施例中，互連，和/或焊球此外’在 和/或焊接凸點19〇4可^直接在通孔塾上形成、 施例中，可存在或可接在通孔塾上形成。在實 腿和/或互連焊球19^形成各雖㈣型的焊接凸點 例如，圖3和圖7 f)，，-, 半導體内姉絲的nr 了轉本發财施例的包括 陣列（LGA)㈣ 封裝述圖3的封裝300是觸點 s 1籍的—個示例。LGA封裝（例如封裝300) ^-類積體電路（IC)的表面貼裝（純啊。福）封裝， 韻體電路（1C)含有一系列用於將封裳貼裝在電路板上 的襯塾。可通過使用插口（磁et)(含有管腳）或通過將 襯墊直接焊至電路缺LGA縣與㈣電路板（PCB)電 連接。 圖20所示為球柵陣列（BGA)縣屬的側面剖面 圖:BGA封裝2000類似於圖3的封裝3〇〇，其具有額外的 一系列焊球2002，焊球2002貼在基底306的第二表面314 的焊球墊上。焊球2002回流以使BGA封裝2〇〇〇貼在電路 板上。當形成晶圓時（例如，流程圖4〇〇的附加步驟的晶 圓500)，或在基底306從晶圓分離出來之後，可以將焊球 2002貼在基底306上。 圖21所示為觸點陣列（LGA)封裝2000的侧面剖面 圖。LGA封裝2100類似於圖3的封裝300的一類LGA封 裝’其具有額外的一系列焊接凸點2104，焊接凸點21〇4貼 27/36 201250872 在晶片106的終端’以將晶Μ 106貼裝在基底306的第一 表面312的焊墊上。圖21的LGA封裝2100可以稱為倒裝 晶片LGA封裝。 圖22所示為球栅陣列（BGA)封裝22()()的側面剖面 圖/。類似于圖20的封裝2_，職封裝22〇具有額外的 一系列焊接凸點21〇4,焊接凸點聰貼在晶片则的炊 端’以將晶片106貼裝在基底306的第一表面312的焊塾 上。圖22的BGA封農謂可以稱為倒裳晶片隐封裝。 在實施例中，可在基底3〇6的第二表面314上形； =連形式簡封裝關電路板上。這樣的互連的示例包 GA封裝的球形互連（例如，焊球2002 )、管腳（例如， 管腳陣列封裝（PGA))、貼或其他類型的互連。這樣^ =何方式應用於基底，包括按照傳統技術和有專 應當注意的是，在實施例中，包含于冗 封裝30G、封裝膽a和、封们咖&则’ 的半導體基底可以是有源的或無源的L =) 基底1902可選地包含有源積體電路邏輯195〇合^的 :二有源積體電路邏輯1950使基底19〇2成為有:以 土底。當其不存在時，基底1902是無源半導體= 可包含任-形式的邏輯(例如’電晶體、；二： 式）’例如用於執行任一邏輯功能的處理 y 可與基底1902巾的通孔和/或佈線連接，從^日輯: 的信號電連接。 -、日日片106 推論 儘管以上對本發明的各個實施例進行 J %述，但應該 28/36 201250872 而:=於示例說明而非限制目 圍的情況下;;=…？背離本發明的精神和範 a„,,^ ^ 了對其形式和細卽作出各種改變。因此，太 定。‘、、、以下所附的申請專利範圍及其等效替換來限 【圖式簡單說明】 圖。圖1和2是示例性傳統的晶圓級積體電路封裝的剖面 圖。圖3是根據本發明實施例的積體電路封裝的側面剖面 圖4是根據本發明實施例的組裝積體 性過程的流程圖。 了我的不例 圖5疋根據本發明實施例的第一半導體晶圓的平面圖。 圖6是根據本發明實施例的測試第一半導體晶圓= 底區域的可選過程的示意圖。 土 圖7是根據本發明實施例的第二半導體晶圓白勺平面圖。 圖8是根據本發明實施綱圖5巾具有貼在晶圓的每 個基底區域的晶片的半導體晶圓的示意圖。 圖9是根據本發明實施例的圖5中半導體晶圓的一部 分的側面剖面圖，其中第一和第二晶片貼裝在各自的基底 區域。 圖10是根據本發明實施例的圖9所示的具有封裝晶片 的晶圓的一部分的側面剖視圖。 圖11是根據本發明實施例的1C封裝從圖1〇中的封裝 晶圓獨立（singulate )出來的示意圖。 29/36 201250872 圖12是根據本發明實施例的使用载體組裝積體電路封 裝的示例性過程的流程圖。 圖13是根據本發明實施例的貼有半導體内插器基底的 載體表面的示意圖。 ° ' 圖Η是根據本發明實施例的圖13中具有貼在半導體 基底上的W的讀务圖^是根據本發明實施例的在載 體上貼有半導體基底的晶片的側面剖面圖。 圖16是根據本發明實施例的圖15中貼裝有半導體美 = 剖視圖，所述载體使用封細: 圖Π是根據本發明實施例的圖16的側面剖視 成賴材料、半導體基底和晶片中分離出來而形 ‘二圖17的模㈣獨立 的^1====❹嶋輪基底 底的咖㈣内插器基 【主要元件符號說明】 100 102a 102b 104 106 106a 晶圓級集成電路封裝 第一電介質層 第*一電介質層 焊球
BQ 片 第一晶 片 30/36 201250872 106b 第二晶片 108 焊球 110 跡線 112 終端 114 通孔 200 晶圓級集成電路封裝 202 跡線 204 絕緣材料 206 焊球 208 通孔 210 終端 300 集成電路封裝 302a 第一絕緣層 302b 核心半導體層 302c 第二絕緣層 304 封裝材料 306 半導體基底 306a-b 基底 308 第二通孔墊 310 通孔 312 第一表面 314 弟—表面 316 通孔 318 通孔墊 320 終端 500 第一半導體晶圓 31/36 201250872 502 基底區域 502a-b 基底區域 504 表面 700 第二半導體晶圓 702 集成電路區域 704 表面 1000 模制組件 1002 模塑料 1100a 第一 1C封裝 1100b 第二1C封裝 1302 載體 1304 表面 1602 模塑料 1700 模制組件 1800a-b 1C封裝 1900 1C封裝 1902 基底 1904 焊接凸點 1906 焊球 1908 通過焊盤 1910 開口 1912 跡線 1918 通孔 1920 通孔墊 1922 核心半導體層 1924 第一絕緣層 32/36 201250872 1926 1928 1930 1932 1934 1936 1938 1940 1942 2000 2002 2100 2104 2200 第二絕緣層 第三絕緣層 焊球墊 跡線 信號佈線層 信號佈線層 第一表面 第二表面 表面 球柵陣列（BGA)封裝 焊球 LGA封裝 焊接凸點 BGA封裝 33/36

Claims (1)

  1. 201250872 七、申請專利範圍： 卜一種積體電路封裝之組裝方法，其特徵在於，所述方法包 括： 在第-半導體晶圓的多個半導體基底區域中形成穿過所 述第一半導體晶圓的多個通孔； 將夕個從第二半導體晶圓獨立出來的晶片貼在所述第一 半導體晶圓的表面； 在所述第一半導體晶圓的所述表面對所述晶片進行封 裝；及 字斤述第半導體晶圓獨立出來以分離多個半導體區 =，以形成多個積體電路封裝，每個積體電路封裝包括至 少一個所述晶片和與基底區域相對應的基底，每個基底包 括扇出佈線。 2、 如申請專利範圍第1項所述的積體電路封裝之組裝方法， 其中所述第一半導體晶圓為矽晶圓，所述通孔為矽穿孔。 3、 如申請專利範圍第1項所述的積體電路封裝的組裝方法， 其中所述方法還包括： 在所述獨立之前，測試所述第一半導體晶圓中的所述基底 區域，以確定一套工作基底。 4、 如申請專利範圍第1項所述的積體電路封裝之組裝方法， 其中所述方法還包括： 在每個所述半導體區域的所述第一半導體晶圓 的表面形 成佈線。 5、 如申請專利範圍第1項所述的積體電路封裝之組裝方法， 其中所述貼包括： 使用一系列焊接凸點將每個晶片貼裝在基底區域。 34/36 201250872 6、如申請專利範圍第1項所述的積體電路封裝之組裝方法， 其中所述方法還包括： 在所述獨立之前，在所述第一半導體晶圓的第二表面上形 成多個互連凸點； 其中每個積體電路封裝包括所述多個互連凸點中的互連 凸點’所述多個互連凸點用於連接所述積體電路封裝和電 路板。 mm 、如申請專利範圍第1項所述的積體電路封裝之組裝方法， 其中母個積體電路封裝表面的一系列導電襯塾用於將所 述積體電路封裝與電路板連接為觸點陣列封裝。 8、一種積體電路封裝之組裝方法，其特徵在於，所述方法包 括： 在弟半導肢日日圓的多個半導體基底區域形成穿過所述 第一半導體晶圓的多個通孔； 將所述第一半導體晶圓獨立出來以形成與所述多個基底 區域相對應的多個基底； 將所述基底貼在載體表面； 將多個從第二半導體晶圓獨立出來的晶片貼到所述基底； 使用封裝材料對所述載體所述基底上的所述晶片進行封 裝； 從封裝好的晶片和基底中將所述載體分離出來，以形成模 制元件’所述模制組件包括用於封裝所述晶片和所述基底 的封裝材料；及 將所述模制組件獨立出來以形成多個積體電路封裝，每個 積體電路封裝包括所述晶片的至少一個和所述基底的至 少一個，每個基底包括扇出佈線。 35/36 201250872 9 10 如申請專利範圍第8項所述的積體電路封裝之 其中所述方法還包括： 在所述將所述第_半導體晶圓獨立之前，職所述第一半 導體晶圓中的所述基底區域，以確定一套工作基底。 一種積體電關裝，其舰在於，所述賴電路^裝包括： 含有相對的第-和第二表面的發基底、多個穿過所述石夕基 底的通孔和至少在所述祕底的所述第—表面的佈線； 貼裝在所述石夕基底的所述第一表面的晶片； 封裝所述矽基底的所述第一表面上的所述晶片的封裝材 料0 36/36
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