TWI804640B - 包括中介層的半導體封裝 - Google Patents

包括中介層的半導體封裝 Download PDF

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TWI804640B
TWI804640B TW108121825A TW108121825A TWI804640B TW I804640 B TWI804640 B TW I804640B TW 108121825 A TW108121825 A TW 108121825A TW 108121825 A TW108121825 A TW 108121825A TW I804640 B TWI804640 B TW I804640B
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semiconductor
interposer
connection
patterns
redistribution structure
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TW108121825A
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TW202008546A (zh
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金鍾潤
李錫賢
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南韓商三星電子股份有限公司
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Publication of TW202008546A publication Critical patent/TW202008546A/zh
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Abstract

本發明概念提供一種包括中介層的半導體封裝。半導體封裝包括：封裝基礎基板；下部重佈線結構，設置於封裝基礎基板上且包括多個下部重佈線圖案；至少一個中介層，包括多個第一連接柱及多個連接配線圖案，所述多個第一連接柱在下部重佈線結構上彼此間隔開且分別連接至所述多個下部重佈線圖案的一些部分；上部重佈線結構，在所述多個第一連接柱及所述至少一個中介層上包括多個上部重佈線圖案，所述多個上部重佈線圖案分別連接至所述多個第一連接柱及所述多個連接配線圖案；以及至少兩個半導體晶片，黏合於上部重佈線結構上，同時彼此間隔開。

Description

包括中介層的半導體封裝
本發明概念是有關於一種包括多個半導體晶片的半導體封裝，且更具體而言，是有關於一種包括用於將所述多個半導體晶片內連至彼此的中介層的半導體封裝。
[相關申請案的交叉參考]
本申請案主張於2018年7月31日在韓國智慧財產局提出申請的韓國專利申請案第10-2018-0089508號的權利，所述韓國專利申請案的全部揭露內容併入本案供參考。
根據電子行業的發展及使用者的需求，電子裝置已進一步微型化、多功能化及/或大容量化，且因此，需要包括多個半導體晶片的半導體封裝。
當半導體封裝中所包括的所述多個半導體晶片中的每一者被高度積體化時，印刷電路板可能無法適應如此高的積體度。對此，已開發了經由中介層對所述多個半導體晶片進行內連的半導體封裝。
本發明概念提供一種包括中介層的半導體封裝，所述半導體封裝可以較低的成本實施。
根據本發明概念的態樣，提供一種半導體封裝，所述半導體封裝包括：下部重佈線結構，包括多個下部絕緣層及分別位於所述多個下部絕緣層的頂表面及底表面中的至少一者上的多個下部重佈線圖案；多個第一連接柱，分別位於所述多個下部重佈線圖案的至少一些部分上；中介層，在所述下部重佈線結構上與所述多個第一連接柱分開，且包括中介層基板、多個連接配線圖案以及多個第二連接柱，所述多個連接配線圖案位於所述中介層基板的頂表面上，所述多個第二連接柱分別位於所述多個連接配線圖案的至少一些部分上；上部重佈線結構，包括至少一個上部絕緣層及多個上部重佈線圖案，所述多個上部重佈線圖案位於所述至少一個上部絕緣層的頂表面或底表面上且分別連接至所述多個第一連接柱及所述多個第二連接柱；以及至少兩個半導體晶片，位於所述上部重佈線結構上，電性連接至所述多個上部重佈線圖案，且彼此分開。
根據本發明概念的另一態樣，提供一種半導體封裝，所述半導體封裝包括：封裝基礎基板；下部重佈線結構，位於所述封裝基礎基板上且包括多個下部重佈線圖案；至少一個中介層，分別包括多個第一連接柱以及多個連接配線圖案，所述多個第一連接柱在所述下部重佈線結構上彼此分開且連接至所述多個下部 重佈線圖案的一些部分；上部重佈線結構，在所述多個第一連接柱及所述至少一個中介層上包括多個上部重佈線圖案，所述多個上部重佈線圖案分別連接至所述多個第一連接柱及所述多個連接配線圖案；以及至少兩個半導體晶片，位於所述上部重佈線結構上，彼此分開，且電性連接至所述多個上部重佈線圖案。
根據本發明概念的另一態樣，提供一種半導體封裝，所述半導體封裝包括：下部重佈線結構，包括多個下部重佈線圖案；中介層，位於所述下部重佈線結構上，所述中介層包括多個第一連接柱、中介層基板、多個連接配線圖案以及多個第二連接柱，所述多個第一連接柱連接至所述多個下部重佈線圖案，所述多個連接配線圖案位於所述中介層基板上，所述多個第二連接柱位於所述多個連接配線圖案上；上部重佈線結構，在所述多個第一連接柱及所述中介層上包括多個上部重佈線圖案，所述多個上部重佈線圖案電性連接至所述多個第一連接柱及所述多個第二連接柱；以及至少兩個半導體晶片，位於所述上部重佈線結構上且電性連接至所述多個上部重佈線圖案，其中所述多個上部重佈線圖案的一部分及所述多個下部重佈線圖案的一部分在水平方向上延伸超過由所述至少兩個半導體晶片佔據的覆蓋區。
1、1a、1b、1c、1d、1e、1f、1g、2、3、4、5:半導體封裝
10:載體基板
20:釋放膜
100:封裝基礎基板
110:基礎板層
122:上部接墊
124:下部接墊
132:頂部阻焊層
134:底部阻焊層
150:外部連接端子
210:下部重佈線結構
212:下部重佈線圖案
214:下部通孔圖案
216:下部絕緣層
220:第一連接柱
225:連接凸塊
230、230a、230b、230c、230d、231:中介層
230b-I、230c-I、230d-I:第一子中介層
230b-II、230c-II、230d-II:第二子中介層
230b-III:第三子中介層
230b-IV:第四子中介層
232:中介層基板
234:連接配線圖案
236:第二連接柱
238、338:貫穿電極
240:晶粒貼合膜
250:填充絕緣材料層
252:填充絕緣層
260:上部重佈線結構
262:上部重佈線圖案
264:上部通孔圖案
266:上部絕緣層
270:板連接構件
280:板底部填充材料層
300、302、305:至少兩個半導體晶片
300a、303、304:多個半導體晶片
310、310a、310c、310d:第一半導體晶片
310b:主半導體晶片
312:第一半導體基板
314:第一晶片接墊
320、320a、320c、320d、330:第二半導體晶片
320b-I:第一子半導體晶片
320b-II:第二子半導體晶片
320b-III:第三子半導體晶片
320b-IV:第四子半導體晶片
322:第二半導體基板
324:第二晶片接墊
330a、330b、330d:切片
330c:第三半導體晶片/切片
332:半導體基板
334:下部晶片接墊
336:上部晶片接墊
370:晶片連接構件
372:切片連接端子
380:底部填充材料層
382:切片黏合層
400:模製構件
400P:初步模製構件
500:熱發射構件
600:被動裝置
H1:第一高度
H2:第二高度
H3:第三高度
LY11:第一下部層
LY12:第二下部層
LY13:第三下部層
LY21:第一上部層
LY22:第二上部層
P1、P2:最小節距
PO:接墊開口
t1、t2:厚度
W1、W2:寬度
結合附圖閱讀以下詳細說明，將更清楚地理解本發明概念的實施例，在附圖中：圖1A是根據實施例的半導體封裝的剖視圖。
圖1B是半導體封裝中的中介層及上部重佈線結構中的每一者的配線的平面佈局圖。
圖2至圖8是根據實施例的半導體封裝的剖視圖。
圖9A至圖9I是根據實施例的用於闡釋製造半導體封裝的方法的剖視圖。
圖10A至圖10G是根據另一實施例的用於闡釋製造半導體封裝的方法的剖視圖。
圖11至圖14是根據實施例的半導體封裝的平面佈局圖。
圖1A是根據實施例的半導體封裝1的剖視圖。
參照圖1A，半導體封裝1包括下部重佈線結構210、中介層230、上部重佈線結構260及/或至少兩個半導體晶片300。中介層230可設置於下部重佈線結構210與上部重佈線結構260之間，且所述至少兩個半導體晶片300可黏合於上部重佈線結構260上。
下部重佈線結構210可包括：多個下部絕緣層216；多個下部重佈線圖案212，分別設置於所述多個下部絕緣層216的頂表面及底表面中的至少一者上；以及多個下部通孔圖案214，穿透所述多個下部絕緣層216中的至少一者中的每一者且接觸所述多個下部重佈線圖案212中的一些下部重佈線圖案212中的每一者。
所述多個下部絕緣層216中的每一者可由例如包含有機化合物的材料層形成。根據實施例，所述多個下部絕緣層216中 的每一者可由包含有機聚合物材料的材料層形成。根據實施例，所述多個下部絕緣層216中的每一者可由感光性聚醯亞胺(photosensitive polyimide，PSPI)形成。
下部重佈線圖案212及下部通孔圖案214中的每一者可包含金屬，例如銅(Cu)、鎢(W)、鈦(Ti)、鈦鎢(TiW)、氮化鈦(TiN)、鉭(Ta)、氮化鉭(TaN)、鉻(Cr)、鋁(Al)、銦(In)、鉬(Mo)、錳(Mn)、鈷(Co)、錫(Sn)、鎳(Ni)、鎂(Mg)、錸(Re)、鈹(Be)、鎵(Ga)、或釕(Ru)、其合金、或金屬氮化物，但並不僅限於此。
下部重佈線圖案212及下部通孔圖案214中的每一者可包括：晶種層，接觸下部絕緣層216；以及導電材料層，位於晶種層上。根據實施例，晶種層可藉由物理氣相沈積形成，且導電材料層可藉由無電鍍覆形成。下部重佈線圖案212的一部分可與下部通孔圖案214的一部分一起成一體地形成。舉例而言，下部重佈線圖案212可與下部通孔圖案214的與下部重佈線圖案212的頂部接觸的一部分成一體地形成，或者與下部通孔圖案214的與下部重佈線圖案212的底部接觸的一部分成一體地形成。
在圖1A中，下部重佈線圖案212僅設置於所述多個下部絕緣層216中的兩個相鄰層之間，但並不僅限於此。根據實施例，下部重佈線圖案212可設置於所述多個下部絕緣層216的最上部層的頂表面及/或最下部層的底表面上。
當下部重佈線圖案212設置於所述多個下部絕緣層216 的頂表面及底表面之中以及兩個相鄰的下部絕緣層216之間時，包括電路配線的位置可被稱為層。下部重佈線結構210可包括多個層，所述多個層包括第一下部層LY11、第二下部層LY12及第三下部層LY13。
多個第一連接柱220及中介層230可黏合於下部重佈線結構210上。所述多個第一連接柱220中的每一者可設置於下部重佈線結構210上，且與中介層230間隔開。
所述多個第一連接柱220可分別設置於所述多個下部重佈線圖案212的一些部分上。第一連接柱220可連接至例如下部重佈線結構210的最上部層，例如，當下部重佈線結構210具有三個層時，連接至設置於第三下部層LY13中的下部重佈線圖案212。第一連接柱220可由例如與下部重佈線圖案212或下部通孔圖案214相同的材料形成。
中介層230可藉由例如晶粒貼合膜240黏合於下部重佈線結構210上。根據實施例，中介層230可黏合於下部重佈線結構210中所包括的所述多個下部絕緣層216的最上部層的頂表面上。
中介層230可包括中介層基板232及設置於中介層基板232的頂表面上的多個連接配線圖案234。
中介層基板232可為半導體基板。舉例而言，中介層基板232可包含矽(Si)。所述多個連接配線圖案234可經由半導體裝置的一般配線製程形成於中介層基板232上。所述多個連接配 線圖案234可包括一個層的連接線配線，但並不僅限於此。根據實施例，所述多個連接配線圖案234可包括至少多個層的連接線配線及對不同層的連接線配線進行內連的通孔插塞。此處，可在連接線配線與通孔插塞之間提供配線間絕緣層。中介層230可藉由僅執行配線製程而形成，而不必在半導體基板上形成單獨的電子裝置。
中介層230可更包括分別設置於所述多個連接配線圖案234的一些部分上的多個第二連接柱236。根據實施例，所述多個第二連接柱236可分別黏合於與所述多個連接配線圖案234的兩端相鄰的一些部分上。
上部重佈線結構260可位於第一連接柱220及中介層230上。上部重佈線結構260可包括：至少一個上部絕緣層266；多個上部重佈線圖案262，設置於所述至少一個上部絕緣層266的頂表面或底面上；及/或多個上部通孔圖案264，分別穿透上部絕緣層266且接觸所述多個上部重佈線圖案262的一些部分。
上部重佈線圖案262、上部通孔圖案264及上部絕緣層266分別與下部重佈線圖案212、下部通孔圖案214及下部絕緣層216相同，且因此不再提供其細節。
上部重佈線結構260可包括多個層，所述多個層包括第一上部層LY21及第二上部層LY22。上部重佈線結構260的層的數目可少於下部重佈線結構210的層的數目。舉例而言，下部重佈線結構210可包括至少三個層，而上部重佈線結構260可包括 少於下部重佈線結構210的層的數目的至少兩個層。
第一連接柱220可內連下部重佈線結構210的下部重佈線圖案212與上部重佈線結構260的上部重佈線圖案262。舉例而言，第一連接柱220可接觸且電性內連下部重佈線結構210的最上部層(例如，設置於第三下部層LY13處的下部重佈線圖案212的頂表面)與上部重佈線結構260的最下部層(例如，設置於第一上部層LY21處的上部重佈線圖案262的底表面)。
第二連接柱236可內連中介層230的連接配線圖案234與上部重佈線結構260的上部重佈線圖案262。舉例而言，第二連接柱236可接觸且電性內連連接配線圖案234的頂表面與上部重佈線結構260的最下部層(例如，設置於第一上部層LY21處的上部重佈線圖案262的底表面)。
在下部重佈線結構210與上部重佈線結構260之間可填充有環繞第一連接柱220及中介層230的填充絕緣層252。填充絕緣層252可包含環氧模製化合物(epoxy molding compound，EMC)或聚合物材料。
下部重佈線結構210的側表面、填充絕緣層252的側表面及上部重佈線結構260的側表面可在垂直方向上彼此對準。
第一連接柱220可具有第一高度H1，且第二連接柱236可具有第二高度H2。第一高度H1可大於第二高度H2。中介層230可具有第三高度H3。第一高度H1可大於第三高度H3。由於中介層230包括第二連接柱236，因此第三高度H3可大於第二高度 H2。
第一連接柱220的最上部部分與第二連接柱236的最上部部分可位於同一水平高度上。由於第一連接柱220的第一高度H1可大於中介層230的第三高度H3，因此第一連接柱220的最下部部分可位於較中介層230的底表面低的水平高度處。
第一連接柱220及第二連接柱236中的每一者均可與暴露於上部重佈線結構260的底表面處的上部重佈線圖案262的底表面接觸。因此，第一連接柱220的最上部部分、第二連接柱236的最上部部分及上部重佈線結構260的底表面可位於同一水平高度處。另外，第一連接柱220的最上部部分、第二連接柱236的最上部部分及填充絕緣層252的頂表面可共面。
第一連接柱220可藉由穿透下部重佈線結構210的下部絕緣層216的一部分而接觸下部重佈線圖案212的頂表面。因此，第一連接柱220的最下部部分可位於較下部重佈線結構210的頂表面低的水平高度處。
所述至少兩個半導體晶片300可黏合於上部重佈線結構260上。所述至少兩個半導體晶片300可包括第一半導體晶片310及第二半導體晶片320。第一半導體晶片310及第二半導體晶片320可在上部重佈線結構260上彼此間隔開。
半導體晶片300中的至少一者可為例如中央處理單元(central processing unit，CPU)晶片、圖形處理單元(graphics processing unit，GPU)晶片或應用處理器(application processor， AP)晶片。半導體晶片300中的至少一者可為例如動態隨機存取記憶體(dynamic random access memory，DRAM)晶片、靜態隨機存取記憶體(static random access memory，SRAM)晶片、快閃記憶體晶片、電性可抹除及可程式化唯讀記憶體(electrically erasable and programmable read-only memory，EEPROM)晶片、相變隨機存取記憶體(phase-change random access memory，PRAM)晶片、磁性隨機存取記憶體(magnetic random access memory，MRAM)晶片或電阻式隨機存取記憶體(resistive random access memory，RRAM)晶片。
根據實施例，第一半導體晶片310可為CPU晶片、GPU晶片、或AP晶片，且第二半導體晶片320可為DRAM晶片、SRAM晶片、快閃記憶體晶片、EEPROM晶片、PRAM晶片、MRAM晶片或RRAM晶片。
第一半導體晶片310包括第一半導體基板312及設置於第一半導體基板312的一個表面上的第一晶片接墊314。第二半導體晶片320包括第二半導體基板322及設置於第二半導體基板322的一個表面上的第二晶片接墊324。
第一半導體晶片310的第一晶片接墊314及第二半導體晶片320的第二晶片接墊324可經由晶片連接構件370連接至上部重佈線結構260的上部重佈線圖案262。晶片連接構件可為例如凸塊、焊料球或導電柱。
第一半導體基板312及第二半導體基板322可包含例如 矽。作為另一種選擇，第一半導體基板312及第二半導體基板322可包含：半導體元素，例如鍺(Ge)；或者化合物半導體，例如碳化矽(SiC)、砷化鎵(GaAs)、砷化銦(InAs)或磷化銦(InP)。第一半導體基板312及第二半導體基板322可各自具有有效表面(active surface)及與有效表面相對的非有效表面(inactive surface)。根據實施例，第一半導體基板312及第二半導體基板322中的每一者的有效表面可面對上部重佈線結構260。
在第一半導體基板312及第二半導體基板322中的每一者的有效表面上可形成有包括各種類型的多個單獨裝置的半導體裝置。
在上部重佈線結構260與第一半導體晶片310及第二半導體晶片320中的每一者之間可填充有環繞晶片連接構件370的底部填充材料層380。底部填充材料層380可包含環氧樹脂，且藉由例如毛細底部填充方法(capillary under-fill method)形成。根據實施例，底部填充材料層380可為非導電膜(non-conductive film，NCF)。
半導體封裝1可為例如扇出型封裝。由所述至少兩個半導體晶片300佔據的覆蓋區可小於上部重佈線結構260及下部重佈線結構210的水平面積。由所述至少兩個半導體晶片300佔據的覆蓋區可在垂直方向上與所有上部重佈線結構260及/或下部重佈線結構210交疊。上部重佈線結構260的上部重佈線圖案262的一部分及下部重佈線結構210的下部重佈線圖案212的一部分 可延伸至自被所述至少兩個半導體晶片300一起佔據的覆蓋區在水平方向上進一步向外突出。
半導體封裝1可更包括板連接構件270，所述板連接構件270黏合於下部重佈線結構210下方。根據實施例，板連接構件270可藉由接墊開口PO而接觸下部重佈線圖案212的底表面，所述接墊開口PO穿透下部重佈線結構210的所述多個下部絕緣層216中的最下部層。板連接構件270可為例如凸塊、焊料球或導電柱。在封裝基礎基板100與下部重佈線結構210之間可填充有環繞板連接構件270的板底部填充材料層280。
根據實施例，半導體封裝1可更包括封裝基礎基板100。封裝基礎基板100可包括基礎板層110以及分別設置於基礎板層110的頂表面及底表面上的上部接墊122及下部接墊124。
根據實施例，封裝基礎基板100可為印刷電路板(printed circuit board，PCB)。舉例而言，封裝基礎基板100可為多層式PCB。基礎板層110可包含選自酚醛樹脂、環氧樹脂及PI中的至少一種材料。基礎板層110可包含選自例如以下材料中的至少一種材料：阻燃劑4(frame retardant 4，FR4)、四官能環氧樹脂、聚苯醚、環氧/聚伸苯醚、雙馬來醯亞胺三嗪(bismaleimide triazine，BT)、聚醯胺短纖席材(Thermount)、氰酸酯、PI及液晶聚合物。
在基礎板層110的頂表面及底表面上可分別形成有頂部阻焊層132及底部阻焊層134，所述頂部阻焊層132及底部阻焊層 134暴露出上部接墊122及下部接墊124。板連接構件270可連接至上部接墊122，且外部連接端子150可連接至下部接墊124。
封裝基礎基板100可包括：配線圖案，電性連接上部接墊122與下部接墊124；以及導通孔，對配線圖案進行電性內連。配線圖案可設置於基礎板層110的頂表面上、底表面上及/或基礎板層110內部。配線圖案可包含例如電解沈積(electrolytically deposited，ED)銅箔、滾軋退火(rolled-annealed，RA)銅箔、不銹鋼箔、鋁箔、超薄銅箔、濺鍍銅或銅合金。
導通孔可穿透基礎板層110的至少一部分。根據實施例，導通孔可包含銅、鎳、不銹鋼或鈹銅合金(BeCu)。
根據實施例，當半導體封裝1不包括封裝基礎基板100時，板連接構件270可執行外部連接端子的功能。
根據實施例，半導體封裝1可更包括熱發射構件500。熱發射構件500可為例如散熱塊(slug)或散熱器(heat sink)。熱發射構件500可接觸封裝基礎基板100的頂表面，且環繞所述至少兩個半導體晶片300，如圖1A中所示，但並不僅限於此。根據實施例，熱發射構件500可接觸所述至少兩個半導體晶片300的頂表面，但是可不接觸封裝基礎基板100的頂表面。根據實施例，可在熱發射構件500與所述至少兩個半導體晶片300的頂表面之間設置熱介面材料(thermal interface material，TIM)。
根據實施例，可在熱發射構件500的外表面上形成電磁干擾(electro-magnetic interference，EMI)屏蔽層。EMI屏蔽層 可電性連接至封裝基礎基板100中所包括的接地層。
圖1B是半導體封裝1中的中介層230的連接配線圖案234及上部重佈線結構260的上部重佈線圖案262的平面佈局圖。圖1B是圖1A的半導體封裝或圖2至圖8的半導體封裝中的每一者中的中介層及上部重佈線結構中的每一者的配線的平面佈局圖。
一起參照圖1A及圖1B，中介層230包括連接配線圖案234及連接至連接配線圖案234的兩端的第二連接柱236。上部重佈線結構260包括內連上部通孔圖案264與第二連接柱236的上部重佈線圖案262。上部通孔圖案264可電性連接至第一半導體晶片310的第一晶片接墊314及第二半導體晶片320的第二晶片接墊324。
上部重佈線圖案262的寬度W1及最小節距P1可分別大於連接配線圖案234的寬度W2及最小節距P2。下部重佈線圖案212的寬度、最小節距及厚度可等於或相似於上部重佈線圖案262的寬度W1、最小節距P1及厚度t1。根據實施例，上部重佈線圖案262的厚度t1可大於連接配線圖案234的厚度t2。
第一半導體晶片310可經由上部重佈線結構260的上部重佈線圖案262及上部通孔圖案264、第一連接柱220、以及下部重佈線結構210的下部重佈線圖案212及下部通孔圖案214電性連接至封裝基礎基板100。第二半導體晶片320可經由上部重佈線結構260的上部重佈線圖案262及上部通孔圖案264、第一連接柱 220以及下部重佈線結構210的下部重佈線圖案212及下部通孔圖案214電性連接至封裝基礎基板100。在半導體封裝1中，第一半導體晶片310與第二半導體晶片320可藉由上部重佈線結構260的上部重佈線圖案262及上部通孔圖案264以及中介層230電性連接至彼此，而不經過(passing through)下部重佈線結構210的下部重佈線圖案212及下部通孔圖案214。
舉例而言，電源訊號、接地訊號、控制訊號、時脈訊號等自板連接構件270至第一半導體晶片310及第二半導體晶片320中的每一者的傳輸、以及板連接構件270與第一半導體晶片310及第二半導體晶片320中的每一者之間的資料傳輸及/或接收可經由下部重佈線結構210的下部重佈線圖案212及下部通孔圖案214、第一連接柱220、以及上部重佈線結構260的上部重佈線圖案及上部通孔圖案264來執行。另一方面，例如，第一半導體晶片310及第二半導體晶片320之間的資料傳輸及/或接收，以及用於第一半導體晶片310與第二半導體晶片320之間的時脈同步的訊號傳輸可僅經由上部重佈線結構260的上部重佈線圖案262及上部通孔圖案264以及中介層230來執行，而不經過下部重佈線結構210的下部重佈線圖案212及下部通孔圖案214。
根據實施例的半導體封裝1經由能夠達成相對精細的節距的中介層230在所述至少兩個半導體晶片300(例如，第一半導體晶片310及第二半導體晶片320)之間傳輸訊號，且經由以相對低成本製造的第一連接柱220及下部重佈線結構210在板連接構 件270與第一半導體晶片310及第二半導體晶片320中的每一者之間傳輸訊號。
舉例而言，由於對於封裝基礎基板與兩個半導體晶片中的每一者之間的訊號以及所述兩個半導體晶片之間的訊號二者均經由中介層傳輸的半導體封裝而言，所述半導體封裝包括相對大的中介層，因此製造成本可能增加。另一方面，由於對於封裝基礎基板與兩個半導體晶片中的每一者之間的訊號以及所述兩個半導體晶片之間的訊號二者均經由重佈線結構傳輸的半導體封裝而言，半導體封裝不能達成精細節距，因此半導體封裝的大小可能增大或者良率可能降低。
然而，由於半導體封裝1經由中介層230在第一半導體晶片310與第二半導體晶片320之間傳輸訊號，且經由第一連接柱220及下部重佈線結構210在封裝基礎基板100與第一半導體晶片310及第二半導體晶片320中的每一者之間傳輸訊號，因此中介層230的所需大小相對小。因此，半導體封裝1可具有低製造成本及高良率。
圖2至圖8是根據實施例的半導體封裝1a至半導體封裝1g的剖視圖。可省略圖2至圖8的與圖1A及圖1B重複的細節，且主要闡述其不同之處。
參照圖2，半導體封裝1a包括下部重佈線結構210、中介層230、上部重佈線結構260及/或所述至少兩個半導體晶片300。中介層230設置於下部重佈線結構210與上部重佈線結構260 之間，且所述至少兩個半導體晶片300可黏合於上部重佈線結構260上。
半導體封裝1a更包括在上部重佈線結構260上環繞所述至少兩個半導體晶片300的模製構件400。模製構件400可由例如EMC形成。模製構件400可環繞上部重佈線結構260的頂表面及所述至少兩個半導體晶片300中的每一者，例如第一半導體晶片310的側表面及第二半導體晶片320的側表面。
模製構件400可暴露出所述至少兩個半導體晶片300的頂表面，例如第一半導體晶片310的頂表面及第二半導體晶片320的頂表面。模製構件400的頂表面及所述至少兩個半導體晶片300的頂表面(例如第一半導體晶片310的頂表面及第二半導體晶片320的頂表面)可共面。
根據實施例，底部填充材料層380可為由模製底部填充膠(molded under-fill，MUF)形成的模製構件400的一部分。熱發射構件500可接觸所述至少兩個半導體晶片300的頂表面及模製構件400的頂表面。下部重佈線結構210的側表面、填充絕緣層252的側表面、上部重佈線結構260的側表面及/或模製構件400的側表面可在垂直方向上對準。
參照圖3，半導體封裝1b包括下部重佈線結構210、中介層231、上部重佈線結構260及所述至少兩個半導體晶片300。中介層231設置於下部重佈線結構210與上部重佈線結構260之間，及/或所述至少兩個半導體晶片300可黏合於上部重佈線結構 260上。
中介層231包括：中介層基板232；連接配線圖案234，設置於中介層基板232的頂表面上；第二連接柱236，設置於連接配線圖案234的一部分上；及/或貫穿電極238，穿透中介層基板232且接觸連接配線圖案234的底表面。
貫穿電極238可電性內連連接配線圖案234與下部重佈線圖案212。根據實施例，可在貫穿電極238與下部重佈線圖案212之間設置穿透晶粒貼合膜240的連接凸塊225。晶粒貼合膜240可為例如非導電膜。
根據實施例，連接凸塊225可以與第一連接柱220相似的方式形成於下部重佈線圖案212上。根據另一實施例，連接凸塊225可在製造中介層231的同時形成於位於中介層231的底表面上的貫穿電極238上。根據另一實施例，連接凸塊225可包括在製造中介層231的同時形成於位於中介層231的底表面上的貫穿電極238上的上部部分、以及以與第一連接柱220相似的方式形成於下部重佈線圖案212上的下部部分。
根據實施例的半導體封裝1b可經由中介層231而不藉由下部重佈線結構210在所述至少兩個半導體晶片300之間(例如，在第一半導體晶片310與第二半導體晶片320之間)傳輸訊號，經由第一連接柱220及下部重佈線結構210而不藉由中介層230在板連接構件270與第一半導體晶片310及第二半導體晶片320中的每一者之間傳輸訊號中的一些訊號、以及一起經由中介層 230及下部重佈線結構210在板連接構件270與第一半導體晶片310及第二半導體晶片320中的每一者之間傳輸訊號中的其餘訊號。
舉例而言，在板連接構件270與第一半導體晶片310及第二半導體晶片320中的每一者之間的訊號中，電源訊號、接地訊號及資料的傳輸及接收可經由下部重佈線結構210來執行，而控制訊號及時脈訊號的傳輸及接收可經由中介層230及下部重佈線結構210一起執行。然而，此僅為實例，且因此不受限制。換言之，可慮及第一連接柱220及貫穿電極238的電性特性及水平橫截面來確定板連接構件270與第一半導體晶片310及第二半導體晶片320中的每一者之間的訊號中的每一訊號的路徑。
參照圖4，半導體封裝1c包括下部重佈線結構210、中介層231、上部重佈線結構260、及/或所述至少兩個半導體晶片300。中介層231可設置於下部重佈線結構210與上部重佈線結構260之間，且所述至少兩個半導體晶片300可黏合於上部重佈線結構260上。半導體封裝1c更包括在上部重佈線結構260上環繞所述至少兩個半導體晶片300的模製構件400。
中介層231包括：中介層基板232；連接配線圖案234，設置於中介層基板232的頂表面上；第二連接柱236，設置於連接配線圖案234的一部分上；以及貫穿電極238，穿透中介層基板232且接觸連接配線圖案234的底表面。
參照圖5，半導體封裝1d包括下部重佈線結構210、中 介層230、上部重佈線結構260、及/或所述至少兩個半導體晶片300。中介層230可設置於下部重佈線結構210與上部重佈線結構260之間，且所述至少兩個半導體晶片300可黏合於上部重佈線結構260上。
半導體封裝1d更包括黏合至下部重佈線結構210的被動裝置600。被動裝置600可為例如晶片電阻器、晶片電容器、電感器、用於產生時脈的石英、或溫度感測器。根據實施例，半導體封裝1d可更包括主動裝置，例如開關、直流(direct current，DC)-DC轉換器、或電壓調節器，所述主動裝置像被動裝置600一樣黏合至下部重佈線結構210。
被動裝置600可設置於下部重佈線結構210上，同時與第一連接柱220及中介層230間隔開。被動裝置600可設置於下部重佈線圖案212的一部分上。被動裝置600可設置於下部重佈線結構210的最上部部分的層上，例如，當下部重佈線結構210包括三個層時，設置於在第三下部層LY13上設置的下部重佈線圖案212上。
填充絕緣層252可在下部重佈線結構210與上部重佈線結構260之間環繞第一連接柱220、中介層230及被動裝置600。
參照圖6，半導體封裝1e包括：下部重佈線結構210；被動裝置600，黏合至下部重佈線結構210；中介層230；上部重佈線結構260；所述至少兩個半導體晶片300；及/或模製構件400，在上部重佈線結構260上環繞所述至少兩個半導體晶片300。中介 層230可設置於下部重佈線結構210與上部重佈線結構260之間，且所述至少兩個半導體晶片300可黏合於上部重佈線結構260上。
參照圖7，半導體封裝1f包括下部重佈線結構210、中介層230、上部重佈線結構260、及/或多個半導體晶片300a。中介層230可設置於下部重佈線結構210與上部重佈線結構260之間，且所述多個半導體晶片300a可黏合於上部重佈線結構260上。
所述多個半導體晶片300a可包括第一半導體晶片310及第二半導體晶片330。第一半導體晶片310可為例如CPU晶片、GPU晶片或AP晶片，且第二半導體晶片330可為高頻寬記憶體(high bandwidth memory，HBM)DRAM晶片。
根據實施例，第二半導體晶片330可為多個記憶體半導體晶片的堆疊，其中根據固態技術協會(JEDEC)標準定義，堆疊表示將記憶體系統中的所有記憶體晶片一起置於一個總成中。換言之，第二半導體晶片330可包括多個切片330a至330d，其中根據JEDEC標準定義，切片(slice)表示記憶體晶片堆疊中的一個記憶體晶片。
根據實施例，在所述多個切片330a至330d中，底部處的切片330a可為包括串列-並行轉換電路的緩衝晶片(buffer slice)，且其餘的切片330b至330d可各自為HBM DRAM半導體晶片。
所述多個切片330a至330d中的每一者包括半導體基板332及設置於半導體基板332的底表面(例如，有效表面)上的下 部晶片接墊334。在所述多個切片330a至330d中，除切片330d之外的切片330a至330c中的每一者可包括貫穿電極338，貫穿電極338電性內連上部晶片接墊336與下部晶片接墊334，所述上部晶片接墊336設置於半導體基板332的頂表面(例如，非有效表面)上。
切片連接端子372及環繞切片連接端子372的切片黏合層382可設置於所述多個切片330a至330d之間，其中切片連接端子372及切片黏合層382在所述多個切片330a至330d之間電性內連頂部切片的下部晶片接墊334與底部切片的上部晶片接墊336。切片連接端子372可為例如凸塊或焊料球。切片黏合層382可為例如非導電膜。
參照圖8，半導體封裝1g包括：下部重佈線結構210；被動裝置600，黏合至下部重佈線結構210；中介層230；上部重佈線結構260；所述多個半導體晶片300a；及/或模製構件400，在上部重佈線結構260上環繞所述多個半導體晶片300a。中介層230可設置於下部重佈線結構210與上部重佈線結構260之間，且所述多個半導體晶片300a可黏合於上部重佈線結構260上。
圖9A至圖9I是根據實施例的用於闡釋製造半導體封裝的方法的剖視圖。舉例而言，圖9A至圖9I是用於闡釋製造圖1A的半導體封裝1的方法的剖視圖。
參照圖9A，在黏合有釋放膜20的載體基板10上形成下部重佈線結構210。下部重佈線結構210可包括：所述多個下部 絕緣層216；下部重佈線圖案212，設置於所述多個下部絕緣層216中的每一者的頂表面或底表面上；及/或下部通孔圖案214，穿透所述多個下部絕緣層216中的每一者。
下部重佈線結構210可藉由依序堆疊所述多個下部絕緣層216中的每一者及下部重佈線圖案212或者下部通孔圖案214及下部重佈線圖案212兩者來形成。
舉例而言，製造下部重佈線結構210的詳細方法如下。首先，形成最下部層的下部絕緣層216，且在最下部層的下部絕緣層216上形成下部重佈線圖案212，下部重佈線圖案212形成最下部部分的層，例如第一下部層LY11。接著，在包括第一下部層LY11的下部重佈線圖案212上形成下部絕緣層216，且形成下部通孔圖案214，下部絕緣層216暴露出包括第一下部層LY11的下部重佈線圖案212的一部分，下部通孔圖案214包括連接至下部重佈線圖案212的第一下部層LY11。此處，下部通孔圖案214與下部重佈線圖案212可成一體地形成。藉由重複此種製程，可形成所述多個下部絕緣層216及包括多個層的下部重佈線結構210，所述多個層包括第一下部層LY11、第二下部層LY12及第三下部層LY13。
根據實施例，下部重佈線結構210的最上部層的下部絕緣層216可被形成為覆蓋最上部部分的層的全部，例如覆蓋包括第三下部層LY13的下部重佈線圖案212。
參照圖9B，在下部重佈線結構210上形成第一連接柱220，所述第一連接柱220連接至下部重佈線結構210的最上部部 分的層(例如，包括第三下部層LY13的下部重佈線圖案212)。
為形成第一連接柱220，在下部重佈線結構210上形成罩幕圖案，所述罩幕圖案用於使欲形成第一連接柱220的位置開口，且藉由使用罩幕圖案作為蝕刻罩幕來移除下部重佈線結構210的最上部層的下部絕緣層216的暴露部分，以暴露出下部重佈線圖案212的形成下部重佈線結構210的最上部部分的層(例如第三下部層LY13)的部分。接著，對暴露的下部重佈線圖案212執行無電鍍覆以形成第一連接柱220。根據實施例，在下部重佈線結構210上形成晶種層之後，可藉由使用晶種層作為晶種執行無電鍍覆來形成導電材料層，且接著可移除罩幕圖案以形成第一連接柱220。
參照圖9C，中介層230黏合於下部重佈線結構210上。中介層230可於下部重佈線結構210上設置成與第一連接柱220間隔開。中介層230可藉由使用例如晶粒貼合膜240黏合於下部重佈線結構210上。中介層230可黏合於下部重佈線結構210中所包括的所述多個下部絕緣層216中的最上部層的頂表面上。
中介層230可包括：中介層基板232；連接配線圖案234，設置於中介層基板232的頂表面上；及/或第二連接柱236，設置於連接配線圖案234的一部分上。中介層基板232的頂表面可位於較第一連接柱220的最上部部分低的水平高度處。
在圖3或圖4的半導體封裝1b或1c中，圖3或圖4的中介層231可代替中介層230黏合於下部重佈線結構210上，其 中中介層231包括：中介層基板232；連接配線圖案234，設置於中介層基板232的頂表面上；第二連接柱236，設置於連接配線圖案234的一部分上；以及貫穿電極238，穿透中介層基板232且接觸連接配線圖案234的底表面。
參照圖9D，在下部重佈線結構210上形成填充絕緣材料層250，所述填充絕緣材料層250覆蓋第一連接柱220及中介層230。填充絕緣材料層250可由環氧模製化合物(EMC)或聚合物材料形成。
在圖5或圖6的半導體封裝1d或1e中，在形成填充絕緣材料層250之前，圖5或圖6的被動裝置600可黏合至下部重佈線結構210，以與第一連接柱220及中介層230間隔開。
參照圖9E，使黏合有圖9D的釋放膜20的載體基板10與下部重佈線結構210分離。接著，移除所述多個下部絕緣層216中最下部層的下部絕緣層216的一部分，以形成接墊開口PO，且藉由接墊開口PO而黏合板連接構件270，所述接墊開口PO暴露出包括第一下部層LY11的下部重佈線圖案212的一部分，所述板連接構件270接觸包括第一下部層LY11的下部重佈線圖案212的底表面。
參照圖9F，移除圖9E的填充絕緣材料層250的上部部分，以使得第一連接柱220及第二連接柱236被暴露出，由此形成填充絕緣層252。填充絕緣層252可覆蓋下部重佈線結構210的頂表面及第一連接柱220的側表面，且覆蓋中介層230的除第 二連接柱236的最上部部分之外的側表面及頂表面。換言之，填充絕緣層252可覆蓋第一連接柱220的側表面及第二連接柱236的側表面，同時暴露出第一連接柱220的頂表面及第二連接柱236頂表面。
第一連接柱220的最上部部分、第二連接柱236的最上部部分及上部重佈線結構260的底表面可位於同一水平高度上。另外，第一連接柱220的最上部部分、第二連接柱236的最上部部分及填充絕緣層252的頂表面可共面。
參照圖9G，上部重佈線結構260形成於填充絕緣層252上。上部重佈線結構260可包括：所述至少一個上部絕緣層266；上部重佈線圖案262，設置於所述至少一個上部絕緣層266的頂表面或底表面上；以及上部通孔圖案264，穿透所述至少一個上部絕緣層266。
上部重佈線結構260可藉由依序堆疊上部重佈線圖案262或者上部通孔圖案264及上部重佈線圖案262兩者以及上部絕緣層266來形成。
舉例而言，製造上部重佈線結構260的詳細方法如下。首先，將上部重佈線圖案262形成為接觸第一連接柱220及第二連接柱236中的每一者，所述上部重佈線圖案262形成上部重佈線結構260的最下部部分的層，例如第一上部層LY21。接著，在包括第一上部層LY21的上部重佈線圖案262上形成上部絕緣層266，且形成上部通孔圖案264，所述上部絕緣層266暴露出包括 第一上部層LY21的上部重佈線圖案262的一部分，所述上部通孔圖案264包括連接至上部重佈線圖案262的第一上部層LY21。此處，上部通孔圖案264與上部重佈線圖案262可成一體地形成。藉由重複此種製程，可形成所述至少一個上部絕緣層266及包括多個層的上部重佈線結構260，所述多個層包括第一上部層LY21及第二上部層LY22。
上部重佈線結構260的層的數目可少於下部重佈線結構210的層的數目。舉例而言，下部重佈線結構210可包括至少三個層，而上部重佈線結構260可包括少於下部重佈線結構210的層的數目的至少兩個層。
參照圖9H，將所述至少兩個半導體晶片300黏合於上部重佈線結構260上。所述至少兩個半導體晶片300可包括第一半導體晶片310及第二半導體晶片320。
可經由晶片連接構件370將第一半導體晶片310的第一晶片接墊314及第二半導體晶片320的第二晶片接墊324各自連接至上部重佈線結構260的上部重佈線圖案262。
可在上部重佈線結構260與第一半導體晶片310及第二半導體晶片320中的每一者之間填充環繞晶片連接構件370的底部填充材料層380。
在圖7的半導體封裝1f中，可將圖7的第二半導體晶片330而非第二半導體晶片320黏合於上部重佈線結構260上。
參照圖9I，製備封裝基礎基板100，所述封裝基礎基板 100包括基礎板層110以及分別設置於基礎板層110的頂表面及底表面上的上部接墊122及下部接墊124，且接著將圖9H的所得製品黏合於封裝基礎基板100上以使得板連接構件270連接至封裝基礎基板100的上部接墊122。
外部連接端子150可黏合至封裝基礎基板100的下部接墊124。
接著，如圖1A中所示，將熱發射構件500設置成接觸所述至少兩個半導體晶片300的頂表面以形成半導體封裝1。根據實施例，半導體封裝1可藉由將熱發射構件500設置成接觸封裝基礎基板100的頂表面且環繞所述至少兩個半導體晶片300而形成。
圖10A至圖10G是根據另一實施例的用於闡釋製造半導體封裝的方法的剖視圖。舉例而言，圖10A至圖10G是用於闡釋製造圖1的半導體封裝1a的方法的剖視圖，其中圖10A示出圖9D之後的製程。
參照圖10A，藉由移除圖9D的填充絕緣材料層250的上部部分以使得第一連接柱220及第二連接柱236被暴露出而形成填充絕緣層252。填充絕緣層252可覆蓋下部重佈線結構210的頂表面及第一連接柱220的側表面，且覆蓋中介層230的除第二連接柱236的最上部部分之外的側表面及頂表面。換言之，填充絕緣層252可覆蓋第一連接柱220及第二連接柱236中的每一者的側表面，同時暴露出第一連接柱220及第二連接柱236中的 每一者的頂表面。
參照圖10B，在填充絕緣層252上形成上部重佈線結構260。上部重佈線結構260可包括：所述至少一個上部絕緣層266；上部重佈線圖案262，設置於所述至少一個上部絕緣層266的頂表面或底表面上；以及上部通孔圖案264，穿透所述至少一個上部絕緣層266。
上部重佈線結構260可藉由依序堆疊上部重佈線圖案262或者上部通孔圖案264及上部重佈線圖案262兩者以及上部絕緣層266來形成。
舉例而言，製造上部重佈線結構260的詳細方法如下。首先，將上部重佈線圖案262形成為接觸第一連接柱220及第二連接柱236中的每一者，所述上部重佈線圖案262形成上部重佈線結構260的最下部部分的層，例如第一上部層LY21。接著，在包括第一上部層LY21的上部重佈線圖案262上形成上部絕緣層266，且形成上部通孔圖案264，所述上部絕緣層266暴露出包括第一上部層LY21的上部重佈線圖案262的一部分，所述上部通孔圖案264包括連接至上部重佈線圖案262的第一上部層LY21。此處，上部通孔圖案264與上部重佈線圖案262可成一體地形成。藉由重複此種製程，可形成所述至少一個上部絕緣層266及包括多個層的上部重佈線結構260，所述多個層包括第一上部層LY21及第二上部層LY22。
上部重佈線結構260的層的數目可少於下部重佈線結構 210的層的數目。舉例而言，下部重佈線結構210可包括至少三個層，而上部重佈線結構260可包括少於下部重佈線結構210的層的數目的至少兩個層。
參照圖10C，將所述至少兩個半導體晶片300黏合於上部重佈線結構260上。所述至少兩個半導體晶片300可包括第一半導體晶片310及第二半導體晶片320。
可經由晶片連接構件370將第一半導體晶片310的第一晶片接墊314及第二半導體晶片320的第二晶片接墊324各自連接至上部重佈線結構260的上部重佈線圖案262。
可將環繞晶片連接構件370的底部填充材料層380填充於上部重佈線結構260與第一半導體晶片310及第二半導體晶片320中的每一者之間。
在圖8的半導體封裝1g中，可將圖8的第二半導體晶片330而非第二半導體晶片320黏合於上部重佈線結構260上。
參照圖10D，形成初步模製構件400P，所述初步模製構件400P在上部重佈線結構260上環繞所述至少兩個半導體晶片300。初步模製構件400P可由例如EMC形成。初步模製構件400P可環繞上部重佈線結構260的頂表面以及所述至少兩個半導體晶片300(例如，第一半導體晶片310及第二半導體晶片320)的側表面及頂表面。
參照圖10E，移除圖10D的初步模製構件400P的上部部分，以使得所述至少兩個半導體晶片300(例如，第一半導體晶 片310及第二半導體晶片320)的頂表面被暴露出，由此形成模製構件400。模製構件400的頂表面及所述至少兩個半導體晶片300(例如，第一半導體晶片310及第二半導體晶片320)的頂表面可共面。模製構件400可環繞上部重佈線結構260的頂表面及所述至少兩個半導體晶片300(例如，第一半導體晶片310及第二半導體晶片320)的側表面。
參照圖10F，使黏合有圖10E的釋放膜20的載體基板10與下部重佈線結構210分離。接著，移除所述多個下部絕緣層216中最下部層的下部絕緣層216的一部分，以形成接墊開口PO，且藉由接墊開口PO而黏合板連接構件270，所述接墊開口PO暴露出包括第一下部層LY11的下部重佈線圖案212的一部分，所述板連接構件270接觸包括第一下部層LY11的下部重佈線圖案212的底表面。
參照圖10G，製備封裝基礎基板100，所述封裝基礎基板100包括基礎板層110以及分別設置於基礎板層110的頂表面及底表面上的上部接墊122及下部接墊124，且接著將圖10F的所得製品黏合於封裝基礎基板100上，以使得板連接構件270連接至封裝基礎基板100的上部接墊122。
可將外部連接端子150黏合至封裝基礎基板100的下部接墊124。
接著，如圖2中所示，將熱發射構件500設置成接觸所述至少兩個半導體晶片300的頂表面以形成半導體封裝1a。根據 實施例，半導體封裝1a可藉由將熱發射構件500設置成接觸封裝基礎基板100的頂表面且環繞所述至少兩個半導體晶片300而形成。
圖11至圖14是根據實施例的半導體封裝2至半導體封裝5的平面佈局圖。圖1A至圖8的半導體封裝1以及半導體封裝1a至半導體封裝1f可為圖11至圖14的半導體封裝2至半導體封裝5中的全部或部分的剖視圖。
參照圖11，半導體封裝2包括：上部重佈線結構260，位於中介層230a上；以及至少兩個半導體晶片302，設置於上部重佈線結構260上且包括第一半導體晶片310a及第二半導體晶片320a。
第一半導體晶片310a及第二半導體晶片320a可設置於上部重佈線結構260上以彼此間隔開。第一半導體晶片310a的一部分及第二半導體晶片320a的一部分可與中介層230a的不同部分交疊。
第一半導體晶片310a與第二半導體晶片320a可經由半導體封裝2中的上部重佈線結構260及中介層230a電性連接至彼此。
舉例而言，第一半導體晶片310a與第二半導體晶片320a之間的資料傳輸及/或接收以及用於第一半導體晶片310a與第二半導體晶片320a之間的時脈同步的訊號傳輸可僅經由上部重佈線結構260及中介層230a執行。
在根據實施例的半導體封裝2中，由於第一半導體晶片310a與第二半導體晶片320a之間的訊號經由上部重佈線結構260及中介層230a傳輸，而另一訊號不經過中介層230a，因此中介層230a的所需大小相對小。因此，半導體封裝2可具有低的製造成本及高的良率。
圖12是根據實施例的半導體封裝3的平面佈局圖。
參照圖12，半導體封裝3包括：上部重佈線結構260，位於多個中介層230b上；以及多個半導體晶片303，設置於上部重佈線結構260上。所述多個半導體晶片303可設置於上部重佈線結構260上，同時彼此間隔開。所述多個半導體晶片303可包括主半導體晶片310b、第一子半導體晶片320b-I、第二子半導體晶片320b-II、第三子半導體晶片320b-III及第四子半導體晶片320b-IV。
所述多個中介層230b可彼此間隔開。所述多個中介層230b可包括第一子中介層230b-I、第二子中介層230b-II、第三子中介層230b-III及第四子中介層230b-IV。
主半導體晶片310b的不同部分可分別與所述多個中介層230b的一些部分交疊。第一子半導體晶片320b-I至第四子半導體晶片320b-IV的一些部分可分別與第一子中介層230b-I至第四子中介層230b-IV的一些部分交疊。
在圖12中，所述多個半導體晶片303包括一個主半導體晶片310b及四個環繞的子半導體晶片(例如，第一子半導體晶 片320b-I至第四子半導體晶片320b-IV)，但作為另一種選擇，所述多個半導體晶片303可包括一個主半導體晶片310b及至少兩個環繞的子半導體晶片。中介層230b的數目可等於或為所述多個半導體晶片303中所包括的子半導體晶片的數目的整數倍。
主半導體晶片310b及第一子半導體晶片320b-I至第四子半導體晶片320b-IV可經由上部重佈線結構260以及第一子中介層230b-I至第四子中介層230b-IV而在半導體封裝3中電性連接至彼此。
在根據實施例的半導體封裝3中，由於主半導體晶片310b與第一子半導體晶片320b-I至第四子半導體晶片320b-IV中的每一者之間的訊號經由上部重佈線結構260及彼此間隔開的第一子中介層230b-I至第四子中介層230b-IV傳輸，而另一訊號不經過所述多個中介層230b，因此所述多個中介層230b的所需大小相對小。因此，半導體封裝3可具有低的製造成本及高的良率。
圖13是根據另一實施例的半導體封裝4的平面佈局圖。
參照圖13，半導體封裝4包括：上部重佈線結構260，位於彼此間隔開的多個中介層230c上；以及多個半導體晶片304，位於上部重佈線結構260上，半導體晶片304包括第一半導體晶片310c至第三半導體晶片330c。所述多個中介層230c可包括第一子中介層230c-I及第二子中介層230c-II。
第一半導體晶片310c至第三半導體晶片330c可設置於上部重佈線結構260上，同時彼此間隔開。第一半導體晶片310c 的一部分及第二半導體晶片320c的一部分可分別與第一子中介層230c-I的不同部分交疊，且第二半導體晶片320c的另一部分及第三半導體晶片330c的一部分可分別與第二子中介層230c-II的不同部分交疊。
在半導體封裝4中，第一半導體晶片310c與第二半導體晶片320c可經由上部重佈線結構260及第一子中介層230c-I電性連接至彼此，且第二半導體晶片320c與第三半導體晶片330c可經由上部重佈線結構260及第二子中介層230c-II電性連接至彼此。
在根據實施例的半導體封裝4中，由於第一半導體晶片310c與第二半導體晶片320c之間的訊號以及第二半導體晶片320c與第三半導體晶片330c之間的訊號經由上部重佈線結構260及彼此間隔開的所述多個中介層230c傳輸，而另一訊號不經過所述多個中介層230c，因此所述多個中介層230c的所需大小相對小。因此，半導體封裝4可具有低的製造成本及高的良率。
圖14是根據另一實施例的半導體封裝5的平面佈局圖。
參照圖14，半導體封裝5包括：上部重佈線結構260，位於彼此間隔開的多個中介層230d上；以及至少兩個半導體晶片305，設置於上部重佈線結構260上且包括第一半導體晶片310d及第二半導體晶片320d。所述多個中介層230d可包括第一子中介層230d-I及第二子中介層230d-II。
第一半導體晶片310d及第二半導體晶片320d可設置於 上部重佈線結構260上，同時彼此間隔開。第一半導體晶片310d的不同部分及第二半導體晶片320d的不同部分可分別與所述多個中介層230d的不同部分交疊。舉例而言，第一半導體晶片310d的所述不同部分可分別與第一子中介層230d-I的一部分及第二子中介層230d-II的一部分交疊，且第二半導體晶片320d的所述不同部分可分別與第一子中介層230d-I的另一部分及第二子中介層230d-II的另一部分交疊。
在半導體封裝5中，第一半導體晶片310d及第二半導體晶片320d可經由上部重佈線結構260及第一子中介層230d-I以及經由上部重佈線結構260及第二子中介層230d-II電性連接至彼此。
在根據實施例的半導體封裝5中，由於第一半導體晶片310d與第二半導體晶片320d之間的訊號經由上部重佈線結構260及所述多個中介層230d傳輸，而另一訊號不經過所述多個中介層230d。另外，由於所述多個中介層230d包括彼此間隔開的第一子中介層230d-I與第二子中介層230d-II，因此所述多個中介層230d的所需大小相對小。另外，由於第一半導體晶片310d與第二半導體晶片320d之間的訊號被分割且經由彼此間隔開的第一子中介層230d-I與第二子中介層230d-II傳輸，因此可增加用於第一半導體晶片310d及第二半導體晶片320d中的每一者的訊號傳輸的晶片接墊(例如，圖1A的第一晶片接墊314及第二晶片接墊324)的設計自由度。因此，半導體封裝5可具有低的製造成本及高的良 率。
儘管已參照本發明概念的實施例具體示出並闡述了本發明概念，然而將理解，在不背離以下申請專利範圍的精神及範圍的條件下可在本文中作出形式及細節上的各種改變。
1‧‧‧半導體封裝
100‧‧‧封裝基礎基板
110‧‧‧基礎板層
122‧‧‧上部接墊
124‧‧‧下部接墊
132‧‧‧頂部阻焊層
134‧‧‧底部阻焊層
150‧‧‧外部連接端子
210‧‧‧下部重佈線結構
212‧‧‧下部重佈線圖案
214‧‧‧下部通孔圖案
216‧‧‧下部絕緣層
220‧‧‧第一連接柱
230‧‧‧中介層
232‧‧‧中介層基板
234‧‧‧連接配線圖案
236‧‧‧第二連接柱
240‧‧‧晶粒貼合膜
252‧‧‧填充絕緣層
260‧‧‧上部重佈線結構
262‧‧‧上部重佈線圖案
264‧‧‧上部通孔圖案
266‧‧‧上部絕緣層
270‧‧‧板連接構件
280‧‧‧板底部填充材料層
300‧‧‧至少兩個半導體晶片
310‧‧‧第一半導體晶片
312‧‧‧第一半導體基板
314‧‧‧第一晶片接墊
320‧‧‧第二半導體晶片
322‧‧‧第二半導體基板
324‧‧‧第二晶片接墊
370‧‧‧晶片連接構件
380‧‧‧底部填充材料層
500‧‧‧熱發射構件
H1‧‧‧第一高度
H2‧‧‧第二高度
H3‧‧‧第三高度
LY11‧‧‧第一下部層
LY12‧‧‧第二下部層
LY13‧‧‧第三下部層
LY21‧‧‧第一上部層
LY22‧‧‧第二上部層
PO‧‧‧接墊開口
t1、t2‧‧‧厚度

Claims (19)

  1. 一種半導體封裝，包括：下部重佈線結構，包括多個下部絕緣層及分別位於所述多個下部絕緣層的頂表面及底表面中的至少一者上的多個下部重佈線圖案；多個第一連接柱，分別位於所述多個下部重佈線圖案的至少一些部分上；中介層，在所述下部重佈線結構上與所述多個第一連接柱分開，且包括中介層基板、多個連接配線圖案以及多個第二連接柱，所述多個連接配線圖案位於所述中介層基板的頂表面上，所述多個第二連接柱分別位於所述多個連接配線圖案的至少一些部分上；上部重佈線結構，包括至少一個上部絕緣層及多個上部重佈線圖案，所述多個上部重佈線圖案位於所述至少一個上部絕緣層的頂表面或底表面上且分別連接至所述多個第一連接柱及所述多個第二連接柱；以及至少兩個半導體晶片，位於所述上部重佈線結構上，電性連接至所述多個上部重佈線圖案，且彼此分開，其中所述多個第一連接柱的最下部部分位於較所述中介層的底表面低的水平高度處。
  2. 如申請專利範圍第1項所述的半導體封裝，其中所述下部重佈線結構及所述上部重佈線結構各自包括包含電路配線的多 個層，所述多個下部重佈線圖案及所述多個上部重佈線圖案位於所述多個層處，其中所述上部重佈線結構中所包括的層的數目少於所述下部重佈線結構中所包括的層的數目。
  3. 如申請專利範圍第1項所述的半導體封裝，其中所述多個第一連接柱的高度大於所述多個第二連接柱的高度。
  4. 如申請專利範圍第1項所述的半導體封裝，其中所述多個第一連接柱的高度大於所述中介層的高度。
  5. 如申請專利範圍第1項所述的半導體封裝，其中所述多個第一連接柱的最上部部分與所述多個第二連接柱的最上部部分處於同一水平高度上。
  6. 如申請專利範圍第1項所述的半導體封裝，更包括填充絕緣層，所述填充絕緣層在所述下部重佈線結構與所述上部重佈線結構之間環繞所述多個第一連接柱及所述中介層。
  7. 如申請專利範圍第6項所述的半導體封裝，其中所述多個第一連接柱的最上部部分、所述多個第二連接柱的最上部部分及所述填充絕緣層的頂表面共面。
  8. 一種半導體封裝，包括：封裝基礎基板；下部重佈線結構，位於所述封裝基礎基板上且包括多個下部重佈線圖案；至少一個中介層，分別包括多個第一連接柱以及多個連接配 線圖案，所述多個第一連接柱在所述下部重佈線結構上彼此分開且連接至所述多個下部重佈線圖案的一些部分；上部重佈線結構，在所述多個第一連接柱及所述至少一個中介層上包括多個上部重佈線圖案，所述多個上部重佈線圖案分別連接至所述多個第一連接柱及所述多個連接配線圖案；以及至少兩個半導體晶片，位於所述上部重佈線結構上，彼此分開，且電性連接至所述多個上部重佈線圖案，其中所述多個第一連接柱的最下部部分位於較所述中介層的底表面低的水平高度處。
  9. 如申請專利範圍第8項所述的半導體封裝，所述半導體封裝被配置成經由所述上部重佈線結構及所述至少一個中介層在所述至少兩個半導體晶片之間傳輸訊號，且所述半導體封裝被配置成經由所述上部重佈線結構、所述多個第一連接柱及所述下部重佈線結構在所述至少兩個半導體晶片與所述封裝基礎基板之間傳輸訊號。
  10. 如申請專利範圍第8項所述的半導體封裝，其中所述多個上部重佈線圖案的最小節距大於所述多個連接配線圖案的最小節距。
  11. 如申請專利範圍第8項所述的半導體封裝，其中所述多個上部重佈線圖案的寬度及厚度大於所述多個連接配線圖案的寬度及厚度。
  12. 如申請專利範圍第8項所述的半導體封裝，其中所述 至少兩個半導體晶片包括主半導體晶片及多個子半導體晶片，其中所述至少一個中介層包括多個子中介層，所述多個子中介層與所述主半導體晶片的一部分及所述多個子半導體晶片中的每一者的一部分交疊，以將所述主半導體晶片電性內連至所述多個子半導體晶片中的每一者。
  13. 如申請專利範圍第8項所述的半導體封裝，其中所述至少兩個半導體晶片包括第一半導體晶片、第二半導體晶片及第三半導體晶片，其中所述至少一個中介層包括第一子中介層以及第二子中介層，所述第一子中介層與所述第一半導體晶片的一部分及所述第二半導體晶片的一部分交疊以將所述第一半導體晶片電性連接至所述第二半導體晶片，所述第二子中介層與所述第二半導體晶片的另一部分及所述第三半導體晶片的一部分交疊以將所述第二半導體晶片電性連接至所述第三半導體晶片。
  14. 如申請專利範圍第8項所述的半導體封裝，更包括熱發射構件，所述熱發射構件接觸所述至少兩個半導體晶片的頂表面。
  15. 如申請專利範圍第14項所述的半導體封裝，其中所述熱發射構件藉由接觸所述封裝基礎基板的頂表面而環繞所述至少兩個半導體晶片。
  16. 如申請專利範圍第8項所述的半導體封裝，其中所述至少兩個半導體晶片包括第一半導體晶片及第二半導體晶片， 其中所述至少一個中介層各自包括第一子中介層以及第二子中介層，所述第一子中介層與所述第一半導體晶片的一部分及所述第二半導體晶片的一部分交疊以將所述第一半導體晶片電性連接至所述第二半導體晶片，所述第二子中介層與所述第一半導體晶片的另一部分及所述第二半導體晶片的另一部分交疊。
  17. 一種半導體封裝，包括：下部重佈線結構，包括多個下部重佈線圖案；中介層，位於所述下部重佈線結構上，所述中介層包括多個第一連接柱、中介層基板、多個連接配線圖案以及多個第二連接柱，所述多個第一連接柱連接至所述多個下部重佈線圖案，所述多個連接配線圖案位於所述中介層基板上，所述多個第二連接柱位於所述多個連接配線圖案上；上部重佈線結構，在所述多個第一連接柱及所述中介層上包括多個上部重佈線圖案，所述多個上部重佈線圖案電性連接至所述多個第一連接柱及所述多個第二連接柱；以及至少兩個半導體晶片，位於所述上部重佈線結構上且電性連接至所述多個上部重佈線圖案，其中所述多個上部重佈線圖案的一部分及所述多個下部重佈線圖案的一部分在水平方向上延伸超過由所述至少兩個半導體晶片佔據的覆蓋區，其中所述多個第一連接柱的最下部部分位於較所述中介層的底表面低的水平高度處。
  18. 如申請專利範圍第17項所述的半導體封裝，更包括被動裝置，所述被動裝置連接至所述下部重佈線結構上的所述多個下部重佈線圖案的一部分。
  19. 如申請專利範圍第17項所述的半導體封裝，其中所述中介層更包括貫穿電極，所述貫穿電極藉由穿透所述中介層基板而將所述多個連接配線圖案內連至所述多個下部重佈線圖案。
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Families Citing this family (42)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20200161206A1 (en) * 2018-11-20 2020-05-21 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and semiconductor manufacturing process
US11217546B2 (en) * 2018-12-14 2022-01-04 Taiwan Semiconductor Manufacturing Company, Ltd. Embedded voltage regulator structure and method forming same
US11189599B2 (en) * 2019-05-30 2021-11-30 Taiwan Semiconductor Manufacturing Company, Ltd. System formed through package-in-package formation
DE102019128274A1 (de) * 2019-05-30 2020-12-03 Taiwan Semiconductor Manufacturing Co., Ltd. Package-in-Package-gebildetes System
US11387177B2 (en) * 2019-06-17 2022-07-12 Taiwan Semiconductor Manufacturing Company Ltd. Package structure and method for forming the same
US11296053B2 (en) 2019-06-26 2022-04-05 Invensas Bonding Technologies, Inc. Direct bonded stack structures for increased reliability and improved yield in microelectronics
US20210005542A1 (en) * 2019-07-03 2021-01-07 Intel Corporation Nested interposer package for ic chips
US11195816B2 (en) * 2019-07-23 2021-12-07 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit packages comprising a plurality of redistribution structures and methods of forming the same
US10868538B1 (en) * 2019-07-29 2020-12-15 Taiwan Semiconductor Manufacturing Company Ltd. Logic cell structure and integrated circuit with the logic cell structure
US20210043573A1 (en) * 2019-08-06 2021-02-11 Intel Corporation Thermal management in integrated circuit packages
US11830787B2 (en) 2019-08-06 2023-11-28 Intel Corporation Thermal management in integrated circuit packages
US11784108B2 (en) * 2019-08-06 2023-10-10 Intel Corporation Thermal management in integrated circuit packages
KR102517379B1 (ko) * 2020-02-14 2023-03-31 삼성전자주식회사 반도체 패키지의 제조 방법
JP2021150567A (ja) 2020-03-23 2021-09-27 キオクシア株式会社 半導体装置及びその製造方法
US11594498B2 (en) 2020-04-27 2023-02-28 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and method
CN111554619A (zh) * 2020-04-30 2020-08-18 通富微电子股份有限公司 一种芯片封装方法
CN111554656A (zh) * 2020-04-30 2020-08-18 通富微电子股份有限公司 一种半导体封装器件
CN111554631A (zh) * 2020-04-30 2020-08-18 通富微电子股份有限公司 一种芯片封装方法
CN111554630A (zh) * 2020-04-30 2020-08-18 通富微电子股份有限公司 一种芯片封装方法
CN111554658A (zh) * 2020-04-30 2020-08-18 通富微电子股份有限公司 一种半导体封装器件
CN111554629A (zh) * 2020-04-30 2020-08-18 通富微电子股份有限公司 一种芯片封装方法
US11355463B2 (en) 2020-05-20 2022-06-07 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and method
DE102020124229A1 (de) 2020-05-20 2021-11-25 Taiwan Semiconductor Manufacturing Co., Ltd. Halbleitervorrichtung und verfahren
US11728254B2 (en) 2020-05-22 2023-08-15 Taiwan Semiconductor Manufacturing Co., Ltd. Giga interposer integration through chip-on-wafer-on-substrate
KR20220007410A (ko) 2020-07-10 2022-01-18 삼성전자주식회사 반도체 패키지
JP7490484B2 (ja) * 2020-07-22 2024-05-27 キオクシア株式会社 半導体装置
CN114068487A (zh) 2020-08-06 2022-02-18 力成科技股份有限公司 封装结构及其制造方法
TWI777633B (zh) * 2020-08-06 2022-09-11 力成科技股份有限公司 封裝結構及其製造方法
KR20220031245A (ko) * 2020-09-04 2022-03-11 에스케이하이닉스 주식회사 적층 반도체 칩을 포함하는 반도체 패키지 및 그 제조 방법
US11764177B2 (en) 2020-09-04 2023-09-19 Adeia Semiconductor Bonding Technologies Inc. Bonded structure with interconnect structure
US11728273B2 (en) 2020-09-04 2023-08-15 Adeia Semiconductor Bonding Technologies Inc. Bonded structure with interconnect structure
US20220102280A1 (en) * 2020-09-25 2022-03-31 Apple Inc. Very Fine Pitch and Wiring Density Organic Side by Side Chiplet Integration
KR20220047066A (ko) 2020-10-08 2022-04-15 삼성전자주식회사 반도체 패키지 장치
KR20220048695A (ko) * 2020-10-13 2022-04-20 삼성전자주식회사 반도체 칩, 적층 반도체 칩 구조체, 및 이를 포함하는 반도체 패키지
US11600562B2 (en) * 2020-10-21 2023-03-07 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages and method of manufacturing the same
US11538759B2 (en) * 2021-01-26 2022-12-27 Deca Technologies Usa, Inc. Fully molded bridge interposer and method of making the same
US11837567B2 (en) 2021-02-26 2023-12-05 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and method of forming thereof
US11855057B2 (en) * 2021-07-08 2023-12-26 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of forming the same
EP4362086A1 (en) * 2021-08-19 2024-05-01 Huawei Technologies Co., Ltd. Chip package structure and electronic apparatus
US11935761B2 (en) 2021-08-27 2024-03-19 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and method of forming thereof
WO2023034738A1 (en) * 2021-09-01 2023-03-09 Adeia Semiconductor Technologies Llc Stacked structure with interposer
JPWO2023042615A1 (zh) * 2021-09-14 2023-03-23

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170062383A1 (en) * 2015-08-31 2017-03-02 Taiwan Semiconductor Manufacturing Company, Ltd. Package Structures and Methods of Making the Same
TW201814856A (zh) * 2016-10-12 2018-04-16 美商美光科技公司 採用成型中介層的晶圓級封裝

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SG119329A1 (en) * 2004-07-29 2006-02-28 Fujikura Ltd Semiconductor device and method for manufacturing the same
US9337120B2 (en) 2012-08-17 2016-05-10 Cisco Technology, Inc. Multi-chip module with multiple interposers
KR101411813B1 (ko) * 2012-11-09 2014-06-27 앰코 테크놀로지 코리아 주식회사 반도체 디바이스 및 그 제조 방법
US20140131854A1 (en) 2012-11-13 2014-05-15 Lsi Corporation Multi-chip module connection by way of bridging blocks
US8901748B2 (en) 2013-03-14 2014-12-02 Intel Corporation Direct external interconnect for embedded interconnect bridge package
US9455162B2 (en) * 2013-03-14 2016-09-27 Invensas Corporation Low cost interposer and method of fabrication
US20150115433A1 (en) 2013-10-25 2015-04-30 Bridge Semiconductor Corporation Semiconducor device and method of manufacturing the same
US9406361B2 (en) 2014-03-27 2016-08-02 Oracle International Corporation Low latency, high bandwidth memory subsystem incorporating die-stacked DRAM
US9704735B2 (en) * 2014-08-19 2017-07-11 Intel Corporation Dual side solder resist layers for coreless packages and packages with an embedded interconnect bridge and their methods of fabrication
JP6378616B2 (ja) * 2014-11-12 2018-08-22 イビデン株式会社 電子部品内蔵プリント配線板
US10515939B2 (en) 2015-02-17 2019-12-24 Mediatek Inc. Wafer-level package having multiple dies arranged in side-by-side fashion and associated yield improvement method
US10074630B2 (en) 2015-04-14 2018-09-11 Amkor Technology, Inc. Semiconductor package with high routing density patch
US9595494B2 (en) * 2015-05-04 2017-03-14 Qualcomm Incorporated Semiconductor package with high density die to die connection and method of making the same
US10008439B2 (en) 2015-07-09 2018-06-26 Avago Technologies General Ip (Singapore) Pte. Ltd. Thin recon interposer package without TSV for fine input/output pitch fan-out
US9368450B1 (en) * 2015-08-21 2016-06-14 Qualcomm Incorporated Integrated device package comprising bridge in litho-etchable layer
US9761533B2 (en) * 2015-10-16 2017-09-12 Xilinx, Inc. Interposer-less stack die interconnect
US10037946B2 (en) * 2016-02-05 2018-07-31 Dyi-chung Hu Package structure having embedded bonding film and manufacturing method thereof
US20170287838A1 (en) 2016-04-02 2017-10-05 Intel Corporation Electrical interconnect bridge
US10276403B2 (en) 2016-06-15 2019-04-30 Avago Technologies International Sales Pe. Limited High density redistribution layer (RDL) interconnect bridge using a reconstituted wafer
US10170428B2 (en) 2016-06-29 2019-01-01 Intel Corporation Cavity generation for embedded interconnect bridges utilizing temporary structures
US10833052B2 (en) * 2016-10-06 2020-11-10 Micron Technology, Inc. Microelectronic package utilizing embedded bridge through-silicon-via interconnect component and related methods
US10763239B2 (en) * 2017-10-27 2020-09-01 Taiwan Semiconductor Manufacturing Co., Ltd. Multi-chip wafer level packages and methods of forming the same

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170062383A1 (en) * 2015-08-31 2017-03-02 Taiwan Semiconductor Manufacturing Company, Ltd. Package Structures and Methods of Making the Same
TW201814856A (zh) * 2016-10-12 2018-04-16 美商美光科技公司 採用成型中介層的晶圓級封裝

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