CN110783309A - 包括内插件的半导体封装件 - Google Patents
包括内插件的半导体封装件 Download PDFInfo
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- CN110783309A CN110783309A CN201910455124.1A CN201910455124A CN110783309A CN 110783309 A CN110783309 A CN 110783309A CN 201910455124 A CN201910455124 A CN 201910455124A CN 110783309 A CN110783309 A CN 110783309A
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Abstract
提供了一种包括内插件的半导体封装件。半导体封装件包括:封装件基底基板;设置在封装件基底基板上并且包括多个下再分布线图案的下再分布线结构;分别位于多个下再分布线图案的至少一部分上的多个第一连接柱状物;位于下再分布线结构上并且彼此间隔开的至少一个内插件,每个内插件包括多个连接布线图案以及分别位于多个连接布线图案的一部分上的彼此间隔开的多个第二连接柱状物;位于至少一个内插件和多个第一连接柱状物上并且包括分别连接到多个第一连接柱状物和多个第二连接柱状物的多个上再分布线图案的上再分布线结构;以及彼此间隔开地附接到上再分布线结构上的至少两个半导体芯片。
Description
相关申请的交叉引用
本申请要求于2018年7月31日在韩国知识产权局提交的韩国专利申请No.10-2018-0089508的权益,其公开内容通过引用整体并入本文。
技术领域
本发明构思涉及包括多个半导体芯片的半导体封装件,更具体地,涉及包括用于将多个半导体芯片彼此互连的内插件(interposer)的半导体封装件。
背景技术
根据电子工业的发展和用户需求的不断提高,电子设备已经进一步小型化、多功能化和/或大容量化,因此,需要包括多个半导体芯片的半导体封装件。
当包括在半导体封装件中的多个半导体芯片中的每一个半导体芯片都被高度集成时,印刷电路板可能无法适应这种高集成度。就这一点而言,已经开发了通过内插件来互连多个半导体芯片的半导体封装件。
发明内容
本发明构思提供了一种半导体封装件,所述半导体封装件包括可以以较低成本实现的内插件。
根据本发明构思的一个方面,提供了一种半导体封装件,所述半导体封装件包括:下再分布线结构,所述下再分布线结构包括多个下绝缘层和分别位于所述多个下绝缘层的顶表面和底表面中的至少一个上的多个下再分布线图案;多个第一连接柱状物,所述多个第一连接柱状物分别位于所述多个下再分布线图案的至少一部分下再分布线图案上;内插件,所述内插件位于所述下再分布线结构上并且与所述多个第一连接柱状物间隔开,并且包括内插基板、位于所述内插基板的顶表面上的多个连接布线图案以及分别位于所述多个连接布线图案的至少一部分连接布线图案上的多个第二连接柱状物;上再分布线结构,所述上再分布线结构包括至少一个上绝缘层和位于所述至少一个上绝缘层的顶表面或底表面上并分别连接到所述多个第一连接柱状物和所述多个第二连接柱状物的多个上再分布线图案;以及至少两个半导体芯片,所述至少两个半导体芯片位于所述上再分布线结构上,所述至少两个半导体芯片彼此间隔开地电连接到所述多个上再分布线图案。
根据本发明构思的另一方面,提供了一种半导体封装件,所述半导体封装件包括:封装件基底基板;下再分布线结构,所述下再分布线结构位于所述封装件基底基板上并且包括多个下再分布线图案;多个第一连接柱状物,所述多个第一连接柱状物分别位于所述多个下再分布线图案中的至少一部分下再分布线图案上;至少一个内插件,所述至少一个内插件位于所述下再分布线结构上并且彼此间隔开,所述至少一个内插件中的每个内插件包括多个连接布线图案以及分别位于所述多个连接布线图案的一部分上的彼此间隔开的多个第二连接柱状物;上再分布线结构,所述上再分布线结构位于所述至少一个内插件和所述多个第一连接柱状物上,并且包括分别连接到所述多个第一连接柱状物和所述多个第二连接柱状物的多个上再分布线图案;以及至少两个半导体芯片,所述至少两个半导体芯片在所述上再分布线结构上彼此间隔开并且电连接到所述多个上再分布线图案。
根据本发明构思的另一方面,提供了一种半导体封装件,包括:下再分布线结构,所述下再分布线结构包括多个下再分布线图案;多个第一连接柱状物,所述多个第一连接柱状物连接到所述多个下再分布线图案;内插件,所述内插件位于所述下再分布线结构上,所述内插件包括内插基板、位于所述内插基板上的多个连接布线图案以及位于所述多个连接布线图案上的多个第二连接柱状物;上再分布线结构,所述上再分布线结构包括位于所述多个第一连接柱状物和所述内插件上并且电连接到所述多个第一连接柱状物和所述多个第二连接柱状物的多个上再分布线图案;以及至少两个半导体芯片,所述至少两个半导体芯片位于所述上再分布线结构上并且电连接到所述多个上再分布线图案,其中,所述多个上再分布线图案的一部分和所述多个下再分布线图案的一部分在水平方向上延伸超过由所述至少两个半导体芯片所占据的覆盖区域。
附图说明
通过以下结合附图的详细描述,将更清楚地理解本发明构思的实施例,其中:
图1A是根据一个实施例的半导体封装件的截面图;
图1B是半导体封装件中的内插件的布线和上部再分布线结构的布线的平面布局;
图2至图8是根据实施例的半导体封装件的截面图;
图9A至图9I是用于说明根据一个实施例的制造半导体封装件的方法的截面图;
图10A至图10G是用于说明根据另一实施例的制造半导体封装件的方法的截面图;以及
图11至图14是根据实施例的半导体封装件的平面布局。
具体实施方式
图1A是根据一个实施例的半导体封装件1的截面图。
参照图1A,半导体封装件1包括下再分布线结构210、内插件230、上再分布线结构260和/或至少两个半导体芯片300。内插件230可以设置在下再分布线结构210与上再分布线结构260之间,至少两个半导体芯片300可以附接在上再分布线结构260上。
下再分布线结构210可以包括多个下绝缘层216、分别设置在多个下绝缘层216的顶表面和底表面中的至少一个上的多个下再分布线图案212以及分别穿透多个下绝缘层216并分别接触多个下再分布线图案212的多个下通路图案214。
多个下绝缘层216中的每一个可以由例如包括有机化合物的材料层形成。根据一个实施例,多个下绝缘层216中的每一个可以由包括有机聚合物材料的材料层形成。根据一个实施例,多个下绝缘层216中的每一个可以由光敏聚酰亚胺(PSPI)形成。
下再分布线图案212和下通路图案214均可以包括诸如铜(Cu)、钨(W)、钛(Ti)、钛钨(TiW)、氮化钛(TiN)、钽(Ta)、氮化钽(TaN)、铬(Cr)、铝(Al)、铟(In)、钼(Mo)、锰(Mn)、钴(Co)、锡(Sn)、镍(Ni)、镁(Mg)、铼(Re)、铍(Be)、镓(Ga)或钌(Ru)的金属、它们的合金或金属氮化物,但不限于此。
下再分布线图案212和下通路图案214均可以包括接触下绝缘层216的晶种层以及位于晶种层上的导电材料层。根据一个实施例,晶种层可以通过物理气相沉积形成,导电材料层可以通过化学镀形成。下再分布线图案212的一部分可以与下通路图案214的一部分一体地形成。例如,下再分布线图案212可以与下通路图案214的与下再分布线图案212的顶部接触的部分一体地形成;或者下再分布线图案212可以与下通路图案214的与下再分布线图案212的底部接触的部分一体地形成。
在图1A中,下再分布线图案212仅设置在多个下绝缘层216中的两个相邻层之间,但不限于此。根据一个实施例,下再分布线图案212还可以设置在多个下绝缘层216中的最上面的下绝缘层216的顶表面上和/或最下面的下绝缘层216的底表面上。
设置在下绝缘层216的顶表面或底表面上的下再分布线图案212可以被称为或者可以构成下再分布线图案层。下再分布线结构210可以具有包括第一下再分布线图案层LY11(在下文中简称为第一下层LY11)、第二下再分布线图案层LY12(在下文中简称为第二下层LY12)和第三下再分布线图案层LY13(在下文中简称为第三下层LY13)在内的多个下再分布线图案层。
多个第一连接柱状物220和内插件230可以附接在下再分布线结构210上。多个第一连接柱状物220中的每一个可以设置在下再分布线结构210上并与内插件230间隔开。
多个第一连接柱状物220可以分别设置在多个下再分布线图案212的多个部分上。第一连接柱状物220可以连接到例如下再分布线结构210的最上面的下再分布线图案层,例如,当下再分布线结构210具有三个下再分布线图案层时,第一连接柱状物220可以连接到第三下层LY13。例如,第一连接柱状物220可以由与下再分布线图案212或下通路图案214相同的材料形成。
内插件230可以通过例如裸片(die)附接膜240附接在下再分布线结构210上。根据一个实施例,内插件230可以附接在包括在下再分布线结构210中的多个下绝缘层216中的最上面的下绝缘层216的顶表面上。
内插件230可以包括内插基板232和设置在内插基板232的顶表面上的多个连接布线图案234。
内插基板232可以是半导体基板。例如,内插基板232可以包括硅(Si)。可以通过半导体器件的普通布线工艺在内插基板232上形成多个连接布线图案234。多个连接布线图案234可以包括一个层的连接线布线,但不限于此。根据一个实施例,多个连接布线图案234可以包括至少一个层的连接线布线以及将不同层的连接线布线互连的通路插塞。这里,可以在连接线布线与通路插塞之间设置布线间绝缘层。可以通过在半导体基板上仅执行布线工艺而不必形成单独的电子器件,来形成内插件230。
内插件230还可以包括分别设置在多个连接布线图案234的多个部分上的多个第二连接柱状物236。根据一个实施例,多个第二连接柱状物236可以分别附接在与多个连接布线图案234的两端相邻的部分上。
上再分布线结构260可以位于第一连接柱状物220和内插件230上。上再分布线结构260可以包括至少一个上绝缘层266、设置在至少一个上绝缘层266的顶表面或底表面上的多个上再分布线图案262、和/或穿透上绝缘层266并分别与多个上再分布线图案262的多个部分接触的多个上通路图案264。
上再分布线图案262、上通路图案264和上绝缘层266分别与下再分布线图案212、下通路图案214和下绝缘层216相同,因此将不再提供它们的细节。
设置在上绝缘层266的顶表面或底表面上的上再分布线图案262可以被称为或者可以构成上再分布线图案层。上再分布线结构260可以具有包括第一上再分布线图案层LY21(在下文中简称为第一上层LY21)和第二上再分布线图案层LY22(在下文中简称为第二上层LY22)在内的多个上再分布线图案层。上再分布线结构260的再分布线图案层的数目可以少于下再分布线结构210的再分布线图案层的数目。例如,下再分布线结构210可以包括至少三个再分布线图案层,而上再分布线结构260可以包括至少两个上再分布线图案层,少于下再分布线结构210的至少三个再分布线图案层。
第一连接柱状物220可以将下再分布线结构210的下再分布线图案212和上再分布线结构260的上再分布线图案262互连。例如,第一连接柱状物220可以接触下再分布线结构210的最上面的下再分布线图案层(例如,第三下层LY13的下再分布线图案212的顶表面)以及上再分布线结构260的最下面的上再分布线图案层(例如,第一上层LY21的上再分布线图案262的底表面)并将它们电互连。
第二连接柱状物236可以将内插件230的连接布线图案234和上再分布线结构260的上再分布线图案262互连。例如,第二连接柱状物236可以接触连接布线图案234的顶表面和上再分布线结构260的最下面的上再分布线图案层(例如,第一上层LY21的上再分布线图案262的底表面)并且将它们电互连。
围绕第一连接柱状物220和内插件230的填充绝缘层252可以填充在下再分布线结构210与上再分布线结构260之间。填充绝缘层252可以包括环氧树脂模制化合物(EMC)或聚合物材料。
下再分布线结构210的侧表面、填充绝缘层252的侧表面和上再分布线结构260的侧表面可以在垂直方向上彼此对齐。
第一连接柱状物220可以具有第一高度H1,第二连接柱状物236可以具有第二高度H2。第一高度H1可以大于第二高度H2。内插件230可以具有第三高度H3。第一高度H1可以大于第三高度H3。由于内插件230包括第二连接柱状物236,所以第三高度H3可以大于第二高度H2。
第一连接柱状物220的最上部分(即,顶表面)和第二连接柱状物236的最上部分可以位于同一水平面。由于第一连接柱状物220的第一高度H1可以大于内插件230的第三高度H3,所以第一连接柱状物220的最下面的部分(即,底表面)可以位于比内插件230的底表面低的水平面。
第一连接柱220状物和第二连接柱状物236均可以与暴露于上再分布线结构260的底表面的上再分布线图案262的底表面接触。因此,第一连接柱状物220的最上部分、第二连接柱状物236的最上部分和上再分布线结构260的底表面可以位于同一水平面。而且,第一连接柱状物220的最上部分、第二连接柱状物236的最上部分和填充绝缘层252的顶表面可以共面。
第一连接柱状物220可以通过穿透下再分布线结构210的下绝缘层216的一部分而与下再分布线图案212的顶表面接触。因此,第一连接柱状物220的最下面的部分可以位于比下再分布线结构210的顶表面低的水平面。
至少两个半导体芯片300可以附接到上再分布线结构260。至少两个半导体芯片300可以包括第一半导体芯片310和第二半导体芯片320。第一半导体芯片310和第二半导体芯片320可以在上再分布线结构260上彼此间隔开。
半导体芯片300中的至少一个可以是例如中央处理单元(CPU)芯片、图形处理单元(GPU)芯片或应用处理器(AP)芯片。半导体芯片300中的至少一个可以是例如动态随机存取存储器(DRAM)芯片、静态随机存取存储器(SRAM)芯片、闪速存储器芯片、电可擦除可编程只读存储器(EEPROM)芯片、相变随机存取存储器(PRAM)芯片、磁随机存取存储器(MRAM)芯片或电阻随机存取存储器(RRAM)芯片。
根据一个实施例,第一半导体芯片310可以是CPU芯片、GPU芯片或AP芯片,第二半导体芯片320可以是DRAM芯片、SRAM芯片、闪速存储器芯片、EEPROM芯片、PRAM芯片、MRAM芯片或RRAM芯片。
第一半导体芯片310包括第一半导体基板312和设置在第一半导体基板312的一个表面上的第一芯片焊盘314。第二半导体芯片320包括第二半导体基板322和设置在第二半导体基板322的一个表面上的第二芯片焊盘324。
第一半导体芯片310的第一芯片焊盘314和第二半导体芯片320的第二芯片焊盘324可以经由芯片连接构件370连接到上再分布线结构260的上再分布线图案262。芯片连接构件可以是例如凸块、焊球或导电柱状物。
第一半导体基板312和第二半导体基板322可以包括例如Si。或者,第一半导体基板312和第二半导体基板322可以包括诸如锗(Ge)的半导体元素或者诸如碳化硅(SiC)、砷化镓(GaAs)、砷化铟(InAs)或磷化铟(InP)的化合物半导体。第一半导体基板312和第二半导体基板322均可以具有有源表面和与有源表面相对的无源表面。根据一个实施例,第一半导体基板312和第二半导体基板322中的每一个的有源表面可以面对上再分布线结构260。
可以在第一半导体基板312和第二半导体基板322中的每一个的有源表面上形成包括多个各种类型的单独器件的半导体器件。
围绕芯片连接构件370的底部填充材料层380可以填充在上再分布线结构260与第一半导体芯片310和第二半导体芯片320中的每一个之间。底部填充材料层380可以包括环氧树脂,并且通过例如毛细管底部填充方法形成。根据一个实施例,底部填充材料层380可以是非导电膜(NCF)。
半导体封装件1可以是例如扇出型封装件。由至少两个半导体芯片300占据的覆盖面积可以小于上再分布线结构260和下再分布线结构210的水平面积。由至少两个半导体芯片300占据的覆盖区域可以在垂直方向上与整个上再分布线结构260和/或整个下再分布线结构210的交叠。上再分布线结构260的上再分布线图案262的一部分和下再分布线结构210的下再分布线图案212的一部分可以延伸以在水平方向上从由至少两个半导体芯片300总共占据的覆盖区域进一步向外突出。
半导体封装件1还可以包括附接在下再分布线结构210下方的板连接构件270。根据一个实施例,板连接构件270可以通过穿透下再分布线结构210的多个下绝缘层216中的最下面的下绝缘层216的焊盘开口PO而与下再分布线图案212的底表面接触。板连接构件270可以是例如凸块、焊球或导电柱状物。围绕板连接构件270的板底部填充材料层280可以填充在封装件基底基板100与下再分布线结构210之间。
根据一个实施例,半导体封装件1还可以包括封装件基底基板100。封装件基底基板100可以包括基底板层110以及分别设置在基底板层110的顶表面和底表面上的上焊盘122和下焊盘124。
根据一个实施例,封装件基底基板100可以是印刷电路板(PCB)。例如,封装件基底基板100可以是多层PCB。基底板层110可以包括选自酚醛树脂、环氧树脂和PI中的至少一种材料。基底板层110可以包括例如选自阻燃剂4(FR4)、四官能环氧树脂、聚苯醚、环氧/聚苯醚、双马来酰亚胺三嗪(bismaleimide triazine,BT)、聚酰胺短纤席材(Thermount)、氰酸酯、PI和液晶聚合物中的至少一种材料。
暴露上焊盘122的顶部阻焊层132和暴露下焊盘124的底部阻焊层134可以分别形成在基底板层110的顶表面和底表面上。板连接构件270可以连接到上焊盘122,外部连接端子150可以连接到下焊盘124。
封装件基底基板100可以包括将上焊盘122和下焊盘124电连接的布线图案以及将布线图案电互连的导电通路。布线图案可以设置在基底板层110的顶表面、底表面和/或内部上。布线图案可以包括例如电解沉积(ED)铜箔、轧制退火(RA)铜箔、不锈钢箔、铝箔、超薄铜箔、溅射铜或铜合金。
导电通路可以穿透基底板层110的至少一部分。根据一个实施例,导电通路可以包括Cu、Ni、不锈钢或BeCu。
根据一个实施例,当半导体封装件1不包括封装件基底基板100时,板连接构件270可以执行外部连接端子的功能。
根据一个实施例,半导体封装件1还可以包括散热构件500。散热构件500可以是例如散热片或散热器。散热构件500可以如图1A所示的那样与封装件基底基板100的顶表面接触并围绕至少两个半导体芯片300,但不限于此。根据一个实施例,散热构件500可以与至少两个半导体芯片300的顶表面接触,但是可以不接触封装件基底基板100的顶表面。根据一个实施例,热界面材料(TIM)可以设置在散热构件500与至少两个半导体芯片300的顶表面之间。
根据一个实施例,电磁界面(EMI)屏蔽层可以形成在散热构件500的外表面上。EMI屏蔽层可以电连接到包括在封装件基底基板100中的接地层。
图1B是半导体封装件1中的内插件230的连接布线图案234和上再分布线结构260的上再分布线图案262的平面布局。图1B是图1A的半导体封装件或图2至图8的每一个半导体封装件中的内插件和上再分布线结构中的每一个的布线的平面布局。
参照图1A和图1B,内插件230包括连接布线图案234和连接到连接布线图案234的两端的第二连接柱状物236。上再分布线结构260包括将上通路图案264和第二连接柱状物236互连的上再分布线图案262。上通路图案264可以电连接到第一半导体芯片310的第一芯片焊盘314和第二半导体芯片320的第二芯片焊盘324。
上再分布线图案262的宽度W1和最小节距P1可以分别大于连接布线图案234的宽度W2和最小节距P2。下再分布线图案212的宽度、最小节距和厚度可以等于或类似于上再分布线图案262的宽度W1、最小节距P1和厚度t1。根据一个实施例,上再分布线图案262的厚度t1可以大于连接布线图案234的厚度t2。
第一半导体芯片310可以经由上再分布线结构260的上再分布线图案262和上通路图案264、第一连接柱状物220以及下再分布线结构210的下再分布线图案212和下通路图案214电连接到封装件基底基板100。第二半导体芯片320可以经由上再分布线结构260的上再分布线图案262和上通路图案264、第一连接柱状物220以及下再分布线结构210的下再分布线图案212和下通路图案214电连接到封装件基底基板100。在半导体封装件1中,第一半导体芯片310和第二半导体芯片320可以通过上再分布线结构260的上再分布线图案262和上通路图案264以及内插件230彼此电连接,而不通过下再分布线结构210的下再分布线图案212和下通路图案214。
例如,从板连接构件270向第一半导体芯片310和第二半导体芯片320中的每一个传输功率信号、接地信号、控制信号、时钟信号等以及板连接构件270与第一半导体芯片310和第二半导体芯片320中的每一个之间的数据发送和/或接收可以经由下再分布线结构210的下再分布线图案212和下通路图案214、第一连接柱状物220以及上再分布线结构260的上再分布线图案和上通路图案264来执行。另一方面,例如,第一半导体芯片310与第二半导体芯片320之间的数据发送和/或接收以及第一半导体芯片310和第二半导体芯片320之间的用于时钟同步的信号传输可以仅经由上再分布线结构260的上再分布线图案262和上通路图案264以及内插件230来执行,而不经过下再分布线结构210的下再分布线图案212和下通路图案214。
根据一个实施例的半导体封装件1经由能够实现相对精细的节距的内插件230在至少两个半导体芯片300(例如,第一半导体芯片310和第二半导体芯片320)之间传输信号,而经由以相对较低成本制造的第一连接柱状物220和下再分布线结构210在板连接构件270与第一半导体芯片310和第二半导体芯片320中的每一个之间传输信号。
例如,由于半导体封装件(在该半导体封装件中,封装件基底基板与两个半导体芯片中的每一个之间的信号以及两个半导体芯片之间的信号都经由内插件传输)包括相对较大的内插件,因此可能会增加制造成本。另一方面,由于半导体封装件(在该半导体封装件中,封装件基底基板与两个半导体芯片中的每一个之间的信号以及两个半导体芯片之间的信号都经由再分布线结构传输)无法实现精细的节距,因此可能会增加半导体封装件的尺寸或降低产量。
然而,由于半导体封装件1经由内插件230在第一半导体芯片310与第二半导体芯片320之间传输信号,经由第一连接柱状物220和下再分布线结构210在封装件基底基板100与第一半导体芯片310和第二半导体芯片320中的每一个之间传输信号,所以内插件230的所需尺寸相对较小。因此,半导体封装件1可以具有低制造成本和高产量。
图2至图8是根据实施例的半导体封装件1a至1g的截面图。可以省略图2至图8中与图1A和图1B重复的细节,而主要描述它们的不同之处。
参照图2,半导体封装件1a包括下再分布线结构210、内插件230、上再分布线结构260和/或至少两个半导体芯片300。内插件230设置在下再分布线结构210与上再分布线结构260之间,至少两个半导体芯片300可以附接在上再分布线结构260上。
半导体封装件1a还包括围绕上再分布线结构260上的至少两个半导体芯片300的模制构件400。模制构件400可以由例如EMC形成。模制构件400可以覆盖上再分布线结构260的顶表面以及至少两个半导体芯片300中的每一个,例如,第一半导体芯片310的侧表面和第二半导体芯片320的侧表面。
模制构件400可以暴露至少两个半导体芯片300的顶表面,例如,第一半导体芯片310的顶表面和第二半导体芯片320的顶表面。模制构件400的顶表面和至少两个半导体芯片300的顶表面(例如,第一半导体芯片310的顶表面和第二半导体芯片320的顶表面)可以共面。
根据一个实施例,底部填充材料层380可以是由模塑底部填充物(molded under-fill,MUF)形成的模制构件400的一部分。散热构件500可以与至少两个半导体芯片300的顶表面和模制构件400的顶表面接触。下再分布线结构210的侧表面、填充绝缘层252的侧表面、上再分布线结构260的侧表面和/或模制构件400的侧表面可以在垂直方向上对齐。
参照图3,半导体封装件1b包括下再分布线结构210、内插件231、上再分布线结构260和至少两个半导体芯片300。内插件231设置在下再分布线结构210与上再分布线结构260之间,和/或至少两个半导体芯片300可以附接在上再分布线结构260上。
内插件231包括内插基板232、设置在内插基板232的顶表面上的连接布线图案234、设置在连接布线图案234的一部分上的第二连接柱状物236和/或穿透内插基板232并接触连接布线图案234的底表面的贯通电极238。
贯通电极238可以将连接布线图案234和下再分布线图案212电互连。根据一个实施例,穿透裸片附接膜240的连接凸块225可以设置在贯通电极238与下再分布线图案212之间。裸片附接膜240可以例如是非导电膜。
根据一个实施例,连接凸块225可以以与第一连接柱状物220类似的方式形成在下再分布线图案212上。根据另一实施例,连接凸块225可以在制造内插件231的同时形成在内插件231的底表面上的贯通电极238上。根据另一实施例,连接凸块225可以包括在制造内插件231的同时形成在内插件231的底表面上的贯通电极238上的上部以及以与第一连接柱状物220类似的方式形成在下再分布线图案212上的下部。
根据一个实施例的半导体封装件1b可以经由内插件231而不通过下再分布线结构210在至少两个半导体芯片300之间(例如,在第一半导体芯片310与第二半导体芯片320之间)传输信号,经由第一连接柱状物220和下再分布线结构210而不通过内插件230在板连接构件270与第一半导体芯片310和第二半导体芯片320中的每一个之间传输一些信号,经由内插件230和下再分布线结构210在板连接构件270与第一半导体芯片310和第二半导体芯片320中的每一个之间传输其余信号。
例如,在板连接构件270与第一半导体芯片310和第二半导体芯片320中的每一个之间的信号当中,可以经由下再分布线结构210来执行电力信号、接地信号和数据的发送和接收,而可以经由内插件230和下再分布线结构210来执行控制信号和时钟信号的发送和接收。然而,这仅仅是示例性的而非限制性的。换句话说,可以考虑第一连接柱状物220和贯通电极238的电特性和水平截面来确定板连接构件270与第一半导体芯片310和第二半导体芯片320中的每一个之间的每个信号的路径。
参照图4,半导体封装件1c包括下再分布线结构210、内插件231、上再分布线结构260和/或至少两个半导体芯片300。内插件231可以设置在下再分布线结构210与上再分布线结构260之间,至少两个半导体芯片300可以附接在上再分布线结构260上。半导体封装件1c还包括围绕上再分布线结构260上的至少两个半导体芯片300的模制构件400。
内插件231包括内插基板232、设置在内插基板232的顶表面上的连接布线图案234、设置在连接布线图案234的一部分上的第二连接柱状物236以及穿透内插基板232并且与连接布线图案234的底表面接触的贯通电极238。
参照图5,半导体封装件1d包括下再分布线结构210、内插件230、上再分布线结构260和/或至少两个半导体芯片300。内插件230可以设置在下再分布线结构210与上再分布线结构260之间,至少两个半导体芯片300可以附接在上再分布线结构260上。
半导体封装件1d还包括附接到下再分布线结构210的无源器件600。无源器件600可以是例如芯片电阻器、芯片电容器、电感器、用于产生时钟的石英或者温度传感器。根据一个实施例,半导体封装件1d还可以包括像无源器件600一样附接到下再分布线结构210的有源器件,例如开关、直流(DC)-DC转换器或电压调节器。
无源器件600可以设置在下再分布线结构210上但与第一连接柱状物220和内插件230间隔开。无源器件600可以设置在下再分布线图案212的一部分上。无源器件600可以设置在下再分布线结构210的最上面的下再分布线图案层上,例如,当下再分布线结构210包括三个下再分布线图案层时,无源器件600可以设置在第三下层LY13的下再分布线图案212上。
填充绝缘层252可以在下再分布线结构210与上再分布线结构260之间围绕第一连接柱状物220、内插件230和无源器件600。
参照图6,半导体封装件1e包括下再分布线结构210、附接到下再分布线结构210的无源器件600、内插件230、上再分布线结构260、至少两个半导体芯片300和/或围绕上再分布线结构260上的至少两个半导体芯片300的模制构件400。内插件230可以设置在下再分布线结构210与上再分布线结构260之间,至少两个半导体芯片300可以附接在上再分布线结构260上。
参照图7,半导体封装件1f包括下再分布线结构210、内插件230、上再分布线结构260和/或多个半导体芯片300a。内插件230可以设置在下再分布线结构210与上再分布线结构260之间,多个半导体芯片300a可以附接在上再分布线结构260上。
多个半导体芯片300a可以包括第一半导体芯片310和第二半导体芯片330。第一半导体芯片310可以是例如CPU芯片、GPU芯片或AP芯片,第二半导体芯片310可以是高带宽存储器(HBM)DRAM芯片。
根据一个实施例,第二半导体芯片320可以是多个存储器半导体芯片的堆叠,其中,根据JEDEC标准定义,堆叠表示在一个组件中采用的存储器系统中的所有存储器芯片。换句话说,第二半导体芯片320可以包括多个切片(slice)330a至330d,其中,根据JEDEC标准定义,切片表示存储器芯片堆叠中的一个存储器芯片。
根据一个实施例,在多个切片330a至330d当中,底部的切片330a可以是包括串并转换电路的缓冲器芯片,其余的切片330b至330d均可以是HBM DRAM半导体芯片。
多个切片330a至330d中的每一个包括半导体基板332和设置在半导体基板332的底表面(例如,有源表面)上的下芯片焊盘334。在多个切片330a至330d中,除切片330d之外的切片330a至330c中的每一个可以包括将设置在半导体基板332的顶表面(例如,非有源表面)上的上芯片焊盘336与下芯片焊盘334电互连的贯通电极338。
切片连接端子372和包围切片连接端子372的切片粘合剂层382可以设置在多个切片330a至330d之间,其中,切片连接端子372和切片粘合剂层382将多个切片330a至330d中的顶部切片的下芯片焊盘334与底部切片的上芯片焊盘336电互连。切片连接端子372可以是例如凸块或焊球。切片粘合剂层382可以是例如非导电膜。
参照图8,半导体封装件1g包括下再分布线结构210、附接到下再分布线结构210的无源器件600、内插件230、上再分布线结构260、多个半导体芯片300a和/或围绕上再分布线结构260上的多个半导体芯片300a的模制构件400。内插件230可以设置在下再分布线结构210与上再分布线结构260之间,多个半导体芯片300a可以附接到上再分布线结构260。
图9A至图9I是用于说明根据一个实施例的制造半导体封装件的方法的截面图。例如,图9A至图9I是用于说明制造图1A的半导体封装件1的方法的截面图。
参照图9A,在附接有离型膜20的载体基板10上形成下再分布线结构210。下再分布线结构210可以包括多个下绝缘层216、设置在多个下绝缘层216中的每一个的顶表面或底表面上的下再分布线图案212、和/或穿透多个下绝缘层216中的每一个的下通路图案214。
可以通过顺序地堆叠多个下绝缘层216中的每一个以及下再分布线图案212(或下通路图案214和下再分布线图案212两者)来形成下再分布线结构210。
例如,制造下再分布线结构210的详细方法如下。首先,形成最下面的下绝缘层216,并且在最下面的下绝缘层216上形成最下面的下再分布线图案212(例如,第一下层LY11的下再分布线图案212)。然后,在第一下层LY11的下再分布线图案212上形成暴露第一下层LY11的下再分布线图案212的一部分的下绝缘层216,并且形成连接到第一下层LY11的下再分布线图案212的下通路图案214。这里,下通路图案214和下再分布线图案212可以一体地形成。通过重复这些过程,可以形成具有多个下绝缘层216和包括第一下层LY11、第二下层LY12和第三下层LY13在内的多个下再分布线图案层的下再分布线结构210。
根据一个实施例,下再分布线结构210的最上面的下绝缘层216可以形成为覆盖整个最上面的下再分布线图案层,例如,第三下层LY13。
参照图9B,在下再分布线结构210上形成连接到下再分布线结构210的最上面的下再分布线图案层(例如,第三下层LY13的下再分布线图案212)的一部分的第一连接柱状物220。
为了形成第一连接柱状物220,在下再分布线结构210上形成用于暴露将要形成第一连接柱状物220的位置的掩模图案,并且通过使用该掩模图案作为蚀刻掩膜来去除下再分布线结构210的最上面的下绝缘层216的暴露部分,从而暴露下再分布线结构210的最上面的下再分布线图案层(例如,第三下层LY13)的下再分布线图案212的一部分。然后,对暴露的下再分布线图案212执行化学镀,以形成第一连接柱状物220。根据一个实施例,在下再分布线结构210上形成晶种层之后,可以通过使用晶种层作为晶种进行化学镀来形成导电材料层,然后可以去除掩模图案以形成第一连接柱状物220。
参照图9C,在下再分布线结构210上附接内插件230。内插件230可以例如与第一连接柱状物220间隔开地设置在下再分布线结构210上。可以通过使用例如裸片附接膜240来将内插件23附接在下再分布线结构210上。内插件230可以附接在下再分布线结构210中所包括的多个下绝缘层216中的最上面的下绝缘层216的顶表面上。
内插件230可以包括内插基板232、设置在内插基板232的顶表面上的连接布线图案234、和/或设置在连接布线图案234的一部分上的第二连接柱状物236。内插基板232的顶表面可以处于低于第一连接柱状物220的最上部分的水平面上。
在图3的半导体封装件1b或图4的半导体封装件1c中,可以在下再分布线结构210上附接图3或图4的内插件231而不是内插件230,其中,内插件231包括内插基板232、设置在内插基板232的顶表面上的连接布线图案234、设置在连接布线图案234的一部分上的第二连接柱状物236以及穿透内插基板232并且与连接布线图案234的底表面接触的贯通电极238。
参照图9D,在下再分布线结构210上形成覆盖第一连接柱状物220和内插件230的填充绝缘材料层250。填充绝缘材料层250可以由环氧树脂模制化合物(EMC)或聚合物材料形成。
在图5半导体封装件1d或图6的半导体封装件1e中,在形成填充绝缘材料层250之前,可以将图5或图6的无源器件600例如与第一连接柱状物220和内插件230间隔开地附接在下再分布线结构210上。
参照图9E,将图9D的附接有离型膜20的载体基板10与下再分布线结构210分离开。然后,去除多个下绝缘层216中的最下面的下绝缘层216的一部分,以形成暴露第一下层LY11的下再分布线图案212的一部分的焊盘开口PO,并且通过焊盘开口PO附接与第一下层LY11的下再分布线图案212的底表面接触的板连接构件270。
参照图9F,去除图9E的填充绝缘材料层250的上部,使得第一连接柱状物220和第二连接柱状物236被暴露,从而形成填充绝缘层252。填充绝缘层252可以覆盖下再分布线结构210的顶表面和第一连接柱状物220的侧表面,并且可以覆盖内插件230的除了第二连接柱状物236的最上部分之外的侧表面和顶表面。换句话说,填充绝缘层252可以覆盖第一连接柱状物220的侧表面和第二连接柱状物236的侧表面,但暴露它们的顶表面。
第一连接柱状物220的最上部分、第二连接柱状物236的最上部分和上再分布线结构260的底表面可以在同一水平面上。而且,第一连接柱状物220的最上部分、第二连接柱状物236的最上部分和填充绝缘层252的顶表面可以共面。
参照图9G,在填充绝缘层252上形成上再分布线结构260。上再分布线结构260可以包括至少一个上绝缘层266、设置在至少一个上绝缘层266的顶表面或底表面上的上再分布线图案262以及穿透至少一个上绝缘层266的上通路图案264。
可以通过顺序地堆叠上再分布线图案262(或上通路图案264和上再分布线图案262)以及上绝缘层266来形成上再分布线结构260。
例如,制造上再分布线结构260的详细方法如下。首先,形成上再分布线结构260的最下面的上再分布线图案层(例如,第一上层LY21)的上再分布线图案262,以接触第一连接柱状物220和第二连接柱状物236中的每一个。然后,在第一上层LY21的上再分布线图案262上形成暴露第一上层LY21的上再分布线图案262的一部分的上绝缘层266,并且形成连接到第一上层LY21的上再分布线图案262的上通路图案264。这里,上通路图案264和上再分布线图案262可以一体地形成。通过重复这些过程,可以形成具有至少一个上绝缘层266和包括第一上层LY21和第二上层LY22在内的多个上再分布线图案层的上再分布线结构260。
上再分布线结构260的层数可以少于下再分布线结构210的层数。例如,下再分布线结构210可以包括至少三个层,而上再分布线结构260可以包括少于下再分布线结构210的层数的至少两个层。
参照图9H,在上再分布线结构260上附接至少两个半导体芯片300。至少两个半导体芯片300可以包括第一半导体芯片310和第二半导体芯片320。
第一半导体芯片310的第一芯片焊盘314和第二半导体芯片320的第二芯片焊盘324可以各自经由芯片连接构件370连接到上再分布线结构260的上再分布线图案262。
可以在上再分布线结构260与第一半导体芯片310和第二半导体芯片320中的每一个之间填充围绕芯片连接构件370的底部填充材料层380。
在图7的半导体封装件1f中,可以在上再分布线结构260上附接图7的第二半导体芯片330而不是第二半导体芯片320。
参照图9I,制备包括基底板层110和分别设置在基底板层110的顶表面和底表面上的上焊盘122和下焊盘124的封装件基底基板100,然后在封装件基底基板100上附接图9H的所得产品,使得板连接构件270连接到封装件基底基板100的上焊盘122。
外部连接端子150可以附接到封装件基底基板100的下焊盘124。
然后,如图1A所示,设置散热构件500以接触至少两个半导体芯片300的顶表面从而形成半导体封装件1。根据一个实施例,可以通过设置散热构件500以接触封装件基底基板100的顶表面并围绕至少两个半导体芯片300来形成半导体封装件1。
图10A至图10G是用于说明根据另一实施例的制造半导体封装件的方法的截面图。例如,图10A至图10G是用于说明制造图2的半导体封装件1a的方法的截面图,其中,图10A示出了图9D之后的过程。
参照图10A,通过去除图9D的填充绝缘材料层250的上部来形成填充绝缘层252,从而暴露第一连接柱状物220和第二连接柱状物236。填充绝缘层252可以覆盖下再分布线结构210的顶表面和第一连接柱状物220的侧表面,并且覆盖内插件230的除了第二连接柱状物236的最上部分之外的侧表面和顶表面。换句话说,填充绝缘层252可以覆盖第一连接柱状物220和第二连接柱状物236中的每一个的侧表面,但暴露它们的顶表面。
参照图10B,在填充绝缘层252上形成上再分布线结构260。上再分布线结构260可以包括至少一个上绝缘层266、设置在至少一个上绝缘层266的顶表面或底表面上的上再分布线图案262以及穿透至少一个上绝缘层266的上通路图案264。
可以通过顺序地堆叠上再分布线图案262(或上通路图案264和上再分布线图案262)以及上绝缘层266来形成上再分布线结构260。
例如,制造上再分布线结构260的详细方法如下。首先,形成构成上再分布线结构260的最下面的上再分布线图案层(例如,第一上层LY21)的上再分布线图案262,以接触第一连接柱状物220和第二连接柱状物236中的每一个。然后,在第一上层LY21的上再分布线图案262上形成暴露第一上层LY21的上再分布线图案262的一部分的上绝缘层266,并且形成连接到第一上层LY21的上再分布线图案262的上通路图案264。这里,上通路图案264和上再分布线图案262可以一体地形成。通过重复这些过程,可以形成具有至少一个上绝缘层266和包括第一上层LY21和第二上层LY22在内的多个上再分布线图案层的上再分布线结构260。
上再分布线结构260的上再分布线图案层的数目可以少于下再分布线结构210的下再分布线图案层的数目。例如,下再分布线结构210可以包括至少三个下再分布线图案层,上再分布线结构260可以包括至少两个上再分布线图案层,少于下再分布线结构210的至少三个下再分布线图案层。
参照图10C,在上再分布线结构260上附接至少两个半导体芯片300。至少两个半导体芯片300可以包括第一半导体芯片310和第二半导体芯片320。
第一半导体芯片310的第一芯片焊盘314和第二半导体芯片320的第二芯片焊盘324可以各自经由芯片连接构件370连接到上再分布线结构260的上再分布线图案262。
可以在上再分布线结构260与第一半导体芯片310和第二半导体芯片320中的每一个之间填充围绕芯片连接构件370的底部填充材料层380。
在图8的半导体封装件1g中,可以在上再分布线结构260上附接图8的第二半导体芯片330而不是第二半导体芯片320。
参照图10D,形成围绕上再分布线结构260上的至少两个半导体芯片300的初步模制构件400P。初步模制构件400P可以由例如EMC形成。初步模制构件400P可以覆盖上再分布线结构260的顶表面以及至少两个半导体芯片300(例如,第一半导体芯片310和第二半导体芯片320)的侧表面和顶表面。
参照图10E,去除图10D的初步模制构件400P的上部,使得至少两个半导体芯片300(例如,第一半导体芯片310和第二半导体芯片320)的顶表面被暴露,从而形成模制构件400。模制构件400的顶表面和至少两个半导体芯片300(例如,第一半导体芯片310和第二半导体芯片320)的顶表面可以共面。模制构件400可以覆盖上再分布线结构260的顶表面和至少两个半导体芯片300(例如,第一半导体芯片310和第二半导体芯片320)的侧表面。
参照图10F,将图10E的附接离型膜20的载体基板10与下再分布线结构210分离。然后,去除多个下绝缘层216中的最下面的下绝缘层216的一部分,以形成暴露第一下层LY11的下再分布线图案212的一部分的焊盘开口PO,并且通过该焊盘开口PO附接与第一下层LY11的下再分布线图案212的底表面接触的板连接构件270。
参照图10G,制备包括基底板层110和分别设置在基底板层110的顶表面和底表面的上焊盘122和下焊盘124的封装件基底基板100,然后在该封装件基底基板100上附接图10F的所得产品,使得板连接构件270连接到封装件基底基板100的上焊盘122。
外部连接端子150可以附接到封装件基底基板100的下焊盘124。
然后,如图2所示,设置散热构件500以接触至少两个半导体芯片300的顶表面从而形成半导体封装件1a。根据一个实施例,可以通过设置散热构件500以接触封装件基底基板100的顶表面并围绕至少两个半导体芯片300来形成半导体封装件1a。
图11至图14是根据实施例的半导体封装件2至5的平面布局。图1A至图8的半导体封装件1和1a至1f可以是图11至图14的半导体封装件2至5的全部或部分的截面图。
参照图11,半导体封装件2包括位于内插件230a上的上再分布线结构260以及设置在上再分布线结构260上并包括第一半导体芯片310a和第二半导体芯片320的至少两个半导体芯片302。
第一半导体芯片310a和第二半导体芯片320a可以例如彼此间隔开地设置在上再分布线结构260上。第一半导体芯片310a的一部分和第二半导体芯片320a的一部分可以与内插件230a的不同部分交叠。
在半导体封装件2中,第一半导体芯片310a和第二半导体芯片320a可以经由上再分布线结构260和内插件230a彼此电连接。
例如,第一半导体芯片310a与第二半导体芯片320a之间的数据发送和/或接收以及第一半导体芯片310a与第二半导体芯片320a之间的用于时钟同步的信号传输可以仅经由上再分布线结构260和内插件230来执行。
在根据一个实施例的半导体封装件2中,由于第一半导体芯片310a与第二半导体芯片320a之间的信号经由上再分布线结构260和内插件230a传输,而其他信号不通过内插件230a,所以内插件230a的所需尺寸相对较小。因此,半导体封装件2可以具有低制造成本和高产量。
图12是根据一个实施例的半导体封装件3的平面布局。
参照图12,半导体封装件3包括位于多个内插件230b上的上再分布线结构260和设置在上再分布线结构260上的多个半导体芯片303。多个半导体芯片303可以彼此间隔开地设置在上再分布线结构上260。多个半导体芯片303可以包括主半导体芯片310b、第一子半导体芯片320b-I、第二子半导体芯片320b-II、第三子半导体芯片320b-III和第四子半导体芯片320b-IV。
多个内插件230b可以彼此间隔开。多个内插件230b可以包括第一子内插件230b-I、第二子内插件230b-II、第三子内插件230b-III和第四子内插件230b-IV。
主半导体芯片310b的不同部分可以分别与多个内插件230b的一部分交叠。第一子半导体芯片320b-I的一部分至第四子半导体芯片320b-IV的一部分可以分别与第一子内插件230b-I的一部分至第四子内插件230b-IV的一部分交叠。
在图12中,多个半导体芯片303包括一个主半导体芯片310b和四个周围的子半导体芯片(例如,第一子半导体芯片320b-I至第四子半导体芯片32b-IV),或者,多个半导体芯片303可以包括一个主半导体芯片310b和至少两个周围的子半导体芯片。内插件230b的数目可以等于包括在多个半导体芯片303中的子半导体芯片的数目,或是其整数倍。
在半导体封装件3中,主半导体芯片310b和第一子半导体芯片320b-I至第四子半导体芯片320b-IV可以经由上再分布线结构260和第一子内插件230b-I至第四子内插件230b-IV彼此电连接。
在根据一个实施例的半导体封装件3中,由于主半导体芯片310b与第一子半导体芯片320b-I至第四子半导体芯片320b-IV中的每一个之间的信号经由上再分布线结构260以及彼此间隔开的第一子内插件230b-I至第四子内插件230b-IV传输,而其他信号不经过多个内插件230b,所以多个内插件230b的所需尺寸相对较小。因此,半导体封装件3可以具有低制造成本和高产量。
图13是根据另一实施例的半导体封装件4的平面布局。
参照图13,半导体封装件4包括位于彼此间隔开的多个内插件230c上的上再分布线结构260以及位于上再分布线结构260上的多个半导体芯片304,半导体芯片304包括第一半导体芯片310c至第三半导体芯片330c。多个内插件230c可以包括第一子内插件230c-I和第二子内插件230c-II。
第一半导体芯片310c至第三半导体芯片330c可以彼此间隔开地设置在上再分布线结构260上。第一半导体芯片310c的一部分和第二半导体芯片320c的一部分可以分别与第一子内插件230c-I的不同部分交叠,第二半导体芯片320c的另一部分和第三半导体芯片330c的一部分可以分别与第二子内插件230c-II的不同部分交叠。
在半导体封装件4中,第一半导体芯片310c和第二半导体芯片320c可以经由上再分布线结构260和第一子内插件230c-I彼此电连接,第二半导体芯片320c和第三半导体芯片330c可以经由上再分布线结构260和第二子内插件230c-II彼此电连接。
在根据一个实施例的半导体封装件4中,由于第一半导体芯片310c与第二半导体芯片320c之间的信号以及第二半导体芯片320c与第三半导体芯片330c之间的信号经由上再分布线结构260和彼此间隔开的多个内插件230c传输,而其他信号不通过多个内插件230c,所以多个内插件230c的所需尺寸相对较小。因此,半导体封装件4可以具有低制造成本和高产量。
图14是根据另一实施例的半导体封装件5的平面布局。
参照图14,半导体封装件5包括位于彼此间隔开的多个内插件230d上的上再分布线结构260以及设置在上再分布线结构260上并且包括第一半导体芯片310d和第二半导体芯片320d的至少两个半导体芯片305。多个内插件230可以包括第一子内插件230d-I和第二子内插件230d-II。
第一半导体芯片310d和第二半导体芯片320d可以彼此间隔开地设置在上再分布线结构260上。第一半导体芯片310d的不同部分和第二半导体芯片320d的不同部分可以分别与多个内插件230的不同部分交叠。例如,第一半导体芯片310d的不同部分可以分别与第一子内插件230d-I的一部分和第二子内插件230d-II的一部分交叠,第二半导体芯片320d的不同部分可以分别与第一子内插件230d-I的另一部分和第二子内插件230d-II的另一部分交叠。
在半导体封装件5中,第一半导体芯片310d和第二半导体芯片320d可以经由上再分布线结构260和第一子内插件230d-I以及经由上再分布线结构260和第二子内插件230d-II彼此电连接。
在根据一个实施例的半导体封装件5中,由于第一半导体芯片310d与第二半导体芯片320d之间的信号经由上再分布线结构260和多个内插件230d传输,而其他信号不经过多个内插件230d。而且,由于多个内插件230d包括彼此间隔开的第一子内插件230d-I和第二子内插件230d-II,因此多个内插件230d的所需尺寸相对较小。而且,由于第一半导体芯片310d与第二半导体芯片320d之间的信号经由彼此间隔开的第一子内插件230d-I和第二子内插件230d-II分开传输,因此可以增加用于第一半导体芯片310d和第二半导体芯片320d中的每一个的信号传输的芯片焊盘(例如,图1A的第一芯片焊盘314和第二芯片焊盘324)的设计自由度。因此,半导体封装件5可以具有低制造成本和高产量。
虽然已经参照本发明构思的实施例具体示出和描述了本发明构思,但是应当理解的是,在不脱离所附权利要求的精神和范围的情况下,可以对本文进行形式和细节上各种改变。
Claims (20)
1.一种半导体封装件,包括:
下再分布线结构,所述下再分布线结构包括多个下绝缘层和分别位于所述多个下绝缘层的顶表面和底表面中的至少一个上的多个下再分布线图案;
多个第一连接柱状物,所述多个第一连接柱状物分别位于所述多个下再分布线图案中的至少一部分下再分布线图案上;
内插件,所述内插件位于所述下再分布线结构上并且与所述多个第一连接柱状物间隔开,并且包括内插基板、位于所述内插基板的顶表面上的多个连接布线图案以及分别位于所述多个连接布线图案中的至少一部分连接布线图案上的多个第二连接柱状物;
上再分布线结构,所述上再分布线结构包括至少一个上绝缘层和位于所述至少一个上绝缘层的顶表面或底表面上并分别连接到所述多个第一连接柱状物和所述多个第二连接柱状物的多个上再分布线图案;以及
至少两个半导体芯片,所述至少两个半导体芯片位于所述上再分布线结构上,所述至少两个半导体芯片彼此间隔开地电连接到所述多个上再分布线图案。
2.根据权利要求1所述的半导体封装件,其中,所述多个下再分布线图案中的每个下再分布线图案构成一个下再分布线图案层,所述多个上再分布线图案中的每个上再分布线图案构成一个上再分布线图案层,
其中,所述上再分布线图案层的数目小于所述下再分布线图案层的数目。
3.根据权利要求1所述的半导体封装件,其中,所述多个第一连接柱状物的高度大于所述多个第二连接柱状物的高度。
4.根据权利要求1所述的半导体封装件,其中,所述多个第一连接柱状物的高度大于所述内插件的高度。
5.根据权利要求1所述的半导体封装件,其中,所述多个第一连接柱状物的顶表面和所述多个第二连接柱状物的顶表面位于同一水平面。
6.根据权利要求1所述的半导体封装件,其中,所述多个第一连接柱状物的底表面所在的水平面低于所述内插件的底表面。
7.根据权利要求1所述的半导体封装件,所述半导体封装件还包括填充绝缘层,所述填充绝缘层在所述下再分布线结构与所述上再分布线结构之间包围所述多个第一连接柱状物和所述内插件。
8.根据权利要求7所述的半导体封装件,其中,所述多个第一连接柱状物的顶表面、所述多个第二连接柱状物的顶表面和所述填充绝缘层的顶表面共面。
9.一种半导体封装件,包括:
封装件基底基板;
下再分布线结构,所述下再分布线结构位于所述封装件基底基板上并且包括多个下再分布线图案;
多个第一连接柱状物,所述多个第一连接柱状物分别位于所述多个下再分布线图案中的至少一部分下再分布线图案上;
至少一个内插件,所述至少一个内插件位于所述下再分布线结构上并且彼此间隔开,所述至少一个内插件中的每个内插件包括多个连接布线图案以及分别位于所述多个连接布线图案的一部分上的彼此间隔开的多个第二连接柱状物;
上再分布线结构,所述上再分布线结构位于所述至少一个内插件和所述多个第一连接柱状物上,并且包括分别连接到所述多个第一连接柱状物和所述多个第二连接柱状物的多个上再分布线图案;以及
至少两个半导体芯片,所述至少两个半导体芯片在所述上再分布线结构上彼此间隔开并且电连接到所述多个上再分布线图案。
10.根据权利要求9所述的半导体封装件,所述半导体封装件被配置为经由所述上再分布线结构和所述至少一个内插件在所述至少两个半导体芯片之间传输信号,并且
所述半导体封装件被配置为经由所述上再分布线结构、所述多个第一连接柱状物和所述下再分布线结构在所述至少两个半导体芯片与所述封装件基底基板之间传输信号。
11.根据权利要求9所述的半导体封装件,其中,所述多个上再分布线图案的最小节距大于所述多个连接布线图案的最小节距。
12.根据权利要求9所述的半导体封装件,其中,所述多个上再分布线图案的宽度和厚度分别大于所述多个连接布线图案的宽度和厚度。
13.根据权利要求9所述的半导体封装件,其中,所述至少两个半导体芯片包括主半导体芯片和多个子半导体芯片,
其中,所述至少一个内插件包括多个子内插件,所述多个子内插件分别与所述主半导体芯片的一部分和所述多个子半导体芯片中的每一个子半导体芯片的一部分交叠,以将所述主半导体芯片与所述多个子半导体芯片中的每一个子半导体芯片电互连。
14.根据权利要求9所述的半导体封装件,其中,所述至少两个半导体芯片包括第一半导体芯片、第二半导体芯片和第三半导体芯片,
其中,所述至少一个内插件包括第一子内插件和第二子内插件,所述第一子内插件与所述第一半导体芯片的一部分以及所述第二半导体芯片的一部分交叠,以将所述第一半导体芯片电连接到所述第二半导体芯片,所述第二子内插件与所述第二半导体芯片的另一部分以及所述第三半导体芯片的一部分交叠,以将所述第二半导体芯片电连接到所述第三半导体芯片。
15.根据权利要求9所述的半导体封装件,所述半导体封装件还包括与所述至少两个半导体芯片的顶表面接触的散热构件。
16.根据权利要求15所述的半导体封装件,其中,所述散热构件通过接触所述封装件基底基板的顶表面而围绕所述至少两个半导体芯片。
17.根据权利要求9所述的半导体封装件,其中,所述至少两个半导体芯片包括第一半导体芯片和第二半导体芯片,
其中,所述至少一个内插件包括第一子内插件和第二子内插件,所述第一子内插件与所述第一半导体芯片的一部分以及所述第二半导体芯片的一部分交叠,所述第二子内插件与所述第一半导体芯片的另一部分以及所述第二半导体芯片的另一部分交叠,以将所述第一半导体芯片电连接到所述第二半导体芯片。
18.一种半导体封装件,包括:
下再分布线结构,所述下再分布线结构包括多个下再分布线图案;
多个第一连接柱状物,所述多个第一连接柱状物连接到所述多个下再分布线图案;
内插件,所述内插件位于所述下再分布线结构上,所述内插件包括内插基板、位于所述内插基板上的多个连接布线图案以及位于所述多个连接布线图案上的多个第二连接柱状物;
上再分布线结构,所述上再分布线结构包括位于所述多个第一连接柱状物和所述内插件上并且电连接到所述多个第一连接柱状物和所述多个第二连接柱状物的多个上再分布线图案;以及
至少两个半导体芯片,所述至少两个半导体芯片位于所述上再分布线结构上并且电连接到所述多个上再分布线图案,
其中,所述多个上再分布线图案的一部分和所述多个下再分布线图案的一部分在水平方向上延伸超过由所述至少两个半导体芯片所占据的覆盖区域。
19.根据权利要求18所述的半导体封装件,所述半导体封装件还包括无源器件,所述无源器件连接到所述下再分布线结构上的所述多个下再分布线图案的一部分。
20.根据权利要求18所述的半导体封装件,其中,所述内插件还包括通过穿透所述内插基板将所述多个连接布线图案与所述多个下再分布线图案互连的贯通电极。
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Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN111554658A (zh) * | 2020-04-30 | 2020-08-18 | 通富微电子股份有限公司 | 一种半导体封装器件 |
CN111554630A (zh) * | 2020-04-30 | 2020-08-18 | 通富微电子股份有限公司 | 一种芯片封装方法 |
CN111554631A (zh) * | 2020-04-30 | 2020-08-18 | 通富微电子股份有限公司 | 一种芯片封装方法 |
CN111554629A (zh) * | 2020-04-30 | 2020-08-18 | 通富微电子股份有限公司 | 一种芯片封装方法 |
CN111554619A (zh) * | 2020-04-30 | 2020-08-18 | 通富微电子股份有限公司 | 一种芯片封装方法 |
CN111554656A (zh) * | 2020-04-30 | 2020-08-18 | 通富微电子股份有限公司 | 一种半导体封装器件 |
WO2023019516A1 (zh) * | 2021-08-19 | 2023-02-23 | 华为技术有限公司 | 芯片封装结构及电子设备 |
Families Citing this family (35)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20200161206A1 (en) * | 2018-11-20 | 2020-05-21 | Advanced Semiconductor Engineering, Inc. | Semiconductor package structure and semiconductor manufacturing process |
US11217546B2 (en) * | 2018-12-14 | 2022-01-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Embedded voltage regulator structure and method forming same |
US11189599B2 (en) * | 2019-05-30 | 2021-11-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | System formed through package-in-package formation |
DE102019128274A1 (de) * | 2019-05-30 | 2020-12-03 | Taiwan Semiconductor Manufacturing Co., Ltd. | Package-in-Package-gebildetes System |
US11387177B2 (en) * | 2019-06-17 | 2022-07-12 | Taiwan Semiconductor Manufacturing Company Ltd. | Package structure and method for forming the same |
US11296053B2 (en) | 2019-06-26 | 2022-04-05 | Invensas Bonding Technologies, Inc. | Direct bonded stack structures for increased reliability and improved yield in microelectronics |
US20210005542A1 (en) * | 2019-07-03 | 2021-01-07 | Intel Corporation | Nested interposer package for ic chips |
US11195816B2 (en) * | 2019-07-23 | 2021-12-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit packages comprising a plurality of redistribution structures and methods of forming the same |
US10868538B1 (en) * | 2019-07-29 | 2020-12-15 | Taiwan Semiconductor Manufacturing Company Ltd. | Logic cell structure and integrated circuit with the logic cell structure |
US11830787B2 (en) | 2019-08-06 | 2023-11-28 | Intel Corporation | Thermal management in integrated circuit packages |
US11784108B2 (en) * | 2019-08-06 | 2023-10-10 | Intel Corporation | Thermal management in integrated circuit packages |
US20210043573A1 (en) * | 2019-08-06 | 2021-02-11 | Intel Corporation | Thermal management in integrated circuit packages |
KR102517379B1 (ko) * | 2020-02-14 | 2023-03-31 | 삼성전자주식회사 | 반도체 패키지의 제조 방법 |
JP2021150567A (ja) | 2020-03-23 | 2021-09-27 | キオクシア株式会社 | 半導体装置及びその製造方法 |
US11594498B2 (en) | 2020-04-27 | 2023-02-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor package and method |
US11355463B2 (en) | 2020-05-20 | 2022-06-07 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor package and method |
DE102020124229A1 (de) | 2020-05-20 | 2021-11-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Halbleitervorrichtung und verfahren |
US11728254B2 (en) | 2020-05-22 | 2023-08-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Giga interposer integration through chip-on-wafer-on-substrate |
KR20220007410A (ko) | 2020-07-10 | 2022-01-18 | 삼성전자주식회사 | 반도체 패키지 |
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TWI777633B (zh) * | 2020-08-06 | 2022-09-11 | 力成科技股份有限公司 | 封裝結構及其製造方法 |
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US11764177B2 (en) | 2020-09-04 | 2023-09-19 | Adeia Semiconductor Bonding Technologies Inc. | Bonded structure with interconnect structure |
KR20220031245A (ko) * | 2020-09-04 | 2022-03-11 | 에스케이하이닉스 주식회사 | 적층 반도체 칩을 포함하는 반도체 패키지 및 그 제조 방법 |
US11728273B2 (en) | 2020-09-04 | 2023-08-15 | Adeia Semiconductor Bonding Technologies Inc. | Bonded structure with interconnect structure |
US20220102280A1 (en) * | 2020-09-25 | 2022-03-31 | Apple Inc. | Very Fine Pitch and Wiring Density Organic Side by Side Chiplet Integration |
KR20220047066A (ko) | 2020-10-08 | 2022-04-15 | 삼성전자주식회사 | 반도체 패키지 장치 |
KR20220048695A (ko) * | 2020-10-13 | 2022-04-20 | 삼성전자주식회사 | 반도체 칩, 적층 반도체 칩 구조체, 및 이를 포함하는 반도체 패키지 |
US11600562B2 (en) | 2020-10-21 | 2023-03-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor packages and method of manufacturing the same |
US11538759B2 (en) * | 2021-01-26 | 2022-12-27 | Deca Technologies Usa, Inc. | Fully molded bridge interposer and method of making the same |
US11837567B2 (en) | 2021-02-26 | 2023-12-05 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor package and method of forming thereof |
US11855057B2 (en) * | 2021-07-08 | 2023-12-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package structure and method of forming the same |
US11935761B2 (en) | 2021-08-27 | 2024-03-19 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor package and method of forming thereof |
WO2023034738A1 (en) * | 2021-09-01 | 2023-03-09 | Adeia Semiconductor Technologies Llc | Stacked structure with interposer |
CN117957651A (zh) * | 2021-09-14 | 2024-04-30 | 罗姆股份有限公司 | 半导体装置以及半导体元件的安装结构 |
Family Cites Families (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
SG119329A1 (en) * | 2004-07-29 | 2006-02-28 | Fujikura Ltd | Semiconductor device and method for manufacturing the same |
US9337120B2 (en) | 2012-08-17 | 2016-05-10 | Cisco Technology, Inc. | Multi-chip module with multiple interposers |
KR101411813B1 (ko) * | 2012-11-09 | 2014-06-27 | 앰코 테크놀로지 코리아 주식회사 | 반도체 디바이스 및 그 제조 방법 |
US20140131854A1 (en) | 2012-11-13 | 2014-05-15 | Lsi Corporation | Multi-chip module connection by way of bridging blocks |
US8901748B2 (en) | 2013-03-14 | 2014-12-02 | Intel Corporation | Direct external interconnect for embedded interconnect bridge package |
US9455162B2 (en) * | 2013-03-14 | 2016-09-27 | Invensas Corporation | Low cost interposer and method of fabrication |
US20150115433A1 (en) | 2013-10-25 | 2015-04-30 | Bridge Semiconductor Corporation | Semiconducor device and method of manufacturing the same |
US9406361B2 (en) | 2014-03-27 | 2016-08-02 | Oracle International Corporation | Low latency, high bandwidth memory subsystem incorporating die-stacked DRAM |
US9704735B2 (en) * | 2014-08-19 | 2017-07-11 | Intel Corporation | Dual side solder resist layers for coreless packages and packages with an embedded interconnect bridge and their methods of fabrication |
JP6378616B2 (ja) * | 2014-11-12 | 2018-08-22 | イビデン株式会社 | 電子部品内蔵プリント配線板 |
US10515939B2 (en) | 2015-02-17 | 2019-12-24 | Mediatek Inc. | Wafer-level package having multiple dies arranged in side-by-side fashion and associated yield improvement method |
US10074630B2 (en) | 2015-04-14 | 2018-09-11 | Amkor Technology, Inc. | Semiconductor package with high routing density patch |
US9595494B2 (en) * | 2015-05-04 | 2017-03-14 | Qualcomm Incorporated | Semiconductor package with high density die to die connection and method of making the same |
US10008439B2 (en) | 2015-07-09 | 2018-06-26 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Thin recon interposer package without TSV for fine input/output pitch fan-out |
US9368450B1 (en) * | 2015-08-21 | 2016-06-14 | Qualcomm Incorporated | Integrated device package comprising bridge in litho-etchable layer |
US9768145B2 (en) * | 2015-08-31 | 2017-09-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods of forming multi-die package structures including redistribution layers |
US9761533B2 (en) * | 2015-10-16 | 2017-09-12 | Xilinx, Inc. | Interposer-less stack die interconnect |
US10037946B2 (en) * | 2016-02-05 | 2018-07-31 | Dyi-chung Hu | Package structure having embedded bonding film and manufacturing method thereof |
US20170287838A1 (en) | 2016-04-02 | 2017-10-05 | Intel Corporation | Electrical interconnect bridge |
US10276403B2 (en) | 2016-06-15 | 2019-04-30 | Avago Technologies International Sales Pe. Limited | High density redistribution layer (RDL) interconnect bridge using a reconstituted wafer |
US10170428B2 (en) | 2016-06-29 | 2019-01-01 | Intel Corporation | Cavity generation for embedded interconnect bridges utilizing temporary structures |
US10833052B2 (en) * | 2016-10-06 | 2020-11-10 | Micron Technology, Inc. | Microelectronic package utilizing embedded bridge through-silicon-via interconnect component and related methods |
US10872852B2 (en) * | 2016-10-12 | 2020-12-22 | Micron Technology, Inc. | Wafer level package utilizing molded interposer |
US10763239B2 (en) * | 2017-10-27 | 2020-09-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | Multi-chip wafer level packages and methods of forming the same |
-
2018
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Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN111554658A (zh) * | 2020-04-30 | 2020-08-18 | 通富微电子股份有限公司 | 一种半导体封装器件 |
CN111554630A (zh) * | 2020-04-30 | 2020-08-18 | 通富微电子股份有限公司 | 一种芯片封装方法 |
CN111554631A (zh) * | 2020-04-30 | 2020-08-18 | 通富微电子股份有限公司 | 一种芯片封装方法 |
CN111554629A (zh) * | 2020-04-30 | 2020-08-18 | 通富微电子股份有限公司 | 一种芯片封装方法 |
CN111554619A (zh) * | 2020-04-30 | 2020-08-18 | 通富微电子股份有限公司 | 一种芯片封装方法 |
CN111554656A (zh) * | 2020-04-30 | 2020-08-18 | 通富微电子股份有限公司 | 一种半导体封装器件 |
WO2023019516A1 (zh) * | 2021-08-19 | 2023-02-23 | 华为技术有限公司 | 芯片封装结构及电子设备 |
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US10847468B2 (en) | 2020-11-24 |
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US20230317623A1 (en) | 2023-10-05 |
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