CN108074908B - 半导体芯片 - Google Patents

半导体芯片 Download PDF

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Publication number
CN108074908B
CN108074908B CN201711119538.4A CN201711119538A CN108074908B CN 108074908 B CN108074908 B CN 108074908B CN 201711119538 A CN201711119538 A CN 201711119538A CN 108074908 B CN108074908 B CN 108074908B
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China
Prior art keywords
bump
region
passivation layer
semiconductor chip
upper passivation
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CN201711119538.4A
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CN108074908A (zh
Inventor
秦正起
李来寅
朴点龙
千镇豪
孙成旻
李镐珍
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Abstract

一种半导体芯片包括：半导体衬底，包括其中配置有凸块的凸块区及不包括凸块的非凸块区；以及钝化层，形成在所述半导体衬底的所述凸块区及所述非凸块区上，其中所述凸块区中所述钝化层的厚度厚于所述非凸块区中所述钝化层的厚度，且在所述凸块区与所述非凸块区之间具有台阶。所述半导体芯片具有提高的可靠性。

Description

半导体芯片
相关申请的交叉参考
本申请主张在2016年11月14日在韩国知识产权局提出申请的韩国专利申请第10-2016-0151306号的权利，所述申请的公开内容并入本申请供参考。
技术领域
本发明涉及一种半导体芯片，且更具体来说涉及一种能够提高可靠性的半导体芯片。
背景技术
随着半导体衬底(或半导体晶片)的直径增大且半导体芯片的集成度提高，半导体制造工艺或半导体芯片的可靠性可能会降低。因此，有必要努力提高半导体制造工艺或半导体芯片的可靠性。
发明内容
本发明提供一种具有提高的可靠性的半导体芯片。
根据本发明的一方面，提供一种半导体芯片，半导体芯片包括：半导体衬底，包括其中配置有凸块(bump)的凸块区及不具有凸块的非凸块区；以及钝化层(passivationlayer)，位于半导体衬底中的凸块区及非凸块区上。凸块区中钝化层的厚度厚于非凸块区中钝化层的厚度，且在凸块区与非凸块区之间具有台阶(step)。
根据本发明的一方面，提供一种半导体芯片，半导体芯片包括：半导体衬底，包括其中配置有通孔(via)及凸块的凸块区及不包括凸块的非凸块区；以及钝化层，位于半导体衬底中的凸块区及非凸块区上。凸块区中钝化层的厚度厚于非凸块区中钝化层的厚度，且在凸块区与非凸块区之间具有台阶。
根据本发明的一方面，提供一种半导体芯片，半导体芯片包括：半导体衬底，具有第一表面及与第一表面相对的第二表面，且包括其中在第一表面上设置有凸块焊盘及凸块的凸块区及不具有凸块的非凸块区；重布线配线区(redistribution wiring region)及虚设区(dummy region)，在半导体衬底的第一表面或第二表面上具有重布线配线图案(redistribution wiring pattern)及虚设图案(dummy pattern)中的至少一者；以及钝化层，被配置成在半导体衬底的第一表面或第二表面上覆盖凸块区、非凸块区、以及重布线配线区及虚设区。凸块区中钝化层的厚度厚于非凸块区中钝化层的厚度，且在凸块区与非凸块区之间具有台阶。
附图说明
由以下结合附图的详细说明，将更清楚地理解本发明概念的实施例，在附图中：
图1是根据本发明一实施例的半导体芯片的部分剖视图。
图2是根据本发明一实施例的半导体芯片的部分剖视图。
图3是根据本发明一实施例的半导体芯片的部分剖视图。
图4是根据本发明一实施例的半导体芯片的部分剖视图。
图5是根据本发明一实施例的半导体芯片的部分剖视图。
图6是根据本发明一实施例的半导体芯片的部分剖视图。
图7是根据本发明一实施例的半导体芯片的部分剖视图。
图8是根据本发明一实施例的半导体芯片的部分剖视图。
图9是根据本发明一实施例的半导体芯片的部分剖视图。
图10是根据本发明一实施例的半导体芯片的部分剖视图。
图11是根据本发明一实施例的半导体芯片的部分剖视图。
图12及图13是部分地示出根据本发明一实施例的半导体芯片的平面图，其说明凸块的厚度与钝化层的厚度之间的关系。
图14是根据本发明一实施例的半导体芯片的部分平面图，其说明凸块的厚度与钝化层的厚度之间的关系。
图15是根据本发明一实施例的半导体芯片的部分平面图，其说明凸块的厚度与钝化层的厚度之间的关系。
图16是根据本发明一实施例的包括半导体芯片的半导体封装的剖视图。
图17是图16的部分放大图。
图18是图16所示半导体芯片的部分放大剖视图。
图19是根据本发明一实施例的包括半导体芯片的半导体封装的剖视图。
图20是根据本发明一实施例的包括半导体芯片的半导体封装的剖视图。
图21是图20的部分放大图。
图22是根据本发明一实施例的包括半导体芯片的半导体封装的剖视图。
附图标号说明
10a、10b、10c、10d、10e、10f、10g、10h、10i、10j、10k、40a、40b、40c、40d、720：半导体芯片；
11：半导体衬底；
12、124a、124b：下部钝化层；
14、14a-1、14a-2、14a-3、14b-1、14b-2、178a、178a-1、178a-2：上部钝化层；
14a、14b：上部钝化层；
15、135：通孔绝缘层；
16：通孔；
18：障壁金属焊盘；
20、194a、730：凸块；
22、192a、726：凸块焊盘；
24：配线层；
26：层间绝缘层；
28、28-1、170a、170b、170c：连接焊盘；
30、608、780：外部连接端子；
32、196a：重布线配线图案；
34、197a：虚设图案；
36：凹陷部；
41：隔离区；
42：中心区；
44：外围区；
60、62、64、66、68、70：子区；
100：第一半导体芯片；
102a：第一半导体衬底；
102b：第二半导体衬底；
104：下部层间绝缘层；
106：保护层；
122：上部层间绝缘层；
132：配线金属层；
134：障壁金属层；
150：集成电路层；
152：金属触点；
174a：第一通孔；
174b：第二通孔；
178b：第二上部钝化层；
180：多层式配线图案；
181：第一配线线路；
183：第一垂直插塞；
185：第二配线线路；
187：第二垂直插塞；
189：第三配线线路；
198a：第一底部填充材料；
198b：第二底部填充材料；
200：第二半导体芯片；
300：第三半导体芯片；
400：第四半导体芯片；
500：上部半导体芯片；
600、700：印刷电路板；
604、780a、780b：连接端子；
606、760：衬底焊盘；
610：粘合层；
700a：第一印刷电路板；
700b：第二印刷电路板；
720a：第一半导体芯片；
720b：第二半导体芯片；
724、724a、724b：钝化层；
740：封装单元；
750：底部填充单元；
760a、760b：下部连接焊盘；
765：上部连接焊盘；
770：参考编号；
1000、1000-1、1000-2、1000-3：半导体封装；
1000-2a：第一半导体封装；
1000-2b：第二半导体封装；
ac：有源区；
C：部分；
d1、d1-1、d2、d2-1、d4、d4-1：距离；
d3、d4-2、d5：距离；
F1：第一表面；
F2：第二表面；
ho1、ho3：介层孔；
ho2：焊盘孔；
ho5：孔；
sh1、sh2、sh3、sh4、sh5：台阶；
t1、t2、t3、t4、t5：厚度；
I：凸块区；
II：非凸块区；
III：重布线配线区；
IV：虚设区；
x、y、z：方向。
具体实施方式
以下，将参考附图详细地阐述本发明的实施例。图式中的相同参考编号表示相同元件。下文的实施例可彼此独立地配置或可彼此加以组合。
图1是根据本发明一实施例的半导体芯片10a的部分剖视图。
具体来说，半导体芯片10a可用于存储器芯片、非存储器芯片或中介层(interposer)中。存储器芯片可为非易失性存储器芯片。存储器芯片可为闪速存储器芯片，例如“与非”(NAND)闪速存储器芯片或“或非”(NOR)闪速存储器芯片。
存储器芯片可为相变随机存取存储器(Phase-change Random-Access Memory，PRAM)、磁阻式随机存取存储器(Magneto-resistive Random-Access Memory，MRAM)或电阻式随机存取存储器(Resistive Random-Access Memory，RRAM)。非存储器芯片可为中央处理器、多媒体半导体、随选半导体(on-demand semiconductor)或功率半导体。中介层可为将上部半导体芯片与下部半导体芯片电连接至彼此而不包括有源装置的芯片。
半导体芯片10a可包括半导体衬底11，半导体衬底11具有第一表面F1及与第一表面F1相对的第二表面F2。第二表面F2可在z轴方向(垂直于半导体衬底的表面)上与第一表面F1相对。半导体衬底11可包括半导体晶片，且可包含例如IV族材料或III-V族化合物。
半导体衬底11可为单晶晶片，例如硅单晶晶片。然而，半导体衬底11并非仅限于单晶晶片，而是可使用例如外延(Epi或Epitaxial)晶片、抛光晶片、退火晶片、绝缘体上硅(silicon-on-insulator，SOI)晶片等各种其他晶片作为半导体衬底11。此处，外延晶片表示其中在单晶硅衬底上生长晶体材料的晶片。
半导体芯片10a可包括其中在半导体衬底11的第一表面F1上设置有凸块20的凸块区I。凸块区I中所包括的凸块20可为用于电连接至外部半导体芯片或另一半导体芯片的连接端子。可在半导体衬底11的第一表面F1上形成有源区，例如晶体管或配线层。如果需要，则可在半导体衬底11的第二表面F2上形成有源区，例如晶体管或配线层。凸块区I可包括穿透过半导体衬底11的通孔16以及形成在通孔16上的障壁金属焊盘18。
通孔16可为穿透过半导体衬底11的硅穿孔。通孔16可被形成用于电连接至位于半导体衬底11上方及下方的半导体芯片。可在通孔16的相对的侧壁上形成使半导体衬底11与通孔16彼此绝缘的通孔绝缘层15。
在凸块区I中，凸块20可形成在障壁金属焊盘18上。如果凸块20为焊料凸块，则凸块20可在回焊工艺之后因表面张力效应而维持球形状。然而，如果凸块20为金(Au)凸块，则凸块20可被形成为镀敷方形柱。凸块20可包含例如焊料、金(Au)及铜(Cu)等金属材料。
凸块区I可包括从凸块20或障壁金属焊盘18的相对的侧壁延伸预定距离的外围区。在图1中，凸块区I可包括从障壁金属焊盘18的相对的侧壁延伸预定距离(例如，d1或d1-1)的外围区。
半导体芯片10a可包括其中不在半导体衬底11的第一表面F1上设置凸块20的非凸块区II。非凸块区II可为除凸块20以及相邻于凸块20的外围区之外的区。半导体芯片10a可包括覆盖半导体衬底11的第一表面F1但通孔16除外的下部钝化层12。下部钝化层12可为氧化物层、氮化物层或其组合层。
可在除通孔16之外的下部钝化层12上形成上部钝化层14。上部钝化层14可为氧化物层、氮化物层或其组合层。上部钝化层14可为感光性有机层。感光性有机层可为感光性聚酰亚胺层。上部钝化层14可为最上钝化层。可在上部钝化层14中形成暴露出通孔16的介层孔(via hole)ho1。可在介层孔ho1中在通孔16上形成障壁金属焊盘18。
上部钝化层14可被划分成凸块区I中的上部钝化层14a及非凸块区II中的上部钝化层14b。凸块区I中的上部钝化层14a可在x轴方向(水平方向)上分别从障壁金属焊盘18的一个侧壁及另一侧壁延伸距离d1及距离d1-1。凸块区I可包括在x轴方向(相对于半导体衬底11的表面来说的水平方向)上分别从障壁金属焊盘18的一个侧壁及另一侧壁延伸距离d1及距离d1-1的上部钝化层14a。在图1中，y轴方向垂直于x轴方向，且可与半导体衬底11的表面平行。
尽管在图1中距离d1与距离d1-1被示出为彼此不相等，但如果需要，则距离d1与距离d1-1可彼此相等。当凸块区I中的上部钝化层14a从障壁金属焊盘18的一个侧壁及另一侧壁延伸时，凸块20可稳定地形成在障壁金属焊盘18上。
凸块区I的上部钝化层14a的厚度t1厚于非凸块区II中上部钝化层14b的厚度t2，且在凸块区I与非凸块区II之间形成有台阶sh1。可通过以下方式来获得台阶sh1：在下部钝化层12上形成上部钝化材料层(图中未示出)，以及使用掩模(例如，相移掩模)对上部钝化材料层执行光刻工艺。
台阶sh1可与暴露出通孔16的介层孔ho1的形成同时地形成。台阶sh1可在z轴方向上被形成为垂直的，或可倾斜预定角度。
非凸块区II中上部钝化层14b的厚度t2小于凸块区I中上部钝化层14a的厚度t1，且因此，施加至包括下部钝化层12及半导体衬底11的半导体结构的压力得以减小，且半导体芯片10a的翘曲(warpage)可得以减少。
具体来说，当上部钝化层14包括感光性有机层(例如，感光性聚酰亚胺层)时且当非凸块区II中上部钝化层14b的厚度t2薄于上部钝化层14a的厚度t1时，施加至包括下部钝化层12及半导体衬底11的半导体结构的压力可大幅减小，且半导体芯片10a的翘曲可大幅减少。
图2是根据本发明一实施例的半导体芯片10b的部分剖视图。
具体来说，半导体芯片10b可与图1所示半导体芯片10a几乎相同，只是半导体芯片10b包括多个通孔16以及凸块焊盘22。因此，可省略或扼要地提供关于与图1所示半导体芯片10a的元件相同的元件的说明。
半导体芯片10b在半导体衬底11中包括多个通孔16。可在通孔16的相对的侧壁上形成使半导体衬底11与通孔16彼此绝缘的通孔绝缘层15。尽管图2示出两个通孔16，但如果需要，则可形成三个或更多个通孔16。半导体芯片10b可包括其中在半导体衬底11的第一表面F1上设置有凸块20的凸块区I。
凸块区I可包括穿透过半导体衬底11的通孔16、形成在通孔16上的凸块焊盘22以及形成在凸块焊盘22上的障壁金属焊盘18。凸块焊盘22可形成在通孔16及下部钝化层12上。凸块焊盘22可为将所有通孔16连接至彼此的焊盘。凸块焊盘22可为金属焊盘。
凸块区I可包括在凸块焊盘22上的障壁金属焊盘18上形成的凸块20。凸块区I可包括从凸块20或障壁金属焊盘18的相对的侧壁延伸预定距离的外围区。在图2中，凸块区I可包括从障壁金属焊盘18的相对的侧壁延伸预定距离(例如，d2或d2-1)的外围区。
半导体芯片10b可包括其中不在半导体衬底11的第一表面F1上设置凸块20的非凸块区II。半导体芯片10b可包括覆盖半导体衬底11的第一表面F1但通孔16除外的下部钝化层12。可在除通孔16之外的下部钝化层12上形成上部钝化层14。可在上部钝化层14中形成暴露出凸块焊盘22的焊盘孔ho2。在焊盘孔ho2中，可在凸块焊盘22上形成障壁金属焊盘18。
上部钝化层14可被划分成凸块区I中的上部钝化层14a-1及非凸块区II中的上部钝化层14b-1。凸块区I中的上部钝化层14a-1可在x轴方向(水平方向)上分别从障壁金属焊盘18的一个侧壁及另一侧壁延伸距离d2及距离d2-1。
尽管在图2中距离d2与距离d2-1被示出为彼此不相等，但如果需要，则距离d2与距离d2-1可彼此相等。凸块区I的上部钝化层14a-1的厚度t3厚于非凸块区II中上部钝化层14b-1的厚度t4，且在凸块区I与非凸块区II之间形成有台阶sh2。
图2所示半导体芯片10b的凸块区I中上部钝化层14a-1的厚度t3可因凸块焊盘22而厚于图1所示半导体芯片10a的上部钝化层14a的厚度。图2所示半导体芯片10b的非凸块区II中上部钝化层14b-1的厚度t4可因凸块焊盘22而厚于图1所示半导体芯片10a的非凸块区II中上部钝化层14b的厚度。
可通过以下方式来获得台阶sh2：在下部钝化层12上形成上部钝化材料层(图中未示出)，以及使用掩模(例如，相移掩模)对上部钝化材料层执行光刻工艺。台阶sh2可与暴露出凸块焊盘22的焊盘孔ho2的形成同时地形成。台阶sh2可在z轴方向上被形成为垂直的，或可倾斜预定角度。
图3是根据本发明一实施例的半导体芯片10c的部分剖视图。
详细来说，半导体芯片10c可与图2所示半导体芯片10b几乎相同，只是半导体芯片10c包括包含重布线配线图案32的重布线配线区III。因此，可省略或扼要地提供关于与图1所示半导体芯片10a及图2所示半导体芯片10b的元件相同的元件的说明。
半导体芯片10c可包括其中在半导体衬底11的第一表面F1上设置有凸块20的凸块区I。凸块区I可包括通孔16、凸块焊盘22以及障壁金属焊盘18。半导体芯片10c可包括其中在下部钝化层12上形成有重布线配线图案32的重布线配线区III。重布线配线区III可形成在凸块区I的一侧处。半导体芯片10c可包括其中不在半导体衬底11的第一表面F1上设置凸块20的非凸块区II。
可形成上部钝化层14以覆盖凸块区I、重布线配线区III及非凸块区II。上部钝化层14可形成在下部钝化层12上且覆盖凸块焊盘22及重布线配线图案32。上部钝化层14可被划分成凸块区I中的上部钝化层14a-1、重布线配线区III中的上部钝化层14a-2以及非凸块区II中的上部钝化层14b-1。
凸块区I及重布线配线区III中的上部钝化层14a-1及14a-2可在x轴方向(水平方向)上从障壁金属焊盘18的一个侧壁延伸距离d3。凸块区I中的上部钝化层14a-1可在-x方向(水平方向)上从障壁金属焊盘18的另一侧壁延伸距离d2-1。
凸块区I及重布线配线区III中上部钝化层14a-1及14a-2的厚度t3可厚于非凸块区II中上部钝化层14b-1的厚度t4，且在重布线配线区III与非凸块区II之间形成有台阶sh3，并且在凸块区I与非凸块区II之间形成有台阶sh2。
图3所示半导体芯片10c的凸块区I及重布线配线区III中上部钝化层14a-1及14a-2的厚度t3可因凸块焊盘22及重布线配线图案32而厚于图1所示半导体芯片10a中上部钝化层14a的厚度。图3所示半导体芯片10c的非凸块区II中上部钝化层14b-1的厚度t4可因凸块焊盘22及重布线配线图案32而厚于图1所示半导体芯片10a的非凸块区II中上部钝化层14b的厚度。
可通过以下方式来获得台阶sh2及sh3：在下部钝化层12上形成上部钝化材料层(图中未示出)，以及使用掩模(例如，相移掩模)对上部钝化材料层执行光刻。台阶sh2及sh3可与暴露出凸块焊盘22的焊盘孔ho2的形成同时地形成。台阶sh2及sh3可在z轴方向上被形成为垂直的，或可倾斜预定角度。
图4是根据本发明一实施例的半导体芯片10d的部分剖视图。
详细来说，半导体芯片10d可等同于图1所示半导体芯片10a，只是半导体芯片10d在半导体衬底11的第一表面F1上包括多个通孔16及凸块焊盘22，且在半导体衬底11的第二表面F2上包括有源区ac、连接焊盘28以及外部连接端子30。因此，可省略或扼要地提供关于与图1所示半导体芯片10a的元件相同的元件的说明。
半导体芯片10d在半导体衬底11中包括多个通孔16。可在通孔16的相对的侧壁上形成使半导体衬底11与通孔16彼此绝缘的通孔绝缘层15。尽管图4示出三个通孔16，但如果需要，则可形成四个或更多个通孔16。半导体芯片10d可包括其中在半导体衬底11的第一表面F1上设置有凸块20的凸块区I。
凸块区I可包括穿透过半导体衬底11的通孔16及形成在通孔16上的凸块焊盘22。凸块焊盘22可形成在通孔16及下部钝化层12上。凸块焊盘22可为将所有通孔16连接至彼此的焊盘。凸块焊盘22可为金属焊盘。
与图1所说明的实例不同，可在凸块区I中的凸块焊盘22上形成凸块20。凸块区I可包括从凸块20或凸块焊盘22的相对的侧壁延伸预定距离的外围区。在图4中，凸块区I可包括从凸块20的相对的侧壁延伸预定距离(例如，d4或d4-1)的外围区。
半导体芯片10d可包括其中不在半导体衬底11的第一表面F1上设置凸块20的非凸块区II。半导体芯片10d可包括覆盖半导体衬底11的第一表面F1但通孔16除外的下部钝化层12。可在除通孔16之外的下部钝化层12上形成上部钝化层14。可在上部钝化层14中形成暴露出通孔16的介层孔ho3。可在介层孔ho3中形成凸块焊盘22及凸块20。
在图4中，凸块焊盘22的厚度被示出为与上部钝化层14a的厚度相等。然而，如果需要，凸块焊盘22的厚度可被形成为更薄。另外，在其中凸块20为焊料凸块的情形中，凸块20可根据上述回焊工艺而具有各种球型形状。
上部钝化层14可被划分成凸块区I中的上部钝化层14a及非凸块区II中的上部钝化层14b。凸块区I中的上部钝化层14a可在x方向(水平方向)上分别从凸块20的一个侧壁及另一侧壁延伸距离d4及距离d4-1。尽管在图4中距离d4与距离d4-1被示出为彼此不相等，但如果需要，则距离d4与距离d4-1可彼此相等。
凸块区I的上部钝化层14a的厚度t1厚于非凸块区II中上部钝化层14b的厚度t2，且在凸块区I与非凸块区II之间产生台阶sh2。可通过以下方式来获得台阶sh2：在下部钝化层12上形成上部钝化材料层(图中未示出)，以及使用掩模(例如，相移掩模)对上部钝化材料层执行光刻工艺。台阶sh2可与暴露出通孔16的介层孔ho3的形成同时地形成。
可在半导体衬底11的第二表面F2上形成包括配线层24及层间绝缘层26的有源区ac。为方便说明起见，图4仅示出配线层24及层间绝缘层26作为有源区ac。可在有源区ac上形成连接焊盘28及外部连接端子30。半导体芯片10d可经由外部连接端子30而安装在外部电路板(例如，印刷电路板)上。
图5是根据本发明一实施例的半导体芯片10e的部分剖视图。
详细来说，半导体芯片10e可等同于图4所示半导体芯片10d，只是在半导体衬底11的第一表面F1上形成有源区ac且在半导体衬底11的第二表面F2上形成将多个通孔16连接至彼此的连接焊盘28-1。因此，将省略或扼要地提供关于与图1及图4所示半导体芯片10a及10d的元件相同的元件的说明。
半导体芯片10e在半导体衬底11中包括多个通孔16。可在半导体衬底11的第一表面F1上形成包括配线层24及层间绝缘层26的有源区ac。半导体芯片10e可在半导体衬底11的第二表面F2上包括连接焊盘28-1，以用于连接多个通孔16。可在连接焊盘28-1上形成外部连接端子30，例如，焊料凸块。半导体芯片10e可经由外部连接端子30而安装在外部电路板(例如，印刷电路板)上。
图6是根据本发明一实施例的半导体芯片10f的部分剖视图。
详细来说，半导体芯片10f可与图4所示半导体芯片10d相同，只是在介层孔ho3中进一步形成障壁金属焊盘18。因此，将省略或扼要地提供关于与图1及图4所示半导体芯片10a及10d的元件相同的元件的说明。
半导体芯片10e在半导体衬底11中包括多个通孔16。可在半导体衬底11的第一表面F1上在除通孔16之外的下部钝化层12上形成上部钝化层14。可在上部钝化层14中形成暴露出通孔16的介层孔ho3。可在介层孔ho3中形成凸块焊盘22及障壁金属焊盘18。凸块焊盘22可为连接多个通孔16的焊盘。可通过在障壁金属焊盘18上形成凸块20来界定凸块区I。
可在半导体衬底11的第二表面F2上形成包括配线层24及层间绝缘层26的有源区ac。可在半导体衬底11的第二表面F2上的有源区ac中形成连接焊盘28及外部连接端子30。
图7是根据本发明一实施例的半导体芯片10g的部分剖视图。
详细来说，半导体芯片10g可与图6所示半导体芯片10f相同，只是半导体芯片10g包括具有重布线配线图案32及虚设图案34的重布线配线区III及虚设区IV。将省略或扼要地提供关于与图6所示半导体芯片10f的元件相同的元件的说明。
在图7中，示出包括重布线配线图案32及虚设图案34的重布线配线区III以及虚设区IV。然而，如果仅包括重布线配线图案32及虚设图案34中的一者，则半导体芯片10g可仅包括重布线配线区III以及虚设区IV中的一者。
半导体芯片10g可包括其中在半导体衬底11的第一表面F1上设置有凸块20的凸块区I。凸块区I可包括通孔16、凸块焊盘22以及障壁金属焊盘18。半导体芯片10g可包括其中在下部钝化层12上形成有重布线配线图案32及虚设图案34的重布线配线区III及虚设区IV。可形成多个重布线配线图案32及多个虚设图案34。
可在凸块区I的一侧处形成重布线配线区III及虚设区IV。上部钝化层14可被形成为覆盖凸块区I、重布线配线区III及虚设区IV以及非凸块区II中的半导体衬底11。上部钝化层14可被形成为覆盖下部钝化层12上的重布线配线图案32及虚设图案34。上部钝化层14可被划分成凸块区I中的上部钝化层14a-1、重布线配线区III及虚设区IV中的上部钝化层14a-3以及非凸块区II中的上部钝化层14b。
凸块区I中的上部钝化层14a-1可在x方向(水平方向)上从凸块20的一个侧壁延伸距离d4。凸块区I中的上部钝化层14a-1可在-x方向(水平方向)上从凸块20的另一侧壁延伸距离d4-2。重布线配线区III及虚设区IV中的上部钝化层14a-3可在-x方向(水平方向)上从凸块20的另一侧壁延伸距离d5。
凸块区I以及重布线配线区III及虚设区IV中上部钝化层14a-1及14a-3的厚度t1厚于非凸块区II中上部钝化层14b的厚度t2，且在重布线配线区III及虚设区IV与非凸块区II之间产生台阶sh4，并且在凸块区I与非凸块区II之间产生台阶sh2。
可通过以下方式来获得台阶sh2及sh4：在下部钝化层12上形成上部钝化材料层(图中未示出)，以及使用掩模(例如，相移掩模)对上部钝化材料层执行光刻。台阶sh2及sh4可与暴露出通孔16的介层孔ho3的形成同时地形成。台阶sh2及sh4可在z轴方向上被形成为垂直的，或可倾斜预定角度。
可在半导体衬底11的第二表面F2上形成包括配线层24及层间绝缘层26的有源区ac。可在半导体衬底11的第二表面F2上的有源区ac中形成连接焊盘28及外部连接端子30。
图8是根据本发明一实施例的半导体芯片10h的部分剖视图。
详细来说，半导体芯片10h可与图7所示半导体芯片10g相同，只是半导体芯片10h包括具有被暴露的重布线配线图案32及虚设图案34的重布线配线区III及虚设区IV以及在非凸块区II中具有凹陷部36的上部钝化层14b-2。因此，可省略或扼要地提供关于与图7所示半导体芯片10g的元件相同的元件的说明。
半导体芯片10h可包括其中在下部钝化层12上形成有重布线配线图案32及虚设图案34的重布线配线区III以及虚设区IV。上部钝化层14可形成在下部钝化层12上且覆盖半导体衬底11的凸块区I、重布线配线区III及虚设区IV以及非凸块区II。重布线配线区III及虚设区IV中的上部钝化层14a-3可凹陷以暴露出重布线配线图案32及虚设图案34。因此，在重布线配线区III及虚设区IV与凸块区I之间产生台阶sh5。
在非凸块区II中，可在上部钝化层14b-2中形成凹陷部36。非凸块区II中的凹陷部36可在形成重布线配线区III及虚设区IV中上部钝化层14a-3中的凹陷时形成。重布线配线区III及虚设区IV以及非凸块区II中上部钝化层14a-3及14b-2的厚度t5可薄于上部钝化层14a-1的厚度t1。另外，在凸块区I与非凸块区II之间形成有台阶sh2。台阶sh2可在z轴方向上被形成为垂直的，或可倾斜预定角度。
图9是根据本发明一实施例的半导体芯片10i的部分剖视图。
详细来说，半导体芯片10i可与图5所示半导体芯片10e相同，只是在半导体衬底11的第二表面F2上形成有凸块焊盘22、凸块20、及上部钝化层14，而不形成通孔。因此，可省略或扼要地提供关于与图5所示半导体芯片10e的元件相同的元件的说明。
半导体芯片10i可包括在半导体衬底11的第二表面F2上包括配线层24及层间绝缘层26的有源区ac。在半导体芯片10i中，在半导体衬底11的第二表面F2上，可在下部钝化层12上形成上部钝化层14。可在上部钝化层14中的孔ho5中形成凸块焊盘22。凸块焊盘22可连接至在半导体衬底11的第二表面F2上形成的芯片焊盘(图中未示出)。可通过在凸块焊盘22上形成凸块20而获得凸块区I。
上部钝化层14可形成在下部钝化层12上且覆盖半导体衬底11中的凸块区I及非凸块区II，但凸块焊盘22及凸块20除外。上部钝化层14可被划分成凸块区I中的上部钝化层14a及非凸块区II中的上部钝化层14b。
另外，凸块区I中上部钝化层14a的厚度t1厚于非凸块区II中上部钝化层14b的厚度t2，且在凸块区I与非凸块区II之间产生台阶sh2。台阶sh2可在z轴方向上被形成为垂直的，或可倾斜预定角度。
图10是根据本发明一实施例的半导体芯片10j的部分剖视图。
详细来说，半导体芯片10j可与图7所示半导体芯片10g相同，只是在半导体衬底11的第二表面F2上形成有凸块焊盘22、障壁金属焊盘18、凸块20、重布线配线图案32、虚设图案34及上部钝化层14，而不形成通孔。因此，可省略或扼要地提供关于与图7所示半导体芯片10g的元件相同的元件的说明。
半导体芯片10j可包括在半导体衬底11的第二表面F2上包括配线层24及层间绝缘层26的有源区ac。在半导体芯片10j中，在半导体衬底11的第二表面F2上，可在下部钝化层12上形成上部钝化层14。可在上部钝化层14中形成凸块焊盘22及障壁金属焊盘18。凸块焊盘22可连接至在半导体衬底11的第二表面F2上形成的芯片焊盘(图中未示出)。可通过在凸块焊盘22及障壁金属焊盘18上形成凸块20来界定凸块区I。
上部钝化层14可形成在下部钝化层12上且覆盖半导体衬底11中的凸块区I、非凸块区II以及重布线配线区III及虚设区IV，但凸块焊盘22、障壁金属焊盘18及凸块20除外。上部钝化层14可被划分成凸块区I中的上部钝化层14a-1、非凸块区II中的上部钝化层14b以及重布线配线区III及虚设区IV中的上部钝化层14a-3。
另外，凸块区I以及重布线配线区III及虚设区IV中上部钝化层14a-1及14a-3的厚度t1厚于非凸块区II中上部钝化层14b的厚度t2。在重布线配线区III及虚设区IV以及非凸块区II之间产生台阶sh4。在凸块区I与非凸块区II之间产生台阶sh2。台阶sh2及sh4可在z轴方向上被形成为垂直的，或可倾斜预定角度。
图11是根据本发明一实施例的半导体芯片10k的部分剖视图。
详细来说，半导体芯片10k可与图8所示半导体芯片10h相同，只是在半导体衬底11的第二表面F2上形成有凸块焊盘22、障壁金属焊盘18、凸块20、重布线配线图案32、虚设图案34及上部钝化层14，而不形成通孔。因此，可省略或扼要地提供关于与图8所示半导体芯片10h的元件相同的元件的说明。
半导体芯片10k可包括在半导体衬底11的第二表面F2上包括配线层24及层间绝缘层26的有源区ac。在半导体芯片10k中，在半导体衬底11的第二表面F2上，可在下部钝化层12上形成上部钝化层14。可在上部钝化层14中形成凸块焊盘22及障壁金属焊盘18。凸块焊盘22可连接至在半导体衬底11的第二表面F2上形成的芯片焊盘(图中未示出)。可通过在凸块焊盘22及障壁金属焊盘18上形成凸块20来界定凸块区I。
上部钝化层14可形成在下部钝化层12上且覆盖半导体衬底11中的凸块区I、非凸块区II以及重布线配线区III及虚设区IV，但凸块焊盘22、障壁金属焊盘18及凸块20除外。
上部钝化层14可被划分成凸块区I中的上部钝化层14a-1、非凸块区II中的上部钝化层14b-2以及重布线配线区III及虚设区IV中的上部钝化层14a-3。
凸块区I中上部钝化层14a-1的厚度t1可厚于非凸块区II以及重布线配线区III及虚设区IV中上部钝化层14b-2及14a-3的厚度t5。在凸块区I与重布线配线区III及虚设区IV之间产生台阶sh5。在凸块区I与非凸块区II之间产生台阶sh2。台阶sh2及sh5可在z轴方向上被形成为垂直的，或可倾斜预定角度。
图12及图13是部分地示出根据本发明概念实施例的半导体芯片40a及40b的平面图，其用于说明凸块的厚度与钝化层的厚度之间的关系。
详细来说，在图12及图13的部分平面图中所说明的半导体芯片40a及40b可包括在半导体衬底11上彼此间隔开的凸块20。凸块20可被配置成图12及图13所示的蜂窝形状。如果需要，则凸块20可在水平方向(x方向)及垂直方向(y方向)上对齐。
如上所述，形成凸块区I的上部钝化层14a可在凸块20周围形成。另外，形成非凸块区II的上部钝化层14b形成在除凸块区I之外的半导体衬底11上。
在图12所示半导体芯片40a中，环绕多个凸块20的上部钝化层14a的厚度被配置成厚于非凸块区II中上部钝化层14b的厚度。在图13所示半导体芯片40b中，仅环绕多个凸块20中的部分凸块20的上部钝化层14a的厚度被配置成厚于非凸块区II中上部钝化层14b的厚度。如上所述，可对半导体衬底11上环绕凸块20的钝化层的厚度进行自由调整以控制半导体芯片的翘曲。
图14是根据本发明一实施例的半导体芯片40c的部分平面图，其用于说明凸块的厚度与钝化层的厚度之间的关系。
详细来说，在图14的部分平面图中所说明的半导体芯片40c可包括在半导体衬底11上彼此间隔开的凸块20。半导体衬底11可被划分成在半导体衬底11的中心部分处形成的中心区42以及环绕中心区42且与中心区42分离的外围区44。隔离区41可位于中心区42与外围区44之间。
如上所述，形成凸块区I的上部钝化层14a可在凸块20周围形成。另外，形成非凸块区II的上部钝化层14b形成在除凸块区I之外的半导体衬底11上。
在图14所示部分平面图中，环绕在中心区42上形成的所有多个凸块20的上部钝化层14a的厚度厚于非凸块区II中上部钝化层14b的厚度。如果需要，如以上参考图13所说明，可仅将环绕在中心区42上形成的多个凸块20中的部分凸块20的上部钝化层14a的厚度配置成厚于非凸块区II中上部钝化层14b的厚度。
在图14所示部分平面图中，环绕在外围区44上形成的多个凸块的上部钝化层14b的厚度被配置成薄于凸块区I中上部钝化层14a的厚度。如上所述，通过自由地调整在半导体衬底11上环绕凸块20的上部钝化层14a及14b的厚度，可对半导体芯片的翘曲进行控制。
图15是根据本发明概念实施例的半导体芯片40d的部分平面图，其用于说明凸块的厚度与钝化层的厚度之间的关系。
详细来说，在图15的部分平面图中所说明的半导体芯片40d可包括在半导体衬底11上彼此间隔开的凸块20。半导体衬底11可被划分成从一侧朝另一侧分割开的多个子区60、62、64、66、68及70。
如上所述，形成凸块区I的上部钝化层14a可在凸块20周围形成。另外，形成非凸块区II的上部钝化层14b形成在除凸块区I之外的半导体衬底11上。
在图15所示部分平面图中，环绕在子区60、62、64、66、68及70中的至少一者上形成的多个凸块20中的部分凸块20的上部钝化层14a的厚度厚于非凸块区II中上部钝化层14b的厚度。如果需要，如以上参考图12所说明，环绕在子区60、62、64、66、68及70中的至少一者上形成的所有多个凸块20的上部钝化层14a的厚度可厚于非凸块区II中上部钝化层14b的厚度。
在图15所示部分平面图中，环绕在子区60、62、64、66、68及70中的至少一者上形成的多个凸块20的上部钝化层14b的厚度薄于凸块区I中上部钝化层14a的厚度。如上所述，通过自由地调整在半导体衬底11上环绕凸块20的上部钝化层14a及14b的厚度，可对半导体芯片的翘曲进行控制。
图16是根据实施例包括半导体芯片的半导体封装1000的剖视图，且图17是示出图16的一部分的部分放大图。
具体来说，图17是图16中的部分C的放大图。根据本发明一实施例的半导体封装1000可包括第一半导体芯片100、第二半导体芯片200及上部半导体芯片500。如上所述，第一半导体芯片100、第二半导体芯片200及上部半导体芯片500可各自包括包含凸块194a及194b的凸块区I、包括重布线配线图案196a及196b以及虚设图案197a及197b的重布线配线区III及虚设区IV、以及不包括凸块的非凸块区II。
第一半导体芯片100可包括穿透过第一半导体衬底102a的一个或多个第一通孔174a。第一通孔174a从第一半导体衬底102a的上表面突出，且第一通孔174a的侧表面可被在第一半导体衬底102a的上表面上形成的下部钝化层124a环绕。
第二半导体芯片200设置在第一半导体芯片100上。第二半导体芯片200可通过热压缩接合(thermo-compression bonding)工艺而接合至第一半导体芯片100。第二半导体芯片200包括一个或多个第二通孔174b，一个或多个第二通孔174b沿着与第一半导体芯片100中的第一通孔174a的垂直线相同的垂直线配置。第二通孔174b从第二半导体衬底102b的上表面突出，且第二通孔174b的侧表面可被在第二半导体衬底102b的上表面上形成的下部钝化层124b环绕。
可分别在第一半导体芯片100的第一通孔174a的上表面上以及在第二半导体芯片200的第二通孔174b的上表面上形成多个凸块焊盘192a及192b。凸块焊盘192a及192b可包含金属。可在第一半导体芯片100的上表面及第二半导体芯片200的上表面上形成高度与凸块焊盘192a及192b的高度相同的重布线配线图案196a及196b以及虚设图案197a及197b。重布线配线图案196a及196b以及虚设图案197a及197b可包含与凸块焊盘192a及192b相同的材料，例如，金属。
如在图17的放大图中所示，第一半导体芯片100的凸块焊盘192a、重布线配线图案196a及虚设图案197a可被上部钝化层178a隐埋或覆盖。与第一半导体芯片100一样，第二半导体芯片200的凸块焊盘192b、重布线配线图案196b及虚设图案197b可被第二上部钝化层178b覆盖或隐埋。
第一半导体芯片100的凸块区I以及重布线配线区III及虚设区IV中第一上部钝化层178a-1的厚度可厚于非凸块区II中第一上部钝化层178a-2的厚度。同样地，第二半导体芯片200的重布线配线区III及虚设区IV中第二上部钝化层178b的厚度可厚于非凸块区II中第二上部钝化层178b的厚度。
上部半导体芯片500设置在第二半导体芯片200上。上部半导体芯片500可通过热压缩接合工艺而接合至第二半导体芯片200。上部半导体芯片500的厚度可厚于第一半导体芯片100及第二半导体芯片200。
第二半导体芯片200经由在第二半导体芯片200的下表面上形成的连接焊盘170b及凸块194a以及在第一半导体芯片100的上表面上形成的凸块焊盘192a而电连接至第一半导体芯片100。上部半导体芯片500经由在上部半导体芯片500的下表面上形成的连接焊盘170c及凸块194b以及在第二半导体芯片200的上表面上形成的凸块焊盘192b而电连接至第二半导体芯片200。
第一半导体芯片100及第二半导体芯片200可为相同种类的半导体芯片。半导体封装1000可包含填充第一半导体芯片100与第二半导体芯片200之间的空间的第一底部填充材料198a。半导体封装1000可包含填充第二半导体芯片200与上部半导体芯片500之间的空间的第二底部填充材料198b。第一底部填充材料198a及第二底部填充材料198b可包含非导电材料，例如，非导电膜(non-conductive film，NCF)。
图18是图16所示半导体封装1000的部分放大剖视图。
详细来说，图18是图16所示第一半导体芯片100的部分放大剖视图。第一半导体芯片100可包括具有第一表面F1及第二表面F2的第一半导体衬底102a、下部层间绝缘层104、集成电路层150、第一通孔174a、上部层间绝缘层122、下部钝化层124a及多层式配线图案180。
集成电路层150可形成在第一半导体衬底102a的第一表面F1上。上面掺杂有杂质的掺杂区可形成在第一半导体衬底102a的上部区上，上部区相邻于其中形成有集成电路层150的第一表面F1。另一方面，第一半导体衬底102a的相邻于第二表面F2的下部区可为未掺杂区。
下部层间绝缘层104可形成在第一半导体衬底102a的第一表面F1之上同时覆盖集成电路层150。下部层间绝缘层104可使集成电路层150中的电路装置彼此隔离。另外，下部层间绝缘层104可使多层式配线图案180及集成电路层150中的电路装置彼此隔离。下部层间绝缘层104可具有包括选自氧化物层、氮化物层、低介电常数层及高介电常数层中的一者或多者的堆叠结构。
集成电路层150可在第一半导体衬底102a的第一表面F1上形成在下部层间绝缘层104中，且可包括多个电路装置。集成电路层150可根据第一半导体芯片100的种类而包括电路装置，例如晶体管及/或电容器。根据集成电路层150的结构，第一半导体芯片100及第二半导体芯片200可用作存储器装置或逻辑装置。
举例来说，存储器装置可包括动态随机存取存储器(dynamic random accessmemory，DRAM)、静态随机存取存储器(static RAM，SRAM)、闪速存储器、电可擦可编程只读存储器(electrically erasable and programmable read only memory，EEPROM)、相变随机存取存储器(PRAM)、磁阻式随机存取存储器(MRAM)或电阻式随机存取存储器(RRAM)。半导体装置的此种结构是所属领域公知的，且因此不会限制本发明的范围。此处，参考编号152可表示将集成电路层150中的电路装置电连接至以上配线图案的金属触点。
上部层间绝缘层122可设置在下部层间绝缘层104上以覆盖多层式配线图案180。上部层间绝缘层122可将第一配线线路181、第一垂直插塞183、第二配线线路185及第二垂直插塞187彼此分离。
下部钝化层124a可保护第一半导体芯片100的上表面。下部钝化层124a可包括氧化物层或氮化物层、或者包括氧化物层及氮化物层的双层。上部钝化层178a可形成在下部钝化层124a上。上部钝化层178a在包括凸块194a的凸块区中的厚度可为更厚，且在不包括凸块194a的非凸块区中的厚度可为更薄。
多层式配线图案180可形成在下部层间绝缘层104及上部层间绝缘层122中，且可电连接至第一通孔174a。多层式配线图案180可包括至少一层配线线路及连接配线线路的垂直触点。多层式配线图案180可用于通过恰当地连接集成电路层150中的电路装置来配置预定电路，或可用于将电路装置连接至外部产品。
在实施例中，可配置有三层配线线路，例如第一配线线路181、第二配线线路185及第三配线线路189，且可形成有将第一配线线路181连接至第二配线线路185的第一垂直插塞(plug)183以及将第二配线线路185连接至第三配线线路189的第二垂直插塞187。多层式配线图案180中的第一配线线路至第三配线线路181、185及189以及第一垂直插塞183及第二垂直插塞187可包含相同的材料(例如，铜或铝)，或可包含不同的材料。
图18所示第一半导体芯片100中的第一通孔174a可包括通孔绝缘层135、障壁金属层134及配线金属层132。障壁金属层134可包括具有选自钛(Ti)、钽(Ta)、氮化钛(TiN)及氮化钽(TaN)中的一者或多者的堆叠结构。
配线金属层132可包含选自以下中的一者或多者：铝(Al)、金(Au)、铍(Be)、铋(Bi)、钴(Co)、铜(Cu)、铪(Hf)、铟(In)、锰(Mn)、钼(Mo)、镍(Ni)、铅(Pb)、钯(Pd)、铂(Pt)、铑(Rh)、铼(Re)、钌(Ru)、钽(Ta)、碲(Te)、钛(Ti)、钨(W)、锌(Zn)及锆(Zr)。配线金属层132可具有包含选自钨(W)、铝(Al)及铜(Cu)中的一者或多者的堆叠结构。
第一通孔174a穿透过下部层间绝缘层104及上部层间绝缘层122、下部钝化层124a以及第一半导体衬底102a，且第一通孔174a的末端可从第一半导体衬底102a的第二表面F2暴露出。第一通孔174a可从第一半导体衬底102a的第二表面F2突出以易于连接至连接焊盘170a。
凸块焊盘192a及凸块194a可形成在第一通孔174a上。凸块194a可连接至第一通孔174a，且可连接至多层式配线图案180。保护层106可形成在第一半导体衬底102a的第二表面F2上以保护装置。
图19是根据本发明一实施例的包括半导体芯片的半导体封装1000-1的剖视图。
详细来说，根据实施例的半导体封装1000-1可与图16所示半导体封装1000相同，只是半导体封装1000-1安装在印刷电路板600上。在图19中，参考编号610可为粘合层。
半导体封装1000-1可包括安装在印刷电路板600上的第一半导体芯片至第四半导体芯片100、200、300及400以及上部半导体芯片500。由于第一半导体芯片100至第四半导体芯片400等同于参考图16至图18所说明的第一半导体芯片100及第二半导体芯片200，因此可省略或扼要地提供关于其的说明。上部半导体芯片500等同于图16所示上部半导体芯片500，且因此可省略其说明。
第一半导体芯片100可经由在其下表面上形成的连接焊盘170a且经由连接端子604及衬底焊盘606而电连接至印刷电路板600。外部连接端子608可形成在印刷电路板600的下表面上。
图20是根据实施例的包括半导体芯片的半导体封装1000-2的剖视图，且图21是示出图20的一部分的部分放大图。
详细来说，半导体封装1000-2可具有其中半导体芯片720经由凸块730而直接安装在印刷电路板700上的结构。半导体封装1000-2可选择性地包括填充半导体芯片720与印刷电路板700之间的空间的底部填充单元750。半导体封装1000-2可选择性地进一步包括封装单元(encapsulation unit)740及外部连接端子780，封装单元740用于封装在印刷电路板700上的半导体芯片720，外部连接端子780用于将半导体芯片720的功能扩展至印刷电路板700的下部部分之外。外部连接端子780可形成在衬底焊盘760上。
凸块730可表示导电突出部，导电突出部用于通过胶带自动接合(tape automatedbonding，TAB)工艺或倒装芯片接合(flip-chip bonding)工艺将半导体芯片720接合至印刷电路板700。凸块730可用作用于将球栅阵列(ball grid array，BGA)、芯片级封装(chipscale package，CSP)等直接连接至印刷电路板700的导电突出部。如果凸块730为焊料凸块，则凸块730可在回焊工艺之后因表面张力效应而维持球形状，但如果凸块730为金(Au)凸块，则凸块730可被形成为被镀敷的方形柱。凸块730可包含金属材料，例如焊料、金(Au)及铜(Cu)。
图21可为图20中的参考编号770的放大图。如图21所示，凸块730可形成在凸块焊盘726上，凸块焊盘726形成在半导体芯片720上的钝化层724中。钝化层724可被划分成包括凸块730及外围部分的凸块区中的钝化层724a以及不包括凸块730的非凸块区中的钝化层724b。
凸块区中的钝化层724a的厚度比非凸块区中的钝化层724b厚，且可在凸块区与非凸块区之间产生台阶。因此，通过减小除环绕凸块730的区之外的非凸块区中钝化层的厚度，可限制在半导体芯片720或半导体封装1000-2中产生翘曲。
图22是根据本发明概念实施例的包括半导体芯片的半导体封装1000-3的剖视图。
详细来说，图22所示半导体封装1000-3可为其中安装有多个图20所示半导体封装1000-2的层叠式封装(package-on-package，POP)类型的系统级封装(system-in-package，SIP)。因此，将省略或扼要地提供关于与图20及图21所示元件相同的元件的说明。
半导体封装1000-3可为其中第二半导体封装1000-2b堆叠在第一半导体封装1000-2a上的封装。第一半导体封装1000-2a可包括安装在第一印刷电路板700a上的第一半导体芯片720a。第二半导体封装1000-2b可包括安装在第二印刷电路板700b上的第二半导体芯片720b。第一半导体芯片720a及第二半导体芯片720b可经由凸块730分别连接至第一印刷电路板700a及第二印刷电路板700b。凸块730形成在第一半导体芯片720a及第二半导体芯片720b上，且具有与图21所示横截面相同的横截面，并且因此省略其说明。
第二半导体封装1000-2b可经由在第二印刷电路板700b的下表面上形成的下部连接焊盘760b及连接端子780b而连接至第一印刷电路板700a的上部连接焊盘765。第一半导体封装1000-2a可经由在第一印刷电路板700a的下表面上形成的下部连接焊盘760a及连接端子780a而连接至外部装置。
尽管已参考本发明的实施例具体示出及阐述了本发明，但应理解，在不背离以上权利要求书的精神及范围的条件下可作出各种形式及细节上的改变。

Claims (18)

1.一种半导体芯片，其特征在于，包括：
半导体衬底，包括凸块区、非凸块区及位于所述凸块区与所述非凸块区之间的虚设区；
虚设图案，位于所述虚设区上；
凸块焊盘，位于所述凸块区上；
障壁金属焊盘，位于所述凸块区上所述凸块焊盘上；
凸块，位于所述凸块区上所述障壁金属焊盘上，所述非凸块区不具有凸块；
上部钝化层，位于所述半导体衬底的所述凸块区、所述虚设区及所述非凸块区上；以及
下部钝化层，位于所述上部钝化层之下，
其中所述虚设图案位于所述下部钝化层与所述上部钝化层之间，
所述上部钝化层是单层，包括具有第一厚度的第一部分和具有小于所述第一厚度的第二厚度的第二部分，所述上部钝化层的所述第一部分位于所述凸块区与所述虚设区，
所述上部钝化层的所述第二部分位于所述非凸块区，
所述上部钝化层覆盖所述虚设图案且绝缘所述虚设图案，
所述上部钝化层包括位于所述凸块区与所述非凸块区之间的台阶，所述台阶通过位于在所述虚设区及所述非凸块区之间的边界上面的所述上部钝化层的所述第一部分的上表面与所述上部钝化层的所述第二部分的上表面来界定，
所述障壁金属焊盘的上表面和所述上部钝化层的所述第一部分的所述上表面彼此共面并且所述障壁金属焊盘的侧壁和所述凸块焊盘的侧壁彼此对齐。
2.根据权利要求1所述的半导体芯片，其特征在于，所述上部钝化层包括氧化物层、氮化物层或感光性有机层中的一者。
3.根据权利要求1所述的半导体芯片，其特征在于，所述凸块区在水平方向上从所述凸块的相对的侧壁延伸一距离。
4.根据权利要求1所述的半导体芯片，其特征在于，所述上部钝化层包括位于所述非凸块区中的凹陷部。
5.根据权利要求1所述的半导体芯片，其特征在于，所述半导体衬底包括第一表面及与所述第一表面相对的第二表面，且所述半导体衬底的所述第一表面或所述第二表面中的一者包括有源区。
6.根据权利要求5所述的半导体芯片，其特征在于，还包括：
连接至所述半导体衬底的所述第二表面的连接焊盘，其中
所述凸块及所述上部钝化层位于所述半导体衬底的所述第一表面上。
7.根据权利要求5所述的半导体芯片，其特征在于，所述凸块及所述上部钝化层连接至所述半导体衬底的所述第二表面。
8.根据权利要求1所述的半导体芯片，其特征在于，还包括：
位于所述半导体衬底的所述凸块区上的彼此间隔开的多个凸块，其中
所述多个凸块包括所述凸块，且
环绕所述多个凸块中的部分凸块的所述上部钝化层的厚度厚于所述非凸块区中所述上部钝化层的厚度。
9.根据权利要求1所述的半导体芯片，其特征在于，还包括：
位于所述半导体衬底的所述凸块区上的彼此间隔开的多个凸块，其中
所述半导体衬底包括中心区及与所述中心区隔离且环绕所述中心区的外围区，且
环绕在所述中心区中形成的所述多个凸块中的部分或所有凸块的所述上部钝化层的厚度厚于所述非凸块区中所述上部钝化层的厚度。
10.根据权利要求1所述的半导体芯片，其特征在于，还包括：
位于所述半导体衬底的所述凸块区上的彼此间隔开的多个凸块，其中
所述半导体衬底的所述上表面包括在从所述半导体衬底的第一侧到第二侧的方向上彼此隔离的多个子区，且
在所述多个子区中的至少一个子区中环绕所述多个凸块中的部分或所有凸块的所述上部钝化层的厚度厚于所述非凸块区中所述上部钝化层的厚度。
11.一种半导体芯片，其特征在于，包括：
半导体衬底，包括其中配置有通孔及凸块的凸块区及不包括凸块的非凸块区；
重布线配线区，具有位于所述半导体衬底的第一表面或第二表面上的至少一个重布线配线图案；
凸块焊盘，位于所述凸块区上；
障壁金属焊盘，位于所述凸块区上所述凸块焊盘上，所述凸块位于所述障壁金属焊盘上；
上部钝化层，位于所述半导体衬底中的所述凸块区、所述重布线配线区及所述非凸块区上；以及
下部钝化层，位于所述上部钝化层之下，
其中所述重布线配线区位于所述下部钝化层与所述上部钝化层之间，
所述上部钝化层是单层，包括具有第一厚度的第一部分和具有小于所述第一厚度的第二厚度的第二部分，
所述上部钝化层的所述第一部分位于所述凸块区及所述重布线配线区中，
所述上部钝化层的所述第二部分位于所述非凸块区中，
在所述凸块区与所述非凸块区之间及所述重布线配线区与所述非凸块区之间具有台阶，
所述障壁金属焊盘的上表面和所述上部钝化层的所述第一部分的上表面彼此共面并且所述障壁金属焊盘的侧壁和所述凸块焊盘的侧壁彼此对齐。
12.根据权利要求11所述的半导体芯片，其特征在于，所述凸块区包括穿透过所述半导体衬底的至少一个通孔，所述凸块焊盘、所述障壁金属焊盘及所述凸块依次设置于所述通孔上。
13.根据权利要求12所述的半导体芯片，其特征在于，形成有多个所述通孔，且所述凸块焊盘位于所述多个通孔中的每一通孔上。
14.一种半导体芯片，其特征在于，包括：
半导体衬底，具有第一表面及与所述第一表面相对的第二表面，且包括其中在所述第一表面上设置有凸块焊盘及凸块的凸块区及不具有凸块的非凸块区；
重布线配线区及虚设区，在所述半导体衬底的所述第一表面或所述第二表面上具有重布线配线图案及虚设图案中的至少一者；以及
障壁金属焊盘，位于所述凸块区上所述凸块焊盘上，所述凸块位于所述障壁金属焊盘上；
上部钝化层，被配置成在所述半导体衬底的所述第一表面或所述第二表面上覆盖所述凸块区、所述非凸块区、所述重布线配线区及所述虚设区；以及
下部钝化层，位于所述上部钝化层之下，
其中所述重布线配线区及虚设区位于所述下部钝化层与所述上部钝化层之间，
所述上部钝化层是单层，包括具有第一厚度的第一部分和具有小于所述第一厚度的第二厚度的第二部分，
所述上部钝化层的所述第一部分位于所述凸块区及所述重布线配线区及所述虚设区中，
所述上部钝化层的所述第二部分位于所述非凸块区中，
在所述凸块区与所述非凸块区之间具有第一台阶,
所述障壁金属焊盘的上表面和所述上部钝化层的所述第一部分的上表面彼此共面并且所述障壁金属焊盘的侧壁和所述凸块焊盘的侧壁彼此对齐。
15.根据权利要求14所述的半导体芯片，其特征在于，所述重布线配线图案及所述虚设图案具有与所述凸块焊盘的厚度相等的厚度，且所述重布线配线图案及所述虚设图案被所述上部钝化层覆盖。
16.根据权利要求14所述的半导体芯片，其特征在于，在所述重布线配线区及所述虚设区与所述非凸块区之间具有第二台阶。
17.根据权利要求14所述的半导体芯片，其特征在于，所述重布线配线区及所述虚设区被形成为接触所述凸块区。
18.根据权利要求14所述的半导体芯片，其特征在于，在所述非凸块区的所述上部钝化层中具有凹陷部。
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