CN102148210A - 半导体器件及其制造方法 - Google Patents
半导体器件及其制造方法 Download PDFInfo
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- CN102148210A CN102148210A CN2010106209883A CN201010620988A CN102148210A CN 102148210 A CN102148210 A CN 102148210A CN 2010106209883 A CN2010106209883 A CN 2010106209883A CN 201010620988 A CN201010620988 A CN 201010620988A CN 102148210 A CN102148210 A CN 102148210A
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- insulating barrier
- conductive layer
- layer
- semiconductor device
- wirings
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Abstract
一种半导体器件及其制造方法,该半导体器件包括:集成电路,具有电极焊盘;第一绝缘层,被设置在集成电路上;再分布层,包括多个布线并被设置在第一绝缘层上,所述多个布线的至少一个被电耦接到电极焊盘;第二绝缘层,在多个布线的至少一部分上具有开口;金属膜,被设置在开口上和第二绝缘层上,并且该金属膜被电耦接到所述多个布线中的至少一个;以及焊接凸点,悬于没有被电耦接到金属膜的多个布线的至少一个之上。本发明减少了第二绝缘树脂层与再分布布线的脱离,并确保了再分布布线的粘附力。
Description
相关申请的交叉参考
本申请要求2009年12月25日提交的日本专利申请No.2009-294180的优先权,其全部内容通过参考合并于此。
技术领域
本文所讨论的实施例涉及一种半导体器件及制造该半导体器件的方法。
背景技术
用于在晶片状态中形成再分布(redistribution)布线和端子的晶片级封装(WLP)技术可被应用于安装在半导体器件上的倒装芯片,该半导体器件包括排列成阵列的多个突出端子。
相关技术例如在日本特开专利公开2002-198374以及2008-135486中公开。
为了增加外部连接端子的个数,图1中示出的第二连接盘部140b的直径被减小。在UBM膜之下的一定间隔(该间隔通过减小该第二连接盘140b的直径而形成)内设置未连接至UBM膜的再分布布线140。然而,在形成再分布布线140的过程中,在用以形成焊接凸点155的回流的冷却操作中,UBM膜150可能会收缩,且该第二绝缘树脂层132可能被所述收缩牵引,因此该第二绝缘树脂层132会从再分布布线140脱离。
这就降低了半导体的布线部中的可靠性。
发明内容
为克服现有技术的缺陷,根据实施例的一个方面,一种半导体器件,包括:集成电路,包括电极焊盘;第一绝缘层,被设置在该集成电路上;再分布层,包括多个布线并被设置在第一绝缘层上,所述多个布线的至少一个被电耦接到电极焊盘;第二绝缘层,在多个布线的至少一部分上具有开口;金属膜,被设置在开口上和第二绝缘层上,并且该金属膜被电耦接到所述多个布线的至少一个;以及焊接凸点,悬于没有被电耦接到该金属膜的多个布线的至少之一上。
本发明减少了第二绝缘树脂层与再分布布线的脱离,并确保了再分布布线的粘附力。
本发明的其他优点和新颖性特征将在下方的说明中部分体现,并且对本领域的技术人员来说,通过对下文的研究或通过对本发明实践的学习,部分其他优点和新颖性特征将变得更加明显。
附图说明
图1A和图1B示出示例性半导体器件;
图2A和图2B示出示例性半导体器件;
图3A至图3C示出制造半导体器件的示例性方法;
图4A至图4C示出制造半导体器件的示例性方法;
图5A至图5C示出制造半导体器件的示例性方法;
图6A和图6B示出制造半导体器件的示例性方法;以及
图7A和图7B示出制造半导体器件的示例性方法。
具体实施方式
图1A和图1B示出示例性半导体器件。该半导体器件可具有WLP结构。如图1A的剖视图所示,该半导体器件100包括半导体衬底120(例如是硅(Si)晶片)。半导体衬底120包括大规模集成(LSI)电路的晶体管。在半导体衬底120上形成LSI端子121和例如由氮化硅(SiN)制成的绝缘层122。绝缘层122在与LSI端子121对齐的位置处有开口。在绝缘层122上(其在与LSI端子121对齐的位置处有开口)形成第一绝缘树脂层131。在第一绝缘树脂层131上形成包含铜(Cu)的再分布布线140,并形成用Cu填充的导体通路135。在第一绝缘树脂层131和再分布布线140上形成第二绝缘树脂层132。第二绝缘树脂层132包括在该半导体器件100的外部连接端子的形成位置用来暴露再分布布线140的开口。焊接凸点155或者外部连接端子可通过开口电耦接到再分布布线140。每个焊接凸点155可通过作为阻挡金属等的凸点下金属膜(UBM膜)150电耦接到再分布布线140。LSI端子121通过该再分布布线140电耦接到该焊接凸点155。
图1B示出半导体器件100的再分布布线140和焊接凸点155的示例性布局。图1B可示出图1A所示的半导体衬底120、再分布布线140以及焊接凸点155。
再分布布线140使形成于半导体衬底120表面上的外围区域处的许多LSI端子121中的每一个均与分布在半导体器件100顶部的至少一个焊接凸点155耦接。因此,对应于位于顶面中心附近的焊接凸点155的再分布布线140可包括:覆盖LSI端子121的第一连接盘(land)部140a,以及位于焊接凸点155下方的第二连接盘部140b,以及在第一和第二连接盘部140a和140b之间延伸的布线部140c。布线部140c将位于中心附近的焊接凸点155下方的第二连接盘部140b耦接到设置于外部区域的第一连接盘部140a,可规划该布线部140c的路径(route)以便在其他再分布布线140的第二连接盘部140b之间通过。
图1B所示的外部连接端子155的数量可以是5×5=25个钉。外部连接端子的数量可以是400个钉或其他数字。表示布线部140c的宽度和布线部之间的间隙(interval)的总值的布线间距(pitch)可以被缩小,并且许多布线部140c可被设置于两个相邻的连接盘部140b之间。布线间距因为设计规则而只能缩小到某个总值。
第二连接盘部140b的直径可以被缩小。在UBM膜下方隔开一定间隙提供没有连接到UBM膜的再分布布线140,该间隙是通过减少第二连接盘部140b的直径而形成的。许多再分布布线140可被设置于两个相邻的第二连接盘部140b之间。
UBM膜150可在回流(reflow)的冷却操作中收缩以形成焊接凸点155,并且第二绝缘树脂层132受所述收缩的牵引,因此而与再分布布线140分层。
图中所示的元件可不以同等比例尺显示。
图2A和图2B示出示例性半导体器件。图2A示出该半导体器件10的一部分的上表面。图2B示出沿着图2A所示的B-B′线的剖面。
半导体器件10包括半导体衬底20、第一绝缘层31、第二绝缘层32、穿过绝缘层31的导体通路35、再分布层40、包括凸点下金属(UBM)膜50的金属层和焊接凸点55。在图2A中可省略该半导体器件10的其他元件。
该半导体衬底20可包括:Si晶片或SOI(绝缘体上硅)晶片,以及靠近其表面的半导体集成电路(例如LSI电路)。该半导体衬底可包括半导体晶片和布线结构,该布线结构包括集成电路和形成于该半导体晶片上的多层布线。集成电路的电极焊盘21和顶部绝缘保护层22形成于半导体衬底20的表面处。电极焊盘21可包括金属(例如铝(Al)),并且绝缘保护层22可包括无机化合物(例如氮化硅(SiN))。绝缘保护层22包括用于暴露电极焊盘21的开口。虽然图2B示出的是一个电极焊盘21,但在半导体衬底20的表面上也可形成多个电极焊盘21。电极焊盘21可沿着半导体衬底20的边缘设置,就像图1B所示的再分布布线的第一连接盘部140a。一些电极焊盘21可被设置在半导体衬底20的中心区中,或者被排列在另一布局中。
焊接凸点55可以是半导体器件10的外部连接端子。焊接凸点55可通过倒装安装耦接至电子装置母板的电路板的连接焊盘。当半导体器件10以叠片方式(chip-on-chip manner)安装在不同的半导体器件上时,焊接凸点55可被耦接至不同半导体器件的连接焊盘。虽然图2A和图2B示出的是两个焊接凸点55,在半导体器件10上也可将许多焊接凸点55排列成阵列。焊接凸点55可包括焊接材料(例如为Sn-Ag、Sn-Cu或Sn-Ag-Cu)。
当两个半导体器件以叠片方式安装时,其中一个半导体器件可以是半导体器件10,另一个可以是没有焊接凸点55的不同的半导体器件。
再分布层40包括将各自的电极焊盘21耦接至对应的焊接凸点55的多个再分布布线。再分布层40的再分布布线用附图标记40表示。再分布布线可将两个或更多的电极焊盘耦接至一个焊接凸点,或可将一个电极焊盘耦接至两个或更多的焊接凸点。再分布布线40包括:耦接至集成电路的电极焊盘21的第一连接盘部40a、耦接至焊接凸点55的第二连接盘部40b、以及将第一连接盘部40a耦接至第二连接盘部40b的布线部40c。
再分布层40被设置于第一绝缘层31和第二绝缘层32之间。第一连接盘部40a通过形成于第一绝缘层31的开口中的导体通路35电耦接到集成电路的电极焊盘21。第二连接盘部40b通过形成于第二绝缘层32的开口中的金属(UBM)膜50电耦接到焊接凸点55。
UBM膜50可包括设置于焊接凸点55和再分布层40之间的接合部处的阻挡金属。由于UBM膜50从第二绝缘层32中的开口内围绕开口延伸至第二绝缘层32的表面,焊接凸点55的直径可大于开口的直径。焊接凸点55可通过UBM膜50耦接至比凸点55的直径小的第二连接盘部40b。耦接至焊接凸点55的第二连接盘部40b的尺寸被减小,用于让没有耦接至凸点55的再分布布线40(例如布线部40c)通过的间隔(space)可形成于UBM膜50和焊接凸点55之下。
例如,可以300μm的间距排列焊接凸点55和UBM膜50,UBM膜50的直径可为150μm,可以30μm(L/S=15μm/15μm)的间距排列再分布布线40。当第二连接盘部40b的直径与UBM膜50的直径大体相同时(例如,大约为150μm),在UBM膜50下方可不设置其他的再分布布线40。可在两个相邻的第二连接盘部40b之间在大约150μm的间隔内设置其他四个再分布布线40。例如,当第二连接盘部40b的直径为100μm时,因为第二连接盘部40b利用小于或等于第二连接盘部40b的直径的接合部而耦接至UBM膜50,可在两个相邻的第二连接盘部40b之间在200μm的间隔内设置六个再分布布线40。
由于多个再分布布线40被设置在单个UBM膜50或焊接凸点55之下,例如,单个焊接凸点55悬于多个再分布布线40之上,因此可增加许多行和列的焊接凸点。
图2A和图2B所示的两个UBM膜50和焊接凸点55悬于多个再分布布线40之上。根据LSI端子和焊接凸点的布局或UBM膜和焊接凸点的位置,半导体器件的一些UBM膜和焊接凸点可不悬于未与它们耦接的再分布布线之上。
再分布层40可包括形成在第一绝缘层31上的第一导电层41以及形成在第一导电层41上的第二导电层42。例如,第二导电层42可包括Cu,其是具有低电阻率的金属,并且该第二导电层42可通过电镀而形成以便具有1至7μm的厚度。第一导电层41可包括充当Cu扩散阻挡层(barrier)的金属,或包括增强再分布布线40与第一绝缘层31的粘附力(adhesion)的金属。例如,第一导电层41可包括钛(Ti)或铬(Cr),并通过溅镀而形成以便具有0.1到0.5μm的厚度。第一导电层41例如可包括具有0.1μm厚度的Cu层,并通过溅镀而形成于Ti或Cr层上。通过溅镀形成的Cu层比镀Cu具有更高的对Ti或Cr层的粘附力。第一导电层41可通过其他方法(例如化学气相沉积(CVD)法)而形成。
在第二导电层42与第二绝缘层32的全部或部分接合部表面处,第二导电层42的中心线平均表面粗糙度(Ra)大约为100nm或以上(例如为大约150nm或200nm)。表1和表2表示表面粗糙度Ra约为100nm的第二导电层42与表面粗糙度Ra约为40nm的第二导电层42之间的对比。例如,在形成焊接凸点55后,在完成该半导体器件10并在布线板上安装该器件之后,所观察到的与第二导电层分层时的剖面如表1所示,而对粘附力的测量则如表2所示。表1表示在测试了20个样品的情形下出现分层的样品的数量。表2表示五个样品的平均粘附力。如表1和表2所示,在形成焊接凸点之后,当表面平均粗糙度Ra处在40到100nm范围内时,不会发生分层,并且获得约1.7N的平均粘附力。例如,40nm或以上的表面粗糙度Ra确保了半导体器件10的再分布布线的粘附力。在通过回流而将样品安装在布线板上之后,分层发生在表面粗糙度Ra为40nm的三个样品中,它们的平均粘附力减少到约1.2N。表面粗糙度Ra为100nm的样品没有产生分层,并且确保了约为1.6N的足够的平均粘附力。
表1
表面粗糙度 | 凸点形成后出现分层 | 安装在板上后出现分层 |
40nm | 0/20 | 3/20 |
100nm | 0/20 | 0/20 |
表2
表面粗糙度 | 凸点形成后的粘附力 | 安装在板上后的粘附力 |
40nm | 1.67N | 1.13N |
100nm | 1.72N | 1.61N |
在安装于布线板上之后,通过形成中心线平均表面粗糙度Ra为100nm或以上的第二导电层42,在再分布布线40与第二绝缘层32之间产生锚固效应,用以减少再分布布线40与第二绝缘层32之间的分层的发生。从减少第二绝缘层32中的电介质击穿或裂纹的角度来看,中心线平均表面粗糙度Ra可为100nm或以上,并且可为500nm或以下。
在再分布层40中,第一导电层41的图案部比第二导电层42的图案部小。因此,在第二导电层下方以这种方式形成底切区44,即,第一导电层41的图案部的侧面朝向第二导电层42的图案部的内侧缩进(retreat)。因此,用于形成第二绝缘层32的绝缘材料流入底切区,从而增强了再分布布线40和第二绝缘层32之间的锚固效应。例如,可形成缩进量约为2μm的底切区44。这样的缩进可增强锚固效应以减少层之间的分层的发生。
例如,按照从第二绝缘层32到焊接凸点55的顺序,UBM膜50可包括第一导电层51、第二导电层52和第三导电层53。UBM膜50的第一导电层51可包括具有高阻挡特性和对第二绝缘层32的高粘附力的金属(例如Ti或Cr),并例如通过溅镀形成0.1到0.5μm的厚度。第二导电层52包括具有对第一导电层51的高粘附力的金属(例如Cu),并且例如通过溅镀或CVD方法形成0.1到0.5μm的厚度。第一导电层51和第二导电层52可包括与再分布层40的第一导电层41大体相同的材料。UBM膜50的第三导电层53可包括对焊接凸点55的焊料具有高润湿性(wettability)的金属(例如Ni),并且例如通过电镀形成1到5μm的厚度。
如果第三导电层53包括Ni层,可形成包括有1μm或以上的厚度的Cu层的第二导电层52。Cu层有比较高的弹性模量(Young′s modulus)。因此,通过形成具有1μm或以上的厚度的第二导电层52,由Ni材质的第三导电层53等的再结晶导致的收缩应力可被第二导电层52的变形吸收。第三导电层53可包括通过电镀形成的Cu涂层,以减少Ni层的再结晶效应。
例如,第一绝缘层31的厚度可以是2到7μm,而第二绝缘层32的厚度取决于再分布层40的厚度,并且例如可以是3到10μm。在再分布布线40上方的第二绝缘层32的厚度可为3μm或以上。由于UBM膜50被设置得与再分布布线40隔开3μm或以上的距离(再分布布线40位于UMB膜50之下并且不与UMB膜50耦接),UBM膜50与再分布布线40之间的电气短路得以减少。由于第二绝缘层32的厚度为3μm或以上,在第二绝缘层32中由UBM膜50和/或焊接凸点55的热收缩引起的应力可被减小,从而降低了施加于第二绝缘层32与再分布布线40之间的界面上的应力。
第一绝缘层31和第二绝缘层32可包括同样的材料或不同的材料。第一绝缘层31和第二绝缘层32可包括绝缘树脂,例如聚酰亚胺或酚树脂。
第二绝缘层32可包括在300℃或以下(例如200℃)固化的绝缘树脂。第二绝缘层32也可包括在低温下固化的树脂。由于这种第二绝缘层32可在低温下固化,可以减小可由固化第二绝缘层32引起的并留在第二绝缘层32与再分布布线40之间的膨胀应力或收缩应力。因而,第二绝缘树脂层32与再分布层40之间的分层可被减少。而且,由于第二绝缘层32在低温下固化,可由固化引起的第二绝缘树脂层32的厚度缩小可被减小。因此,再分布布线40边缘处的第二绝缘层32的电气短路和裂纹可被减少。在低温下固化的绝缘树脂可包括酚树脂。例如,从JSR(日本合成橡胶公司)可获得的WPR系列在200℃或以下固化。第二绝缘层32可包括复合材料,该复合材料包括酚树脂和弹性材料(例如橡胶材料)。这样的第二绝缘层32可以很好地吸收应力并且可减小施加于第二绝缘层32与再分布布线40之间的界面上的应力。
第二绝缘层32可包括对Cu具有高粘附力的聚酰亚胺。
图3A至图5C示出半导体器件的制造过程。图2所示的半导体器件10可在图3A至图5C所示的制造过程中加以制造。
如图3A所示,在半导体衬底20的表面上形成具有开口26(电极焊盘21暴露于该开口26)的绝缘保护层22。在半导体衬底20中,形成半导体集成电路(例如LSI电路)。在半导体衬底12的顶部形成电极焊盘21,并且例如该电极焊盘2可包括Al。绝缘保护层22可包括无机材料(例如SiN),并且形成于半导体衬底20的表面上,以具有例如5μm的厚度。在绝缘保护层22中通过光刻法形成开口26。
转到图3B,形成在电极焊盘21上具有开口36的第一绝缘层31,并且在第一绝缘层31上且在开口36中形成导电层41′。例如,通过旋涂法形成包括绝缘材料(例如聚酰亚胺或酚树脂)的绝缘层31,并且通过光刻法形成开口36。做为选择,也可通过印刷形成具有开口36的第一绝缘层31。例如,通过溅镀形成厚度为0.1到0.5μm的Ti或Cr层,从而形成导电层41′,并且随后通过溅镀形成厚度为0.1μm的Cu层。这种多层导电层41′可增强对下方第一绝缘层31和形成于下方第一绝缘层31上的涂层的粘附力。此操作可通过CVD法而不是溅镀法进行。
转到图3C,形成抗蚀剂图案46,然后,通过电镀形成例如5μm厚度的Cu层42。可采用周期脉冲反向(PPR)方法以改善涂层42的表面控制。可将添加剂添加到电镀液(plating bath)以使Cu涂层42的表面变粗糙。例如,可将氯(Cl)和/或聚丙烯酰胺(PAA)添加到硫酸铜水溶液。表3示出用于PPR方法的示例性配方。
表3
电镀液成分 | 标准 | 适当的范围 |
硫酸铜五水合物 | 90g/L | 50-130g/L |
通过将添加剂含量(additive content)控制到合理范围,Cu涂层42的中心线平均表面粗糙度Ra可被控制到100nm或以上(例如150nm或200nm)。表面粗糙度Ra为100nm或以上的Cu涂层42可减少第二绝缘层与Cu涂层42的分层(锚固效应)。
转到图4A,去除抗蚀剂图案46,然后用Cu涂层42作为掩模来蚀刻导电层41′。形成包括第一导电层41、第二导电层42的多个再分布布线40和导体通路35,所述导体通路35将再分布布线40(第一连接盘部40a)耦接至电极焊盘21。例如,如果导电层41′包括Ti层和Cu层,该Cu层可用包括醋酸或氨和过氧化氢的蚀刻剂(etchant)来蚀刻,而Ti层可用氢氟酸来蚀刻。至少Ti层可被过蚀刻,从而形成底切区44(该Ti层41朝向Cu涂层42的图案的内部方向缩进。底切区44的宽度(例如Ti层41相对于Cu涂层42的图案的缩进量)可以是2μm。底切区44可减少第二绝缘层与再分布布线40的分层(锚固效应)。
除了包括(或取代)对电镀液中的添加剂含量加以控制之外,Cu涂层42的粗糙化处理还可包括其他化学处理。例如,在去除抗蚀剂图案46之后实施的化学处理可增加Cu涂层的表面粗糙度Ra。
转到图4B,形成在再分布布线40的第二连接盘部40b上具有开口37的第二绝缘层32。例如,通过旋涂法形成第二绝缘层32,该第二绝缘层32包括与第一绝缘层31大体相同的绝缘树脂(例如聚酰亚胺或酚树脂),随后通过光刻法形成开口37。第二绝缘层32覆盖再分布布线40的部分可具有3μm或以上的厚度。例如,如果再分布布线40包括通过溅镀形成的厚度为0.1到0.5μm的Ti层或Cr层,则还可以形成厚度为0.1μm的Cr层(仍由溅镀形成)、厚度为5μm的Cu涂层(由电镀形成)、以及厚度为10μm的第二绝缘层32。第二绝缘层32可包括在300℃或以下(例如200℃或以下)的温度下固化的绝缘树脂,以便减轻第二绝缘层32的残余应力或厚度的缩小。
如图4C所示,在第二绝缘层32固化后,形成导电层51′和52′。导电层51′和52′分别包括通过溅镀形成的Ti或Cr层和Cu层,与再分布布线40的第一导电层41的层相似。当在导电层52′上方形成Ni层时,导电层52′可包括厚度为1μm或以上的Cu层,以吸收Ni层的收缩应力。
转到图5A,在形成抗蚀剂图案56后,通过电镀形成导电层53和焊料部55′。导电层53′可包括Ni层。导电层53′可包括取代Ni层的Cu层,以便降低第二绝缘层32上的导电层53′的热收缩的影响。
转到图5B,在去除抗蚀剂图案56之后,通过蚀刻去除所暴露的导电层52′和所暴露的导电层51′。因此形成包括导电层51、52和53的UBM膜50。
转到图5C,焊料部55′回流成为焊接凸点55。因此形成图2所示的半导体器件10。
图5A所示的焊料部55′的形成和图5C所示的回流可被省略。可制造出这样的半导体器件,该半导体器件包括将要以叠片方式耦接到另一半导体器件的焊接凸点的外部连接焊盘。
图6A、图6B、图7A和图7B示出用于制造半导体器件的示例性方法。在图6A至图7B中可省略与图2A和图2B所示的半导体器件10的元件相同或相似的元件的描述。
图6A示出半导体器件10′的部分上表面。图6B示出沿着图6A所示的B-B′线截取的剖面。
半导体器件10′包括UBM膜60和焊接凸点65,与图2A和图2B所示的半导体器件10相比,所述焊接凸点65悬于更多的再分布布线40之上。在UBM膜60和焊接凸点65下方、没有电耦接到UBM膜或焊接凸点的再分布布线40的数量可以是任意的。每个UBM膜60包括第一、第二和第三导电层61、62和63。导电层61、62和63可包括分别与半导体器件10的导电层51、52和53的材料相似或大体相同的材料。
在图6A和图6B中,UBM膜60和焊接凸点65可被表示为具有比图2A和图2B所示的半导体器件10的UBM膜50和焊接凸点55更大的直径。半导体器件10′的UBM膜60和焊接凸点65也可比图2A和图2B所示的半导体器件10的UBM膜和焊接凸点更小或大体相等。半导体器件10′的再分布布线以比图2A和图2B所示的半导体器件10的再分布布线的间距更小或大体相等的间距而被排列。
图7A示出半导体器件10″的部分上表面。图7B示出沿着图7A所示的B-B′线截取的剖面。
半导体器件10″包括UBM膜70以取代图2A和图2B所示的半导体器件10的UBM膜50。每个UBM膜70包括分别与半导体器件10的导电层51、52和53相似或大体相同的材料的第一、第二和第三导电层71、72和73。在UBM膜70与再分布布线40的第二连接盘部40b的各个接合部处,半导体器件10″可包括非焊料掩模限定(non-solder mask defined,NSMD)焊盘(其将要用于布线板)。例如,可在第二绝缘层32中形成用于设置外部连接端子的开口,以便覆盖再分布布线40的第二连接盘部40b和第一绝缘层31的没有被第二连接盘部40b覆盖的相邻部。例如,可形成开口以暴露第二连接盘部40b的至少一个侧面。UBM膜70耦接至第二连接盘部40b的至少一个侧面。
当第二连接盘部40b的尺寸被缩小时,可增强第二连接盘部40b与UBM膜70之间的粘附力。当第二连接盘部40b的尺寸被进一步缩小时,例如,当第二连接盘部40b的直径或宽度缩小到与布线部40c的宽度大体相同时,在UBM膜70下方可提供其中设置另一个再分布布线40的空间。
在图7B中,UBM膜70的第二和第三导电层72和73的形状可被维持为与图2B所示的UBM膜50的导电层相同,而UBM层70最底层的导电层71的形状被改变。UBM膜70的每个导电层可形成为任何形状。例如,根据再分布布线40的第二连接盘部40b的宽度或直径或根据形成于第二绝缘层32中的开口的直径,可以选择第二导电层72、第三导电层73和焊接凸点55的形状。
根据上述的优点,描述了本发明的示例性实施例。应注意的是,这些示例仅仅是对本发明的说明。本领域的普通技术人员显然可以进行多种改进和变更。
Claims (20)
1.一种半导体器件,包括:
集成电路,包括电极焊盘;
第一绝缘层,被设置在该集成电路上;
再分布层,包括多个布线并被设置在该第一绝缘层上,所述多个布线的至少一个被电耦接到该电极焊盘;
第二绝缘层,在所述多个布线的至少一部分上具有开口;
金属膜,被设置在所述开口上和该第二绝缘层上,并且该金属膜被电耦接到所述多个布线的至少一个;以及
焊接凸点,悬于所述多个布线中没有被电耦接到该金属膜的至少一个布线之上。
2.根据权利要求1的半导体器件,其中在该再分布层与该第二绝缘层的接合部表面的至少一部分中,该再分布层的中心线平均表面粗糙度为100nm或以上。
3.根据权利要求1的半导体器件,其中该再分布层包括:
第一导电层,被设置在该第一绝缘层上;以及
第二导电层,被设置在该第一导电层上,
其中,该第一导电层的图案小于该第二导电层的图案。
4.一种半导体器件,包括:
集成电路,包括电极焊盘;
第一绝缘层,被设置在该集成电路上;
再分布层,包括多个布线并被设置在该第一绝缘层上,所述多个布线的至少一个被电耦接到该电极焊盘;
第二绝缘层,具有开口并覆盖所述多个布线的至少一部分;以及
金属层,被设置在所述开口上和该第二绝缘层上,并且该金属层被电耦接到所述多个布线的至少一个,该金属层悬于所述多个布线中没有被电耦接到该金属层的至少一个布线之上。
5.根据权利要求4的半导体器件,其中在该再分布层与该第二绝缘层的接合部表面的至少一部分中,该再分布层的中心线平均表面粗糙度为100nm或以上。
6.根据权利要求4的半导体器件,其中该再分布层包括:
第一导电层,被设置在该第一绝缘层上;以及
第二导电层,被设置在该第一导电层上,
其中该第一导电层的图案小于该第二导电层的图案。
7.根据权利要求4的半导体器件,该金属膜包括Ni层。
8.根据权利要求4的半导体器件,其中该金属膜包括厚度为1μm或以上的Cu层,并包括Ni层。
9.根据权利要求4的半导体器件,其中该第二绝缘层包括酚树脂。
10.根据权利要求9的半导体器件,其中该酚树脂包括橡胶材料。
11.根据权利要求4的半导体器件,其中在该再分布层上的第二绝缘层的厚度为3μm或以上。
12.根据权利要求4的半导体器件,其中该第二绝缘层的开口位于所述多个布线的至少一部分上,而该第一绝缘层的一部分没有被所述多个布线覆盖。
13.一种制造半导体器件的方法,包括以下步骤:
形成第一绝缘层,该第一绝缘层在集成电路中包括的电极焊盘上具有第一开口;
在该第一绝缘层上形成再分布层,该再分布层包括被电耦接到该电极焊盘的多个布线;
形成第二绝缘层,该第二绝缘层在所述多个布线的至少一部分上具有至少一个第二开口;以及
形成金属膜,使其被电耦接到所述多个布线的至少一个并且悬于所述多个布线中没有被电耦接到该金属膜的至少一个布线之上。
14.根据权利要求13的方法,其中该再分布层的中心线平均表面粗糙度为100nm或以上。
15.根据权利要求13的方法,还包括以下步骤,
在该金属膜上形成焊接凸点,使其悬于所述多个布线中没有被电耦接到该金属膜的至少一个布线之上。
16.根据权利要求13的方法,还包括以下步骤:
在该第一绝缘层上形成第一导电层和第二导电层;以及
用该第二导电层作为掩模来蚀刻该第一导电层,使得该第一导电膜的图案小于该第二导电膜的图案。
17.根据权利要求13的方法,还包括以下步骤:
在该第一绝缘层上形成第一导电层;
通过电镀在该第一导电层上形成第二导电层;以及
控制电镀液中的添加剂含量,使得该第二导电层的中心线平均表面粗糙度为100nm或以上。
18.根据权利要求17的方法,其中该第二导电层包括铜,并且该电镀液包括硫酸铜水溶液,所述硫酸铜水溶液包括作为添加剂的氯和聚丙烯酰胺的至少一种。
19.根据权利要求13的方法,其中该第二绝缘层在200℃或以下的温度下固化。
20.根据权利要求13的方法,其中该金属膜包括厚度为1μm或以上的Cu层,并包括Ni层。
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US8952538B2 (en) | 2015-02-10 |
US11004817B2 (en) | 2021-05-11 |
US9893029B2 (en) | 2018-02-13 |
US20180122760A1 (en) | 2018-05-03 |
US20150118841A1 (en) | 2015-04-30 |
JP5544872B2 (ja) | 2014-07-09 |
US20110156248A1 (en) | 2011-06-30 |
CN102148210B (zh) | 2014-09-17 |
JP2011134942A (ja) | 2011-07-07 |
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