JP5544872B2 - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- JP5544872B2 JP5544872B2 JP2009294180A JP2009294180A JP5544872B2 JP 5544872 B2 JP5544872 B2 JP 5544872B2 JP 2009294180 A JP2009294180 A JP 2009294180A JP 2009294180 A JP2009294180 A JP 2009294180A JP 5544872 B2 JP5544872 B2 JP 5544872B2
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- insulating layer
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
(付記1)
複数の電極パッドを有する集積回路と、
前記集積回路上に形成された第1の絶縁層と、
前記第1の絶縁層上に形成され、前記複数の電極パッドに電気的に接続された複数の再配線を有する再配線層と、
前記再配線層及び前記第1の絶縁層の上に形成され、前記複数の再配線の各々の一部上に開口を有する第2の絶縁層と、
各々が前記開口内及びその周囲の前記第2の絶縁層上に形成され且つ前記再配線層に電気的に接続された複数の金属膜と、
前記複数の金属膜上に形成された複数のはんだバンプと、を有し、
前記再配線層は、前記第2の絶縁層との接合面の少なくとも一部において100nm以上の中心線平均粗さを有し、且つ前記複数のはんだバンプの少なくとも一部の各々が、該はんだバンプに電気的に接続されない前記再配線層の再配線に跨る、
ことを特徴とする半導体装置。
(付記2)
前記再配線層は、前記第1の絶縁層上に形成された第1導電層と、該第1導電層上に形成された第2導電層とを有し、前記複数の再配線の各々において、前記第1導電層のパターンの大きさは前記第2導電層のそれより小さい、ことを特徴とする付記1に記載の半導体装置。
(付記3)
複数の電極パッドを有する集積回路と、
前記集積回路上に形成された第1の絶縁層と、
前記第1の絶縁層上に形成され、前記複数の電極パッドに電気的に接続された複数の配線を有する再配線層と、
前記再配線層及び前記第1の絶縁樹脂層の上に形成され、前記複数の配線の各々の一部上に開口を有する第2の絶縁層と、
各々が前記開口内及びその周囲の前記第2の絶縁層上に形成され且つ前記再配線層に電気的に接続された複数の金属膜と、を有し、
前記再配線層は、前記第2の絶縁層との接合面の少なくとも一部において100nm以上の中心線平均粗さを有し、且つ前記複数の金属膜の少なくとも一部の各々が、該金属膜に電気的に接続されない前記再配線層の再配線に跨る、
ことを特徴とする半導体装置。
(付記4)
前記再配線層は、前記第1の絶縁層上に形成された第1導電層と、該第1導電層上に形成された第2導電層とを有し、前記複数の再配線の各々において、前記第1導電層のパターンの大きさは前記第2導電層のそれより小さい、ことを特徴とする付記3に記載の半導体装置。
(付記5)
前記金属膜はNi膜を含むことを特徴とする付記1乃至4の何れか一に記載の半導体装置。
(付記6)
前記金属膜はCu膜及び該Cu膜上のNi膜を含み、該Cu膜は1μm以上の厚さを有する、ことを特徴とする付記1乃至5の何れか一に記載の半導体装置。
(付記7)
前記第2の絶縁層はフェノール樹脂を有することを特徴とする付記1乃至6の何れか一に記載の半導体装置。
(付記8)
前記フェノール樹脂はゴム材料を含有することを特徴とする付記7に記載の半導体装置。
(付記9)
前記第2の絶縁層は前記再配線層上で3μm以上の厚さを有することを特徴とする付記1乃至8の何れか一に記載の半導体装置。
(付記10)
前記第2の絶縁層の前記開口は、前記複数の再配線の各々の一部上と、該一部の周囲の、前記複数の再配線により覆われていない前記第1の絶縁層の一部上とに跨って形成されている、ことを特徴とする付記1乃至8の何れか一に記載の半導体装置。
(付記11)
複数の電極パッドを有する集積回路上に、前記電極パッド上に第1の開口を有する第1の絶縁層を形成する工程と、
前記第1の絶縁層上に、前記複数の電極パッドに電気的に接続された複数の再配線を有する再配線層を形成する工程であり、該再配線層の表面の少なくとも一部が100nm以上の中心線平均粗さを有するように再配線層を形成する工程と、
前記再配線層及び前記第1の絶縁層の上に、前記複数の再配線の各々の一部上に第2の開口を有する第2の絶縁層を形成する工程と、
前記第2の開口内及びその周囲の前記第2の絶縁層上に、前記再配線層に電気的に接続された複数の金属膜を形成する工程と、
前記複数の金属膜上に複数のはんだバンプを形成する工程であり、少なくとも一部のはんだバンプの各々が該はんだバンプに電気的に接続されない前記再配線層の再配線に跨るように複数のはんだバンプを形成する工程と、
を有することを特徴とする半導体装置の製造方法。
(付記12)
複数の電極パッドを有する集積回路上に、前記電極パッド上に第1の開口を有する第1の絶縁層を形成する工程と、
前記第1の絶縁層上に、前記複数の電極パッドに電気的に接続された複数の再配線を有する再配線層を形成する工程であり、該再配線層の表面の少なくとも一部が100nm以上の中心線平均粗さを有するように再配線層を形成する工程と、
前記再配線層及び前記第1の絶縁層の上に、前記複数の再配線の各々の一部上に第2の開口を有する第2の絶縁層を形成する工程と、
前記第2の開口内及びその周囲の前記第2の絶縁層上に、前記再配線層に電気的に接続された複数の金属膜を形成する工程であり、少なくとも一部の金属膜の各々が該金属膜に電気的に接続されない前記再配線層の再配線に跨るように複数の金属膜を形成する工程と、
を有することを特徴とする半導体装置の製造方法。
(付記13)
前記再配線層は、前記第1の絶縁層上に形成された第1導電層と、該第1導電層上に形成された第2導電層とを有し、
前記再配線層を形成する工程は、
パターン形成された前記第2導電層をマスクとしたエッチングにより、前記複数の再配線の各々において前記第1導電層のパターンの大きさが前記第2導電層のそれより小さくなるように、前記第1導電層をパターニングする工程を有する、
ことを特徴とする付記11又は12に記載の半導体装置の製造方法。
(付記14)
前記再配線層は、前記第1の絶縁層上に形成された第1導電層と、該第1導電層上に形成された第2導電層とを有し、
前記再配線層を形成する工程は、前記第2導電層を電解めっきにより形成し、前記第2導電層の表面が100nm以上の中心線平均粗さを有するようにめっき浴中の添加剤の濃度を管理することを有する、
ことを特徴とする付記11乃至13の何れか一に記載の半導体装置の製造方法。
(付記15)
前記第2導電層は銅を有し、前記めっき浴は、前記添加剤として塩素及び/又はポリアクリルアミドが混入された硫酸銅水溶液を有する、ことを特徴とする付記14に記載の半導体装置の製造方法。
(付記16)
前記第2の絶縁層を形成する工程は、絶縁樹脂膜の成膜及びパターニングの後に、該絶縁樹脂膜を200℃以下の温度でキュアする工程を有する、ことを特徴とする付記11乃至15の何れか一に記載の半導体装置の製造方法。
(付記17)
前記第2の絶縁層はフェノール樹脂を有することを特徴とする付記15に記載の半導体装置の製造方法。
(付記18)
前記金属膜を形成する工程は、1μm以上の厚さのCu膜を形成する工程と、該Cu膜上に電解めっきによりNi膜を形成する工程とを含む、ことを特徴とする付記11乃至17の何れか一に記載の半導体装置の製造方法。
20 半導体基板
21 電極パッド
22 絶縁保護膜
26 絶縁保護膜の開口
31 第1の絶縁(樹脂)層
32 第2の絶縁(樹脂)層
35 導電性ビア
36 第1の絶縁層の開口
37 第2の絶縁層の開口
40 再配線(層)
40a 第1ランド部
40b 第2ランド部
40c 配線部
41 再配線の第1導電層
42 再配線の第2導電層
44 アンダーカット領域
46、56 レジストパターン
50、60、70 バンプ下金属(UBM)膜
51、61、71 UBM膜の第1導電膜
52、62、72 UBM膜の第2導電膜
53、63、73 UBM膜の第3導電膜
55、65 はんだバンプ
Claims (8)
- 複数の電極パッドを有する集積回路と、
前記集積回路上に形成された第1の絶縁層と、
前記第1の絶縁層上に形成され、前記複数の電極パッドに電気的に接続された複数の再配線と、
前記複数の再配線及び前記第1の絶縁層の上に形成され、前記複数の再配線の各々の一部上に開口部を有する第2の絶縁層と、
前記開口部の内部及び該開口部の周囲の前記第2の絶縁層上に形成され且つ前記複数の再配線の各々に電気的に接続された複数の金属膜と、
前記複数の金属膜上に形成された複数のはんだバンプと、を有し、
前記複数の再配線は、前記第1の絶縁層上に形成され第1の形状を有する第1の導電層と前記第1の導電層の上に形成され前記第1の形状よりも大きい第2の形状を有する第2の導電層とを含み、前記第2の導電層と前記第2の絶縁層との接合面の少なくとも一部において100nm以上の中心線平均粗さを有し、
前記複数のはんだバンプの内の少なくとも一つが、該はんだバンプに電気的に接続されない前記複数の再配線の内の一つに跨る、
ことを特徴とする半導体装置。 - 複数の電極パッドを有する集積回路と、
前記集積回路上に形成された第1の絶縁層と、
前記第1の絶縁層上に形成され、前記複数の電極パッドに電気的に接続された複数の再配線と、
前記複数の再配線及び前記第1の絶縁層の上に形成され、前記複数の再配線の各々の一部上に開口部を有する第2の絶縁層と、
前記開口部の内部及び該開口部の周囲の前記第2の絶縁層上に形成され且つ前記複数の再配線の各々に電気的に接続された複数の金属膜と、を有し、
前記複数の再配線は、前記第1の絶縁層上に形成され第1の形状を有する第1の導電層と前記第1の導電層の上に形成され前記第1の形状よりも大きい第2の形状を有する第2の導電層とを含み、前記第2の導電層と前記第2の絶縁層との接合面の少なくとも一部において100nm以上の中心線平均粗さを有し、
前記複数の金属膜の内の少なくとも一つが、該金属膜に電気的に接続されない前記複数の再配線の内の一つに跨る、
ことを特徴とする半導体装置。 - 前記金属膜はCu膜及び該Cu膜上のNi膜を含み、該Cu膜は1μm以上の厚さを有する、ことを特徴とする請求項1または2に記載の半導体装置。
- 前記第2の絶縁層はフェノール樹脂を有することを特徴とする請求項1乃至3の何れか一項に記載の半導体装置。
- 前記第2の絶縁層の前記開口部は、前記複数の再配線の各々の一部上と少なくとも一つの側面とを前記第2の絶縁層から露出させるように形成されている、ことを特徴とする請求項1乃至4の何れか一項に記載の半導体装置。
- 複数の電極パッドを有する集積回路上に、前記電極パッド上に第1の開口部を有する第1の絶縁層を形成する工程と、
前記第1の絶縁層上に、前記複数の電極パッドに電気的に接続された複数の再配線を形成する工程と、
前記複数の再配線及び前記第1の絶縁層の上に、前記複数の再配線の各々の一部上に第2の開口部を有する第2の絶縁層を形成する工程と、
前記第2の開口部の内部及び該第2の開口部の周囲の前記第2の絶縁層上に、前記複数の再配線の各々に電気的に接続された複数の金属膜を形成する工程と、
前記複数の金属膜上に複数のはんだバンプを形成する工程であり、少なくとも一つのはんだバンプが該はんだバンプに電気的に接続されない前記複数の再配線の内の一つに跨るように複数のはんだバンプを形成する工程と、
を有し、
前記複数の再配線は、前記第1の絶縁層上に形成され第1の形状を有する第1の導電層と前記第1の導電層の上に形成され第2の形状を有する第2の導電層とを含み、前記複数の再配線を形成する工程は、前記第2の導電層をマスクとしたエッチングによって、前記第1の形状が前記第2の形状より小さくなるように前記第1の導電層をパターニングすることを含み、且つ前記第2の導電層と前記第2の絶縁層との接合面の少なくとも一部が100nm以上の中心線平均粗さを有するように前記複数の再配線を形成する、
ことを特徴とする半導体装置の製造方法。 - 前記複数の再配線を形成する工程は、前記第2の導電層を電解めっきにより形成し、前記第2の導電層の表面が100nm以上の中心線平均粗さを有するようにめっき浴中の添加剤の濃度を管理することを有する、
ことを特徴とする請求項6に記載の半導体装置の製造方法。 - 前記第2の絶縁層を形成する工程は、絶縁樹脂膜の成膜及びパターニングの後に、該絶縁樹脂膜を200℃以下の温度でキュアする工程を有する、ことを特徴とする請求項6または7に記載の半導体装置の製造方法。
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