TWI476880B - 用於積體電路之凸塊應力減輕層 - Google Patents

用於積體電路之凸塊應力減輕層 Download PDF

Info

Publication number
TWI476880B
TWI476880B TW098142059A TW98142059A TWI476880B TW I476880 B TWI476880 B TW I476880B TW 098142059 A TW098142059 A TW 098142059A TW 98142059 A TW98142059 A TW 98142059A TW I476880 B TWI476880 B TW I476880B
Authority
TW
Taiwan
Prior art keywords
solder
integrated circuit
layer
metal
metal bump
Prior art date
Application number
TW098142059A
Other languages
English (en)
Other versions
TW201030918A (en
Inventor
Kevin J Lee
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of TW201030918A publication Critical patent/TW201030918A/zh
Application granted granted Critical
Publication of TWI476880B publication Critical patent/TWI476880B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3192—Multilayer coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02175—Flow barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/0219—Material of the auxiliary member
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05022—Disposition the internal layer being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05026—Disposition the internal layer being disposed in a recess of the surface
    • H01L2224/05027—Disposition the internal layer being disposed in a recess of the surface the internal layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H01L2224/05559—Shape in side view non conformal layer on a patterned surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05567—Disposition the external layer being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
    • H01L2224/10122—Auxiliary members for bump connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
    • H01L2224/10125—Reinforcing structures
    • H01L2224/10126—Bump collar
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H01L2224/11462—Electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H01L2224/11464—Electroless plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13005—Structure
    • H01L2224/13007—Bump connector smaller than the underlying bonding area, e.g. than the under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13023—Disposition the whole bump connector protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13164—Palladium [Pd] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13169—Platinum [Pt] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16112—Disposition the bump connector being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81192—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00013—Fully indexed content
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01027—Cobalt [Co]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01032—Germanium [Ge]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2924/15738—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950 C and less than 1550 C
    • H01L2924/15747—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3512—Cracking
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3512—Cracking
    • H01L2924/35121—Peeling or delaminating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/38—Effects and problems related to the device integration
    • H01L2924/384—Bump effects
    • H01L2924/3841—Solder bridging

Description

用於積體電路之凸塊應力減輕層
本發明係有關於用於積體電路之凸塊應力減輕層。
在積體電路的製造中，一覆晶連接經常被用來將一積體電路晶粒(IC晶粒)附裝至一載負基材，譬如像是一積體電路封裝(IC封裝)或一母板。一覆晶構形(configuration)使用一陣列的金屬凸塊其被設置在該IC晶粒的表面上。該等金屬凸塊被對準IC封裝上的對應焊錫球。當被對準時，一溫度在焊錫的熔點之上的退火處理即被實施，以造成焊錫球回流並將該等金屬凸塊弄濕。該等焊錫球與金屬凸塊然後被快速地冷卻用以將金屬的相混減至最小。介於金屬凸塊/焊錫球連接之間及周圍的間隙被填入下填材料，譬如像是環氧樹脂。
挑戰整個微電子工業的一項關鍵的議題為在IC晶粒中相對脆弱的低k層間介電(ILD)層在覆晶封裝處理期間發生的破裂及剝離。在目前的設計中，作用在IC晶粒內的ILD層上的負荷因為來自熱膨脹不匹配的剪應力及因為晶粒與封裝的翹曲行為的正應力而很高。傳統上，因為二氧化矽(其為一相對強的介電材料)典型地被用於該等ILD層，所以破裂及剝離尚未是業界的一個問題。但是，因為使用相對脆弱的低k介電材料已成為業界的標準，所以需要改良的設計來減少包含這些低k材料的ILD層的破裂及剝離。再者，隨著積體電路晶粒及封裝的尺寸持續縮小，所以因為趨勢是朝向縮小的凸塊間距及縮小的凸塊直徑的關係，這些問題被預期會變得更加麻煩。
 【發明內容及實施方式】
本文中所描述的是減小在一積體電路封裝的金屬凸塊層的機械應力的系統及方法。在下面的描述中，各種示範性實施的態樣將使用熟習此技藝者所一般使用的用語來加以描述，用以將他們工作的實質內容傳達給其他熟習此技藝者。然而，對熟習此技藝者言將是很明顯的是，本發明可以只使用某些被描述的態樣來實施。為了說明的目的，特定的數字，材料及構形被提出，以提供對該等示範性實施的徹底瞭解。然而，對熟習此技藝者言將是很明顯的是，本發明可在沒有這些特定的細節下被實施。在其它的例子中，習知的特徵被省略或簡化以避免糢糊了這些示範性實施。
各種操作將以一種最有助於瞭解本發明的方式被依序描述為多個分離的操作，然而，描述的順序不應被解讀為暗示這些操作必定與順序有關。詳言之，這些操作未必是依照提出的順序來實施。
圖1A顯示傳統的IC晶粒100及IC封裝150在被耦合之前的情形。IC晶粒100被顯示為具有一基材102，一元件層104，金屬化層106，多層被動層108，一最終的厚的金屬化層110，及多個金屬凸塊112。凸塊112可使用包括，但不侷限於，銅、鎳、鈀、金、及其它金屬或合金，譬如像是鉛與錫的合金來形成。該結構亦可包含介於金屬凸塊112與最終的被動層108之間的阻障及種晶層114，它們亦被稱為凸塊限制金屬(BLM)層114。圖1A的IC晶粒100被提供作為一IC晶粒的代表性例子且許多其它的變化在此技藝中係為習知。本文中所提供之本發明的實施並不打算要被侷限，也不應被侷限在圖1A所示之特定的IC晶粒結構。
如此技藝中所習知的，基材102可使用像是整塊的矽、絕緣材料上的矽、含鍺的材料及其它適合用作為半導體基材的材料來製造。該元件層104是基材102的頂面且包含各式電子元件，包括但不侷限於，電晶體、電容器、互連線，及淺溝渠隔離結構(它們都未被示出)。
金屬化層106用來互連該半導體基材102上的各式元件。該等金屬化層106可包括金屬互連線、用來分離及隔絕金屬互連線的層間介電(ILD)層、及貫孔(vias)其貫穿該等ILD層將金屬互連線耦合在一起。該等ILD層可用譬如像是摻雜了碳的氧化物及二氧化矽來形成。就是這些ILD層經常會因為覆晶封裝處理所誘發的應力而破裂或剝離。該等金屬互連線及貫孔通常是用金屬或包含銅或鎢的合金形成的。
一或多層被動層108通常被形成在該等金屬化層106上。該等被動層108將該IC晶粒密封且保護它免於受損或污染。該等被動層108可用許多不同的材料來形成，其包括但不侷限於，ILD、氮化物、二氧化矽、苯並唑、環氧樹脂、矽酮、二苯並環丁烯、酚系樹脂、及聚醯亞胺。一最終的厚的金屬化層110可被用來提供一強健的連接於金屬化層106與多個形成在該等被動層108上的金屬凸塊112之間。
該等金屬凸塊112藉由被形成穿過該等被動層108的金屬貫孔來保持對積體電路晶粒的金屬化層的電連接。該等BLM層114典型地為用於該等金屬凸塊112的阻障及種晶層。如上文中提到的，該等金屬凸塊112通常是使用銅、鎳、鈀、金、或在其它實施中為鉛與錫的合金來形成。該等金屬凸塊112可使用此技藝中習知的處理來形成，其包括但不侷限於CVD、PVD、ALD、PECVD、電鍍、及無電電鍍。
圖1A進一步顯示IC封裝150其包括一基材152，該基材具有多個安裝在該基材152的一側上的焊錫球154。該等焊錫球154可用許多傳統的焊錫材料來形成，例如，可使用錫、銀、及銅的合金。該基材152如一微型印刷電路板般地作用，其將該等焊錫球154安排路徑(routing)至許多安裝在該基材152的另一側上的電連接。這些電連接被安排成一柵格陣列156的形式，譬如像是接腳柵格陣列(PGA)、錫球柵隔陣列(BGA)、地柵格陣列(LGA)。
圖1B及1C顯示該覆晶連接如何誘發在該IC晶粒100中的應力。首先，IC晶粒100被顯示為耦合至IC封裝150。將晶粒與封裝實體地連接的方法在此技藝中為習知。如圖所示，每一焊錫球154都沿著一界面160被電及實體地連接至一金屬凸塊112。在回流處理以將焊錫球154與金屬凸塊112實體地結合的期間，焊錫球154將金屬凸塊112弄濕一直到金屬凸塊112的邊緣。因此，焊錫球154在直徑上傾向於比金屬凸塊112大。
如圖所示，該被誘發的應力是因為IC晶粒100的熱膨脹係數(CTE)比IC封裝150的熱膨脹係數小很多。因為IC晶粒100與IC封裝150不斷地在溫度上遭遇到大的變動，譬如像是在製造期間及實際使用在產品上的期間，CTE差異造成IC封裝150在比IC晶粒100高的膨脹及收縮率下膨脹與收縮。這對焊錫球/金屬凸塊連接施加很大的應力，將壓縮及拉伸應力傳遞至IC晶粒100的金屬化層106內的ILD層中並造成破裂及/或剝離的問題。
例如，圖1B顯示在相對高溫時發生的情況。在此例子中，IC封裝150以大於IC晶粒100的膨脹率膨脹，將焊錫球154拉離該IC封裝150的中心，因此亦拉離該等金屬凸塊112。箭頭162大致地顯示直接傳播至該IC晶粒110中的壓縮及拉伸應力。相類似地，圖1C顯示在相對低溫時發生的情況。在此例子中，IC封裝150以大於IC晶粒100的收縮率收縮，將焊錫球154推入該IC封裝150的中心，因此亦推入該等金屬凸塊112。再次地，箭頭162大致地顯示在此情形中直接傳播至該IC晶粒110中的壓縮及拉伸應力。
減少破裂及剝離的一種方法為使用較寬的金屬凸塊112其可將應力分散在一較大的面積上。很不幸地，因為IC晶粒100趨勢是尺寸更小但效能更提高，所需的輸入/輸出連接的數量持續增加，造成相鄰的金屬凸塊112之間更小的間距及縮小的間隙。如圖1D所示，隨著介於金屬凸塊112之間的距離被最小化，相關連的焊錫球154傾向與彼此接觸並短路。因此，必需使用窄的金屬凸塊112，其限制了它們將IC封裝150所誘發的應力分散的能力。
為了要克服先前技術的缺點，圖2A顯示依據本發明的一個實施的焊錫限制層200。該焊錫限制層200被形成在該被動層108的上方及部分金屬凸塊112的上方。該焊錫限制層200遮蔽金屬凸塊112的一部分頂面，藉以限制焊錫球154可接觸到的表面積量。更明確地，該焊錫限制層200遮蔽每一金屬凸塊112的頂面的外緣202，藉以讓這些頂面外緣(202)對於焊錫材料是不可弄濕的(non-wettable)。這可防止焊錫球154一路弄濕到該金屬凸塊112的外緣。圖2B顯示遮蔽該金屬凸塊112的頂面外緣202的焊錫限制層200的俯視圖，藉以只允許該頂面的中央部分被露出來。在不同的實施中，該焊錫限制層200可遮蔽15%至95%的金屬凸塊112的頂面。在一些實施中，該焊錫限制層200可遮蔽35%至50%的金屬凸塊112的頂面。
如圖2C所示，當具有該焊錫限制層200的IC晶粒100被耦合至該IC封裝150時，焊錫球154被限制在該金屬凸塊112的頂面的中央部分。焊錫球154不能將該等金屬凸塊112的外緣弄濕，也因此不能延伸超過該等金屬凸塊112的外緣。
該焊錫限制層200可使用許多可以與半導體製程相容且不會被焊錫材料弄濕的絕緣材料來形成。可被用於該焊錫限制層200的材料的一些例子包括但不侷限於可光學界定的(photodefinable)聚合的介電材料、傳統的介電材料、環氧樹脂、矽酮、聚醯亞胺、不可弄濕的金屬，譬如像是鋁及鎢、及氮化物。可光學界定的聚合的介電材料的一些特定的例子包括但不侷限於由Rohm and Hoas提供的InterViaTM 8000系列的可光學界定的介電材料、由Dow Chemical提供的CycloteneTM 4000系列的可光學界定的介電材料、由Microchem提供的SU-8可光學界定的環氧樹脂材料、由Dow Corning提供的WL-5000系列的可光學界定的矽酮介電材料、由Promerus提供的Avatre可光學界定的介電材料、由ShinEtsuMicroSi提供的SINR系列的可光學界定的介電材料、由Sumitomo Bakelite有限公司提供的SUMIRESIN EXCELCRC-8600系列可光學界定的介電材料、由FujiFilm提供的AN-3310及Durimide 7000系列的可光學界定的聚醯亞胺介電材料、由Toray提供的PhotoneeceTM 可光學界定的聚醯亞胺介電材料、由Asahi Kasei EMD提供的PimelTM 的可光學界定的聚醯亞胺介電材料、由HD Microsystems提供的可光學界定的聚醯亞胺介電材料、由Tokyo Ohka Kogyo有限公司提供的TMMR S2000可光學界定的介電材料、及由JSR Micro公司提供的WPR系列可光學界定的介電材料。
圖2D及2E顯示使用本發明的焊錫限制層所形成的覆晶連接是如何能夠減輕在IC晶粒100內的應力。圖2D顯示在相對高溫下當IC封裝150以大於IC晶粒100的膨脹率在膨脹時發生的情況。圖2E顯示在相對低溫下當IC封裝150以大於IC晶粒100的收縮率在收縮時發生的情況。箭頭162大致顯示被產生的壓縮及拉伸應力。
與圖1B及1C所示的應力不同，依據本發明的實施，應力因為它們在一平行於該IC晶粒100的頂面的方向上的初始傳播而被部分地減輕。該等應力在被傳播至該IC晶粒100之前，橫越該等金屬凸塊112的頂面的一部分才進入到該焊錫限制層200中。這降低了被傳遞至該晶粒100中的壓縮及拉伸應力且至少部分地減輕譬如像是介電層的破裂及/或剝離的問題。
圖2F顯示本發明的另一個實施，其中較寬的金屬凸塊112與本發明的焊錫限制層200一起被使用。再次地，該等較寬的金屬凸塊112可將應力分散於一較大的面積上。在此處，當介於該等金屬凸塊112之間的間隙被最小化時，該焊錫限制層200可防止該等焊錫球154彼此接觸，藉以防止會發生在如圖1D所示的先前技術中的短路。
圖3為依據本發明的一個實施之形成一焊錫限制層200的方法300。有一個包括多個金屬凸塊112的IC晶粒100，該方法300係以沉積一焊錫限制材料的毯覆層於該IC晶粒100及金屬凸塊112上來開始(圖3的處理302)。該焊錫限制材料可以整個覆蓋該等金屬凸塊112。在此實施中，該焊錫限制材料可以是上文所描述的可光學界定的聚合的介電材料中的任何一種。該可光學界定的聚合的介電材料可使用傳統的沉積方法來沉積，其包括但不侷限於物理氣相沉積、濺鍍、旋轉沉積、原子層沉積、或化學氣相沉積。可以與可光學界定的聚合的介電材料一起使用之其它的沉積處理亦可被使用。
接下來，該焊錫限制材料被圖案化以形成開孔，其可將每一金屬凸塊112的一部分頂面露出(處理304)。該焊錫限制材料係使用適合可光學界定的聚合的介電材料之習知的光蝕刻(photolithography)處理加以圖案化。依據本發明的實施，該圖案化處理將焊錫限制材料從每一金屬凸塊12的一部分頂面上去除掉，而沒有實質地露出該等金屬凸塊112的外緣。
圖案化處理，即光蝕刻處理，在此技藝中是習知的。光蝕刻處理將大致包括一曝光步驟以在該焊錫限制材料上界定出在該等金屬凸塊112上方的開孔(處理304a)。請注意該等開孔只是在此步驟中被界定；該等開孔尚未被形成。依據本發明，該等被界定的開孔並沒有延伸至該等金屬凸塊112的邊緣。而是，該等開孔實質上覆蓋每一凸塊112的頂面的一中心部分。該曝光步驟使用一光罩及某些形式的輻射，譬如像是紫外線輻射或超紫外線輻射。
接下來，在一顯影步驟中，一顯影劑溶液被施用，以去除掉界定位在該等金屬凸塊112上方的開孔的可光學界定的介電材料部分(處理304b)。那些被去除掉的部分將會是被露出來的或未被露出來的區域，依該可光學界定的聚合的介電材料是正色調或負色調而定。當這些部分被去除時，最終的結果是一焊錫限制層200其遮蔽該等金屬凸塊112的邊緣，但留著該等金屬凸塊112的頂面的一部分被露出。在一些實施中，該最終的焊錫限制層200可被烘烤或固化以硬化該層(處理304c)。
在本發明的另一實施中，一可光學界定的聚合的介電材料以外的材料可被用於該焊錫限制材料。例如，某些其它的介電材料、環氧樹脂、矽酮、聚醯亞胺、及氮化物可被使用，如果它們對於焊錫而言是不可弄濕的且它們具有適當的相容性及絕緣特性的話。圖4描述此替代的方法400。
圖4為使用光阻來形成開孔圖案於焊錫限制層上的方法400。當焊錫限制材料不是可光學界定的材料時，一傳統的圖案化處理可被用來形成該等開孔於該等金屬凸塊112上方。例如，有一包括多個金屬凸塊112的IC晶粒100，該方法400係以沉積一焊錫限制材料的毯覆層於該IC晶粒100及金屬凸塊112上來開始(圖4的處理402)。該焊錫限制材料可以整個覆蓋該等金屬凸塊112。
接下來，一層光阻材料被沉積在該焊錫限制材料上(處理404)。該光阻材料係使用習知光蝕刻處理加以圖案化，用以形成開孔於該光阻中，該等開孔被對準在每一金屬凸塊112上方，但並未實質地延伸至每一金屬凸塊112的邊緣(處理406)。對該光阻的圖案化處理包括習知的曝光、烘烤、及顯影步驟。
這些在光阻內的開孔然後被用作為一遮罩來蝕刻底下的焊錫限制材料並將該等開孔從該光阻層轉移至該焊錫限制材料中(處理408)。在焊錫限制材料中的該等開孔在沒有實質露出該等金屬凸塊112的邊緣下露出每一金屬凸塊112的頂面的一部分。該蝕刻處理係使用一對於被選取之焊錫限制材料而言是適合的蝕刻劑來實施。
最後，該光阻材料被去除(處理410)且最終結果是一焊錫限制層200，其遮蔽該等金屬凸塊112的外緣但讓該等金屬凸塊112的頂面的一部分被露出來。在一些實施中，該被形成之最終的焊錫限制層200可被烘烤用以將該層進一步硬化。
圖5A顯示依據本發明的另一實施之焊錫限制層。在此實施中，該焊錫限制層200為一相對薄的保形層。在此技藝中用來沉積保形層的習知處理，譬如像是CVD及ALD，可被使用。介於金屬凸塊112之間的間隙可用一不同於該焊錫限制層200的下填材料，譬如像是環氧樹脂，來填入。圖5B及5C顯示保形焊錫限制層200的其它變化。在此，該層200在介於金屬凸塊112之間的區域上的部分被去除掉。在圖5A中，該焊錫限制層200的一唇部202留在每一金屬凸塊112的基部。在圖5B中，即便是此唇部也被去除掉。在圖5B及5C的實施中，該焊錫限制層200因而是一不連續的層。
圖6A至6D顯示該焊錫限制層200其它替代的實施。在這些實施中，一焊錫球154被預先附裝至該IC晶粒110，而不是該IC封裝150的一部分。圖6A顯示一與本發明的焊錫限制層200一起被使用之預先附裝的焊錫球154。圖6B顯示一與本發明的保形焊錫限制層200一起被使用之預先附裝的焊錫球154。圖6C顯示一與本發明的不連續的保形焊錫限制層200一起被使用之預先附裝的焊錫球154，其中該焊錫限制層包括唇部202。圖6D顯示一與本發明不具有唇部之不連續的保形焊錫限制層200一起被使用之預先附裝的焊錫球154。
圖7A及7B顯示另外的實施，其中額外的金屬凸塊700被用來將應力進一步從該IC晶粒100移走。在圖7A中，額外的金屬凸塊700被形成在該焊錫限制層200的開孔內。在圖7B中，額外的金屬凸塊700被形成在該焊錫限制層200之上。在該焊錫限制層200內的開孔在此實施中被貫孔702所取代，該等貫孔將金屬凸塊112耦合至該等額外的金屬凸塊700。
因此，一焊錫限制層已描述，其限制多少的金屬凸塊112的表面可被一焊錫球154弄濕。依據本發明的實施，該焊錫限制層防止該等金屬凸塊的邊緣被該等焊錫球弄濕，藉以將焊錫球侷限在該金屬凸塊的頂面的一部分處。該焊錫限制層亦有助於在IC封裝被附裝至該IC晶粒時散佈應力。揭露於本文中之本發明的實施提供額外的低k ILD保護，它可縮小凸塊間距並容許使用相對脆弱的低k ILD材料及較脆弱的金屬層結構，包括氣隙形結構在內。
本發明之被例示的實施的上述描述(包括在摘要中所描述者)並不是窮舉性的或是將本發明侷限至所揭露的刻板的形式。雖然本發明的特定實施及例子為了示範的目的於本文中被描述，但如熟習相關技藝者將會瞭解的，在本發明的範圍內有各種等效變化的可能。
根據上文的詳細描述，可對本發明實施這些變化。在下面的申請專利範圍中所使用的用語不應被解讀為將本發明侷限在說明書及申請專利範圍所揭露的特定實施上。相反地，本發明的範圍是要由下面的申請專利範圍來界定，申請專利範圍應依據被建立之申請專利範圍解釋的學理來加以理解。
100．．．IC晶粒
150．．．IC封裝
102．．．基材
104．．．元件層
106．．．金屬化層
108．．．被動層
110．．．最終的厚的金屬化層
112．．．金屬凸塊
114．．．阻障及種晶層/BLM層
152．．．基材
154．．．焊錫球
156．．．柵格陣列
160．．．界面
162．．．箭頭
200．．．焊錫限制層
202．．．外緣
162．．．箭頭
300．．．方法
400．．．方法
700．．．額外的金屬凸塊
702．．．貫孔
圖1A顯示傳統的金屬凸塊/焊錫球連接。
圖1B及1C顯示介於IC晶粒與IC封裝之間CTE不匹配如何施加壓擠及拉伸應力至IC晶粒中。
圖1D顯示與使用較寬的金屬凸塊相關連的問題。
圖2A及2B顯示一依據本發明的實施之焊錫限制層。
圖2C顯示一使用本發明的焊錫限制層所形成的覆晶連接。
圖2D及2E顯示使用本發明的焊錫限制層所形成的覆晶連接是如何能夠減輕在IC晶粒內的應力。
圖2F顯示一個實施，其中較寬的金屬凸塊與本發明的焊錫限制層一起被使用。
圖3為依據本發明的一個實施之形成一焊錫限制層的方法。
圖4為依據本發明的另一個實施之形成一焊錫限制層的方法。
圖5A至5C顯示本發明的焊錫限制層的其它實施。
圖6A至6D顯示包含了預附裝的焊錫球之本發明另外的實施。
圖7A及7B顯示包含了額外的金屬凸塊之本發明另外的實施。
100．．．IC晶粒
150．．．IC封裝
102．．．基材
104．．．元件層
106．．．金屬化層
108．．．被動層
110．．．最終的厚的金屬化層
112．．．金屬凸塊
152．．．基材
154．．．焊錫球
156．．．柵格陣列
162．．．箭頭
200．．．焊錫限制層
202．．．外緣

Claims (22)

  1. 一種積體電路，其包含：一積體電路晶粒，其具有一形成在其頂面上的金屬凸塊；及一焊錫限制層，其被形成在該積體電路晶粒上，其中該焊錫限制層遮蔽該金屬凸塊的頂面的一部分，藉以防止焊錫弄濕該金屬凸塊之被遮蔽的部分。
  2. 如申請專利範圍第1項之積體電路，其中該焊錫限制層包含可光學界定的聚合的介電材料。
  3. 如申請專利範圍第1項之積體電路，其中該焊錫限制層包含一選自於由介電材料、環氧樹脂、矽酮、聚醯亞胺、不可弄濕的金屬、及氮化物所構成的組群中的材料。
  4. 如申請專利範圍第1項之積體電路，其中該積體電路晶粒具有多個形成在其頂面上的金屬凸塊且該焊錫限制層填入到介於該等金屬凸塊之間的間隙中並將該等金屬凸塊彼此電絕緣。
  5. 如申請專利範圍第1項之積體電路，其中該被遮蔽的部分包含該金屬凸塊的頂面的外緣。
  6. 如申請專利範圍第1項之積體電路，其中該金屬凸塊包括一選自於由銅、鎳、鈀、鈷、鐵、銀、金、及鉑所構成的組群中之金屬。
  7. 如申請專利範圍第1項之積體電路，其中該焊錫限制層遮蔽該金屬凸塊的30%至50%之間的頂面。
  8. 一種積體電路，其包含：一半導體基材，其具有一元件層、多層金屬化層、一被動層、及一被形成在該被動層上的金屬凸塊，該金屬凸塊被電耦合至該等金屬化層中的至少一金屬化層；及一被形成在該被動層上的焊錫限制層，其遮蔽該金屬凸塊的頂面的外緣，藉以讓該頂面的外緣成為焊錫材料所不可弄濕者。
  9. 如申請專利範圍第8項之積體電路，其中該焊錫限制層包含可光學界定的聚合的介電材料。
  10. 如申請專利範圍第8項之積體電路，其中該焊錫限制層包含一選自於由介電材料、環氧樹脂、矽酮、聚醯亞胺、不可弄濕的金屬、及氮化物所構成的組群中的材料。
  11. 如申請專利範圍第8項之積體電路，其中該焊錫限制層遮蔽該金屬凸塊的30%至50%之間的頂面。
  12. 一種積體電路，其包含：一積體電路晶粒，其具有一形成在其頂面上的金屬凸塊；一焊錫限制層，其被形成在該積體電路晶粒上，其中該焊錫限制層實質地遮蔽該金屬凸塊的頂面的外緣，用以讓該外緣成為焊錫所不可弄濕者；及一被安裝在該金屬凸塊上的焊錫球，其中該焊錫球因為該焊錫限制層而沒有弄濕該金屬凸塊的頂面的外緣。
  13. 如申請專利範圍第12項之積體電路，其中該焊 錫限制層包含可光學界定的聚合的介電材料。
  14. 如申請專利範圍第12項之積體電路，其中該焊錫限制層包含一選自於由介電材料、環氧樹脂、矽酮、聚醯亞胺、不可弄濕的金屬、及氮化物所構成的組群中的材料。
  15. 如申請專利範圍第12項之積體電路，其中該焊錫限制層遮蔽該金屬凸塊的30%至50%之間的頂面。
  16. 如申請專利範圍第12項之積體電路，其中該金屬凸塊包括一選自於由銅、鎳、鈀、鈷、鐵、銀、金、及鉑所構成的組群中之金屬。
  17. 一種積體電路，其包含：一積體電路晶粒，其具有一形成在其頂面上的第一金屬凸塊；一焊錫限制層，其被形成在該積體電路晶粒上，其中該焊錫限制層實質地遮蔽該金屬凸塊的頂面的外緣，用以讓該外緣成為焊錫所不可弄濕者；及一安裝在該第一金屬凸塊上的第二金屬凸塊，其中該第二金屬塊因為該焊錫限制層而沒有與該第一金屬凸塊的頂面的外緣接觸。
  18. 如申請專利範圍第17項之積體電路，其中該焊錫限制層包含可光學界定的聚合的介電材料。
  19. 如申請專利範圍第17項之積體電路，其中該焊錫限制層包含一選自於由介電材料、環氧樹脂、矽酮、聚醯亞胺、不可弄濕的金屬、及氮化物所構成的組群中的材 料。
  20. 如申請專利範圍第17項之積體電路，其中該焊錫限制層遮蔽該金屬凸塊的30%至50%之間的頂面。
  21. 如申請專利範圍第17項之積體電路，其中該第一金屬凸塊包括一選自於由銅、鎳、鈀、鈷、鐵、銀、金、及鉑所構成的組群中之金屬。
  22. 如申請專利範圍第17項之積體電路，其中該第二金屬凸塊包括一選自於由銅、鎳、鈀、鈷、鐵、銀、金、及鉑所構成的組群中之金屬。
TW098142059A 2008-12-19 2009-12-09 用於積體電路之凸塊應力減輕層 TWI476880B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US12/317,227 US7982311B2 (en) 2008-12-19 2008-12-19 Solder limiting layer for integrated circuit die copper bumps

Publications (2)

Publication Number Publication Date
TW201030918A TW201030918A (en) 2010-08-16
TWI476880B true TWI476880B (zh) 2015-03-11

Family

ID=42264836

Family Applications (1)

Application Number Title Priority Date Filing Date
TW098142059A TWI476880B (zh) 2008-12-19 2009-12-09 用於積體電路之凸塊應力減輕層

Country Status (7)

Country Link
US (1) US7982311B2 (zh)
EP (1) EP2359396A4 (zh)
JP (1) JP2012505555A (zh)
KR (1) KR101242998B1 (zh)
CN (1) CN102171805B (zh)
TW (1) TWI476880B (zh)
WO (1) WO2010080275A2 (zh)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7964965B2 (en) * 2008-03-31 2011-06-21 Intel Corporation Forming thick metal interconnect structures for integrated circuits
US7982311B2 (en) * 2008-12-19 2011-07-19 Intel Corporation Solder limiting layer for integrated circuit die copper bumps
TWI445147B (zh) * 2009-10-14 2014-07-11 Advanced Semiconductor Eng 半導體元件
TWI478303B (zh) 2010-09-27 2015-03-21 Advanced Semiconductor Eng 具有金屬柱之晶片及具有金屬柱之晶片之封裝結構
US8934052B2 (en) * 2010-11-02 2015-01-13 Stmicroelectronics Pte Ltd Camera module including an image sensor and a laterally adjacent surface mount device coupled at a lower surface of a dielectric material layer
US8975741B2 (en) * 2011-10-17 2015-03-10 Taiwan Semiconductor Manufacturing Company, Ltd. Process for forming package-on-package structures
US9224674B2 (en) * 2011-12-15 2015-12-29 Intel Corporation Packaged semiconductor die with bumpless die-package interface for bumpless build-up layer (BBUL) packages
US8866311B2 (en) * 2012-09-21 2014-10-21 Advanced Semiconductor Engineering, Inc. Semiconductor package substrates having pillars and related methods
US9520350B2 (en) * 2013-03-13 2016-12-13 Intel Corporation Bumpless build-up layer (BBUL) semiconductor package with ultra-thin dielectric layer
US9607863B1 (en) * 2013-08-09 2017-03-28 Altera Corporation Integrated circuit package with vacant cavity
KR102471533B1 (ko) 2014-08-07 2022-11-28 인텔 코포레이션 패시브 평면형 디바이스를 갖는 rf 회로 장치 및 패시브 평면형 디바이스를 갖는 rf 회로 시스템
CN111146170A (zh) * 2019-12-30 2020-05-12 颀中科技（苏州）有限公司 封装结构及其成型方法
JP7468828B2 (ja) 2020-05-11 2024-04-16 住友電工デバイス・イノベーション株式会社 半導体装置の製造方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020132461A1 (en) * 2001-03-19 2002-09-19 Casio Computer Co., Ltd. Semiconductor device having bump electrodes with a stress dissipating structure and method of manufacturing the same
US20070184578A1 (en) * 2006-02-07 2007-08-09 Yaojian Lin Solder bump confinement system for an integrated circuit package
US20080054461A1 (en) * 2006-08-30 2008-03-06 Dennis Lang Reliable wafer-level chip-scale package solder bump structure in a packaged semiconductor device

Family Cites Families (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3429040A (en) * 1965-06-18 1969-02-25 Ibm Method of joining a component to a substrate
JP2653179B2 (ja) 1989-08-21 1997-09-10 富士電機株式会社 集積回路装置用バンプ電極の製造方法
US5220200A (en) * 1990-12-10 1993-06-15 Delco Electronics Corporation Provision of substrate pillars to maintain chip standoff
US5282565A (en) * 1992-12-29 1994-02-01 Motorola, Inc. Solder bump interconnection formed using spaced solder deposit and consumable path
JPH07240434A (ja) * 1994-03-02 1995-09-12 Oki Electric Ind Co Ltd バンプ電極、およびその製造方法
US5539153A (en) * 1994-08-08 1996-07-23 Hewlett-Packard Company Method of bumping substrates by contained paste deposition
US6232563B1 (en) * 1995-11-25 2001-05-15 Lg Electronics Inc. Bump electrode and method for fabricating the same
JP3751587B2 (ja) * 1996-07-12 2006-03-01 富士通株式会社 半導体装置の製造方法
AU5283399A (en) * 1998-07-15 2000-02-07 Fraunhofer-Gesellschaft Zur Forderung Der Angewandten Forschung E.V. Method for transferring solder to a device and/or testing the device
KR100269540B1 (ko) * 1998-08-28 2000-10-16 윤종용 웨이퍼 상태에서의 칩 스케일 패키지 제조 방법
US6583515B1 (en) * 1999-09-03 2003-06-24 Texas Instruments Incorporated Ball grid array package for enhanced stress tolerance
JP2001217340A (ja) * 2000-02-01 2001-08-10 Nec Corp 半導体装置及びその製造方法
US6444561B1 (en) * 2000-10-02 2002-09-03 Industrial Technology Research Institute Method for forming solder bumps for flip-chip bonding by using perpendicularly laid masking strips
US6800815B1 (en) * 2001-01-16 2004-10-05 National Semiconductor Corporation Materials and structure for a high reliability bga connection between LTCC and PB boards
JP2003100808A (ja) * 2001-09-27 2003-04-04 Matsushita Electric Ind Co Ltd 電子部品とその製造方法とその電子部品を実装した回路基板
JP3808365B2 (ja) * 2001-12-25 2006-08-09 シャープ株式会社 半導体装置およびその製造方法
US6541366B1 (en) 2002-01-08 2003-04-01 Taiwan Semiconductor Manufacturing Co., Ltd. Method for improving a solder bump adhesion bond to a UBM contact layer
JP3829325B2 (ja) * 2002-02-07 2006-10-04 日本電気株式会社 半導体素子およびその製造方法並びに半導体装置の製造方法
US7059512B2 (en) * 2002-11-06 2006-06-13 Ricoh Company, Ltd. Solder alloy material layer composition, electroconductive and adhesive composition, flux material layer composition, solder ball transferring sheet, bump and bump forming process, and semiconductor device
US6878633B2 (en) * 2002-12-23 2005-04-12 Freescale Semiconductor, Inc. Flip-chip structure and method for high quality inductors and transformers
JP4115832B2 (ja) * 2002-12-27 2008-07-09 東芝松下ディスプレイテクノロジー株式会社 半導体素子及び液晶表示パネル
JP2004288785A (ja) * 2003-03-20 2004-10-14 Sony Corp 導電突起の接合構造及び接合方法
US6835580B1 (en) * 2003-06-26 2004-12-28 Semiconductor Components Industries, L.L.C. Direct chip attach structure and method
US8129841B2 (en) * 2006-12-14 2012-03-06 Stats Chippac, Ltd. Solder joint flip chip interconnection
US7329951B2 (en) * 2005-04-27 2008-02-12 International Business Machines Corporation Solder bumps in flip-chip technologies
US7468545B2 (en) * 2005-05-06 2008-12-23 Megica Corporation Post passivation structure for a semiconductor device and packaging process for same
JP2007073681A (ja) * 2005-09-06 2007-03-22 Renesas Technology Corp 半導体装置およびその製造方法
CN100452377C (zh) * 2005-12-01 2009-01-14 联华电子股份有限公司 芯片与封装结构
CN100438008C (zh) * 2006-03-01 2008-11-26 南茂科技股份有限公司 高频集成电路封装构造及其制造方法
TWI302812B (en) * 2006-07-20 2008-11-01 Phoenix Prec Technology Corp Pcb electrical connection terminal structure and manufacturing method thereof
US20080122078A1 (en) * 2006-11-08 2008-05-29 Jun He Systems and methods to passivate on-die redistribution interconnects
US7601628B2 (en) * 2006-11-20 2009-10-13 International Business Machines Corporation Wire and solder bond forming methods
US7682959B2 (en) * 2007-03-21 2010-03-23 Stats Chippac, Ltd. Method of forming solder bump on high topography plated Cu
US7982311B2 (en) * 2008-12-19 2011-07-19 Intel Corporation Solder limiting layer for integrated circuit die copper bumps

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020132461A1 (en) * 2001-03-19 2002-09-19 Casio Computer Co., Ltd. Semiconductor device having bump electrodes with a stress dissipating structure and method of manufacturing the same
US20070184578A1 (en) * 2006-02-07 2007-08-09 Yaojian Lin Solder bump confinement system for an integrated circuit package
US20080054461A1 (en) * 2006-08-30 2008-03-06 Dennis Lang Reliable wafer-level chip-scale package solder bump structure in a packaged semiconductor device

Also Published As

Publication number Publication date
EP2359396A4 (en) 2018-01-10
WO2010080275A2 (en) 2010-07-15
EP2359396A2 (en) 2011-08-24
KR101242998B1 (ko) 2013-03-12
KR20110063811A (ko) 2011-06-14
US20100155946A1 (en) 2010-06-24
CN102171805B (zh) 2013-09-11
TW201030918A (en) 2010-08-16
US7982311B2 (en) 2011-07-19
WO2010080275A3 (en) 2010-09-10
JP2012505555A (ja) 2012-03-01
CN102171805A (zh) 2011-08-31

Similar Documents

Publication Publication Date Title
TWI476880B (zh) 用於積體電路之凸塊應力減輕層
US8101496B2 (en) Method of manufacturing ball grid array type semiconductor device
JP5544872B2 (ja) 半導体装置及びその製造方法
TWI517273B (zh) 具有支撐終端墊的半導體晶片
EP1482553A2 (en) Semiconductor device and manufacturing method thereof
US20120326299A1 (en) Semiconductor chip with dual polymer film interconnect structures
JP5385452B2 (ja) 半導体装置の製造方法
TWI451548B (zh) 佈線基板及其製造方法，暨半導體裝置
JP2006351766A (ja) 半導体装置及びその製造方法
TWI375501B (en) Circuit board and fabrication method thereof and chip package structure
US20230108516A1 (en) Semiconductor device
US20060049518A1 (en) Semiconductor device and method for manufacturing the same
JP2008218494A (ja) 半導体装置およびその製造方法
JP2004022898A (ja) 半導体装置及びその製造方法
JP2010157544A (ja) 半導体装置及びその製造方法、並びに電子機器
KR20170021712A (ko) 반도체 디바이스 및 그 제조 방법
JP2010092974A (ja) 半導体装置及びその製造方法、並びに電子装置
JP2005260079A (ja) 半導体装置及びその製造方法
TWI720735B (zh) 封裝結構及其製造方法
JPH11233669A (ja) 半導体装置の製造方法
JP2008066369A (ja) 半導体装置
JP2005129665A (ja) 半導体装置およびその製造方法
JP4769926B2 (ja) 半導体装置及びその製造方法
JP2011035353A (ja) 半導体装置およびその製造方法
CN115547853A (zh) 半导体封装及其制造方法