TWI517273B - 具有支撐終端墊的半導體晶片 - Google Patents
具有支撐終端墊的半導體晶片 Download PDFInfo
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- TWI517273B TWI517273B TW101107851A TW101107851A TWI517273B TW I517273 B TWI517273 B TW I517273B TW 101107851 A TW101107851 A TW 101107851A TW 101107851 A TW101107851 A TW 101107851A TW I517273 B TWI517273 B TW I517273B
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Description
本發明一般有關半導體加工,更特別是半導體晶片焊錫凸塊墊以及製造該半導體晶片焊錫凸塊墊之方法。
業經使用覆晶安裝方案數十年以將半導體晶片安裝至電路板,諸如,半導體晶片封裝基板。於許多傳統覆晶變體中,在半導體晶片之輸入/輸出(I/O)位置和電路板之對應的I/O位置之間建立複數個焊接點。在一個傳統製程中,焊錫凸塊係冶金接合(metallurgically bonded)至半導體之特定I/O位置或墊,而且所謂預錫(pre-solder)係冶金接合至電路板之對應的I/O位置。其後,使焊錫凸塊與預錫靠近,並且進行迴焊焊錫凸塊和預錫之一者或兩者之加熱程序以建立必要的焊接點。
在一個傳統製程中,焊錫凸塊連接至半導體晶片之特定I/O位置伴隨在靠近I/O位置之半導體晶片之頂層介電薄膜中形成開口,其後沉積金屬以建立凸塊底層金屬(UBM)結構。接著,藉由迴焊而使焊錫凸塊冶金接合至UBM結構。這傳統的UBM結構包含基極、側壁、以及位於介電薄膜上之上凸緣。
覆晶焊接點可受到各種來源之機械應力,諸如熱膨脹失配係數、延展性差異、以及電路板翹曲。此等應力可使剛描述之傳統UBM結構成彎曲力矩。此效應有些方向性,因為應力往往是在更靠近晶粒邊緣和角處為最大且隨著越
來越接近晶粒中心而減少。與此所謂邊緣效應相關之彎曲力矩可能對UBM結構下方之介電薄膜施加應力,若該應力夠大,則可能會產生破裂。
由於各種原因,設計者已開始轉向用於焊接點製造之無鉛焊錫。由此等焊錫所構成之凸塊可產生較相等尺寸之鉛凸塊更高的應力。為了彌補此更高的應力,傳統的設計在凸塊底層金屬和下方晶片凸塊墊之間併入終端墊。終端墊具有大於上方凸塊底層金屬與下方晶片焊墊之占晶面積(footprint),以提供鈍化層應力保護。若晶片提供靠近晶片焊墊之作用金屬線,則終端墊可與此等金屬線重疊,並且產生寄生電路(parasitics)。
本發明有關克服或減少一種或多種前述缺點之效應。
根據本發明之具體例之一個態樣,提供一種製造方法,包括提供具有第一導電體墊和鈍化結構之半導體晶片。第二導電體墊在第一導電體墊周圍製造,但不與第一導電體墊實體接觸以留下缺口。第二導電體適配於保護一部份之鈍化結構。
根據本發明之具體例之另一個態樣,提供一種耦合半導體晶片至電路板之方法。半導體晶片具有鈍化結構、彼此靠近但被聚合物層分離以留下缺口之第一和第二導電體墊,該第一導電體墊與延伸於該第二導電體墊上之凸塊底層金屬電性連接,但該凸塊底層金屬與該第二導電體墊被聚合物層分離。該方法包含耦合焊錫結構至凸塊底層金屬
結構,並且耦合焊錫結構至電路板。
根據本發明之具體例之另一個態樣,提供一種儀器,包含具有第一導電體墊與鈍化結構之半導體晶片。第二導電體墊係在第一導電體墊周圍,但不與第一導電體墊實體接觸以留下缺口。第二導電體墊適配於保護一部份之鈍化結構。
本文中揭露半導體晶片之多種具體例。一個實例包含在個別作用終端墊上製造之焊錫凸塊連接結構,諸如,UBM結構。在具有環繞之虛擬墊之晶片鈍化結構上製造作用終端墊,該晶片鈍化結構並無實體連接至作用終端墊。在不會產生與下方晶片作用導電體金屬線相關之寄生電容下,虛擬墊對鈍化結構提供保護。將於現在描述另外的細節。
於下述之圖式中,在超過一個圖式中出現相同元件處,通常重複元件符號。現在回到圖式,特別是第1圖,其中顯示包含安裝在電路板20上之半導體晶片15之半導體晶片裝置10之例示性具體例之圖式。底層填充(underfill)材料層25置於半導體晶片15與電路板20之間。本文中揭露之焊錫互連結構不取決於半導體晶片15或電路板20之特別功能性。因此,半導體晶片15可為電子學中所用之無數不同類型之電路裝置,諸如,例如,微處理器、圖形處理器、結合之微處理器/圖形處理器、應用特定性積體電路、記憶裝置或類似者中之任一者,而且可為單或多核心或甚至疊加另外的晶粒。半導體晶片15可為由散裝半導體
(諸如,矽或鍺)或絕緣材料上之半導體(諸如,絕緣材料上矽)所建構。半導體晶片15可覆晶安裝至電路板20,而且藉由焊接點或其他結構(未見於第1圖,但於後續圖式中顯示)電性連接至電路板20。
電路板20可為半導體晶片封裝結構、電路卡或幾乎任何其他類型之印刷電路板。雖然單晶結構可用於電路板20,更典型的組態將使用增建(built-up)設計。在這方面,電路板20可由中央核心所組成,根據此中央核心形成一層或多層增建層,且在其下形成另外的一層或多層增建層。核心本身由具有一或多層之堆疊物所組成。此排列之一個實例可稱為所謂“2-2-2”排列,其中單層核心在兩組增建層之間分層。若作為半導體晶片封裝基板實施,電路板20中之層數可為四至十六不等或更多,雖然可使用少於四層。亦可使用所謂“無核心”設計。電路板20之層可由以金屬互連點綴之絕緣材料(諸如,各種周知的環氧化物)所組成。可使用除了增建外之多層組構。視需要地,電路板20可由周知的陶瓷或其他適合封裝基板之材料所構成,或為其他印刷電路板。
電路板20提供有一些導電體金屬線和導孔(via)及其他結構,以在半導體晶片15和未顯示之另一個電路裝置之間提供電力、接地以及信號傳輸。為了促進彼等傳輸,電路板20可提供有針柵陣列、球柵陣列、地柵陣列或其他類型之互連方案之形式之輸入/輸出。
將結合第2圖描述半導體晶片15的另外細節,第2
圖為取第1圖之部分2-2之側面圖。在回到第2圖之前,將有助於注意將側面顯示之封裝10之部分之確切位置。注意部分2-2穿過包含邊緣30之一小部分半導體晶片15。在此背景下,讓注意力回到第2圖。如上所註明,半導體晶片15可組構成散裝半導體或絕緣體上半導體組態。於此闡釋性具體例中,半導體晶片15作為包含散裝半導體層35和半導體裝置層40之散裝半導體實施。半導體裝置層40包含提供半導體晶片15功能性之各種電路,而且將包含促進電力、接地和信號從半導體晶片15傳輸或傳輸至半導體晶片15之複數個金屬層及/或其他類型之導電體層。鈍化結構45形成在半導體裝置層40上,而且可由多層之絕緣材料所組成。將結合後續圖式描述關於鈍化結構45之細節。半導體晶片15可覆晶安裝至載體基板20,而且藉由複數個焊錫結構或焊接點(其中兩者為可見的,且分別標記為50和55)之方式電性連接至載體基板20。由於部分2-2之定位,僅有一部份之焊接點係可見的。
底膠填充材料層25分散於半導體晶片15和基板20之間,以減少半導體晶片15、焊接點50,55等、及電路板20之熱膨脹係數(CTE)之差值之效應。底膠填充材料層25可為,例如,與氧化矽填充物和苯酚樹脂混合之環氧樹脂,而且在迴焊程序之前或之後沉積以建立焊接點50和55。可使用適當的熱固化。
焊接點50之以下描述亦將闡釋其他焊接點。焊接點50包含冶金接合至另一個焊錫結構65之焊錫結構或凸塊
60,焊錫結構65有時稱為預錫。藉由焊錫迴焊程序之方式,使焊錫凸塊60和預錫65冶金結合。不規則線條70表示迴焊後在焊錫凸塊60和預錫65之間之假設性邊界。然而,熟練技術者將了解此邊界70甚至在顯微鏡檢驗時很少是隨時可見的。焊錫凸塊60可由各種鉛或無鉛焊錫所組成。例示性鉛焊錫可具有在或接近共晶比例之組成,諸如,約63% Sn和37% Pb。無鉛實例包含錫-銀(約97.3% Sn 2.7% Ag)、錫-銅(約99% Sn 1% Cu)、錫-銀-銅(約96.5% Sn 3% Ag 0.5% Cu)、或類似者。預錫65可由相同類型之材料所組成。視需要地,可移除預錫65,以有利於單一焊錫結構或焊錫加上導電柱排列。
焊錫凸塊60可冶金連接至另外稱為底層凸塊金屬或UBM結構之導電體結構75。一部份之UBM結構75突出通過置於鈍化結構45上之聚合物層80,而且與導電體或作用終端墊45歐姆接觸。另一部份之UBM結構75位於聚合物膜80之外表面上。聚合物膜80設計為提供貼合的保護膜,而因此可由各種材料所組成,諸如,聚亞胺、苯并環丁烯或類似者。作用終端墊85電性連接至晶片15中之另一個導電體結構或墊90,其可為半導體晶片15中之複數個金屬層之一部份之。的確,幾個此導電體或金屬線為可見的,且可分別標記為95,100。導電體墊85可作為電力、接地或信號之輸入/輸出位置使用,或可作為不與其他結構電性連接之虛置墊(dummy pad)使用。預錫65相同地冶金接合至橫向毗鄰焊錫遮罩115之導電體110。導電體結構110
可形成可為多層導電體結構且藉由導孔互連且由介電材料層環繞(未顯示)之部分。
作用終端墊85具有將隨著製程技術而變化之某些橫向維度X1。於傳統設計中,作用終端墊85會提供有更大的橫向維度X2,以幫助抵消焊錫凸塊60和焊接點50對鈍化結構45施加之機械應力。這些應力對於無鉛金屬而言可能特別高。若應力夠高,則鈍化結構45可能破裂,導致一大堆潛在的問題。然而,若以此寬橫向維度X2製造作用終端墊85,則確實與半導體晶片15之導電體金屬線100和105重疊,其可能產生寄生電容和電性性能中之對應的減少。為了在不造成明顯的寄生電容下對鈍化結構45提供充足的應力保護,以橫向維度X1建構作用終端墊85,也因此不會與導電體金屬線100和105重疊。此外,作用終端墊85由藉由缺口125而與作用終端墊分離之導電體或虛擬墊120橫向環繞。虛擬墊120與作用終端墊85電性絕緣。在此情況下,藉由在缺口125中之一部份之聚合物膜80提供電氣絕緣。若期望,虛擬墊120可為浮動的或與電力或接地耦合。
各種實體製程可能導致施加在鈍化結構45上之應力。一個原因為半導體晶片15、電路板20和底膠填充材料層25在熱循環過程中應變率之差異。差異的應力之另一個促成因素可能為焊錫凸塊60和預錫65之延展性差別。由於已知為邊緣效應之現象,這些差異的應力和所產生之應變可能在半導體15之邊緣30處為最大,並且可在箭頭130
所註明之指離邊緣30且指向半導體晶片15之中心之方向逐漸地減少。
為了幫助一些導致鈍化結構應力之例示性實體力量,第2圖之由橢圓虛線135所限制之部分將於第3圖中以更大的放大率顯示。雖然第3圖為側面圖,未顯示交叉線,致使能更清楚地描繪在有關結構上發揮之各種力量。於此,以下結構將為可見的:一小部分之半導體晶片15、凸塊墊90、鈍化結構45、聚合物膜80、作用終端墊85、虛擬墊120、UBM結構75、底膠填充材料層25、焊錫遮罩115、導電體墊110以及一小部分之電路板20。焊接點50顯示為虛線圖式。往半導體晶片15之中心之方向係由箭頭130所示。
由於基板20在製造、可靠性測試或裝置操作過程中之翹曲且主要由於CTE失配,基板20通過焊接點50展現由一系列向下指向之箭頭概要地表示之分佈負載。分佈負載的強度沿著長度L從最大的ω1至最小的ω0變化,其中ω1與ω0為每單位長度之力量單位。分佈負載之所產生之R位於x-軸上之X n 點。因為第3圖為側面圖,作用於UBM結構75上之分佈負載顯示為線分佈。實踐中,分佈負載將為面積分佈。作為以朝向中心之方向130沿著x-軸之距離作為函數之力量強度ω1至ω2之逐漸減少係由於本文之發明背景中所述之邊緣效應。所產生之R相對於角點A之位置產生以角點A為重心而作用於UBM結構75之力矩M。取決於UBM結構75之延展性和距離L,角點A可以在UBM結
構75之不欲的向下繞軸運動和點A為重心充當支點。由於力矩M,鈍化結構45之面積B可受到壓縮,而且相對面積C可為受到拉力。然而,虛擬墊120之存在提供面積B和C應力保護。
可藉由現在參照第4、5、6、7、8、9、10以及11圖及最初參照第4圖而了解製造例示性UBM結構75之例示性方法。第4圖為顯示半導體晶片15之一小部分半導體裝置層40、導電體墊90和金屬線100和105、以及鈍化結構45之側面圖。應了解第4圖描繪從第2和3圖之方向翻轉之半導體裝置層4和導電體墊90。應了解本文中所述之製程應可在晶圓層級或一個晶粒接著一個晶粒之基準上進行。在此階段,已形成半導體墊90和鈍化結構45。導電體墊90可由各種導電體材料所組成,諸如,鋁、銅、銀、金、鈦、耐火金屬、耐火金屬合物、這些者之合金或類似者所組成。代替單式結構,導電體墊90可由複數個金屬層之層板,諸如,鈦層、隨後鎳-釩層、隨後銅層所組成。於另一個具體例中,可以銅層覆蓋鈦層,隨後以鎳之頂塗覆層覆蓋。然而,熟練技術者將了解可使用更多種導電材料於導電體墊90。可使用施加金屬材料之各種周知技術,諸如,物理氣相沉積、化學氣相沉積、鍍覆或類似者。應了解可使用另外的導電體結構。
鈍化結構可由具有交替層之介電材料所組成,諸如,二氧化矽和氮化矽,而且可藉由周知的化學氣相沉積(CVD)及/或氧化或氧化技術形成。可在鈍化結構45上形成適合
的微影遮罩140,而且以對準導電體墊90之適合的開口圖案化之周知的微影步驟。其後,可進行一個或多個材料移除步驟以在鈍化結構45中產生開口150,致使導電體墊90曝光。例如,材料移除步驟可包含適合選擇用於鈍化結構45之特定材料之一個或多個乾/或濕蝕刻製程。材料移除以產生開口150後,可藉由灰化剝除或溶劑剝除遮罩140。
在鈍化結構45中確立開口150且曝光導電體墊90,可進行作用終端墊85、虛擬墊120、以及聚合物膜80之製造。可以各種順序進行這些步驟。例如,可在作用終端墊85和虛擬墊120製造之前或之後施加聚合物膜80。於此闡釋性具體例中且現在參照第5圖,可在施加第2圖所示之聚合物膜80之前製造作用終端墊85和虛擬墊120。藉由物理氣相沉積、鍍覆或其他材料形成技術,可在鈍化結構45上形成作用終端墊85和虛擬墊120。可使用對鈍化結構展現有利的附著力且與其他導電體冶金接合之各種導電體材料。的確,亦可將結合導電體結構90描述之相同類型之材料和技術用於作用終端墊85與虛擬墊120。於這例示性具體例中,可藉由物理氣相沉積銅隨後進行適合的蝕刻,諸如,磷酸濕式蝕刻,而形成作用終端墊85和終端墊120。任何所使用之製造程序應確保作用終端墊85與虛擬墊120之間之缺口係連續的,以避免短路。一部份之作用終端墊85填滿鈍化結構45中之開口150,並且與下方導電體墊90形成冶金接合。若需要,可進行初步自然氧化物剝除,以確保導電體墊90之表面足以暴露而能與下方之作用終
端墊85冶金接合。
第6圖為製造後作用終端墊85與虛擬墊120之頂視圖。於此闡釋性具體例中,作用終端墊85與虛擬墊120可能具有所顯示之大略呈圓和環之形狀。作用終端墊85與虛擬墊120之間之缺口120係連續的。然而,應了解可使用圓形或環形除外之占晶面積。甚至可與虛擬墊120一起使用分段結構。
如第7圖中所示,接著在作用終端墊85、虛擬墊120和鈍化結構45之曝光部分上施加聚合物膜80。聚合物膜80可由聚亞胺、苯并環丁烯或類似者所組成,或可為其他絕緣材料,諸如,氮化矽獲類似者,而且可藉由旋塗、CVD或其他技術沉積。在施加後,可進行固化烘烤過程。若使用其中最先施加聚合物層80之另外的程序,則將需要在聚合物層80中確立適合的開口(未顯示)以製造作用終端墊85與虛擬墊120。取決於聚合物膜80之組成,這可以多種方法達成。聚亞胺聚合物膜80可注入經微影圖案化之光活性化合物,並且進行材料沉積或鍍覆程序。若聚合物層80無法藉由曝光和顯影之方式移除材料,接著可施加適合的微影遮罩,並且進行蝕刻以產生必要的開口。將於現在描述結構之製造,以從半導體區域40、導電體墊90、及作用終端墊85確立電性通路。
現在參照第8圖,可將聚合物膜80微影圖案化以確立第2圖所示之後來形成之UBM結構75之適合的開口。取決於聚合物膜80之組成,這可以多種方式完成。聚亞胺聚
合物膜80可注入經微影圖案化之光活性化合物,並且進行材料沉積或鍍覆程序。於此闡釋性具體例中,聚合物膜80含有光活性化合物。非接觸之遮罩155以對準作用終端墊85之方式置於聚合物膜80上,但不會覆蓋虛擬墊120。接著,以適當的輻射160進行曝光。未以遮罩155覆蓋之聚合物膜80之部分變得不溶於顯影溶液。現在參照第9圖,移除第8圖中所示之非接觸之遮罩155,並且將聚合物膜80顯影以產生暴露一部份之通常與作用終端墊85對準之開口165。虛擬墊120保持覆蓋。若聚合物層80不能藉由曝光和顯影之方式移除材料,接著可施加適合的微影遮罩,並且進行蝕刻以產生必要的開口。
將於現在結合第10圖描述UBM結構75之製造。熟悉技術者將了解UBM結構係設計成滿足幾個重要目標,即,與上方焊錫凸塊或其他焊錫結構接合,以和下方導電體結構確立導電介面(在此情況下為作用終端墊85),以在需要時與下方或周圍之介電質接合,其均對焊錫組分擴散入下方導電體結構提供屏障,否則會使彼等導電體結構退化。為了滿足這些材料要求,取決於焊錫施加程序之類型,UBM結構可使用不同組成之多層膜。於此闡釋性具體例中,UBM結構75可形成為一系列連續施加之膜。至於印刷焊錫凸塊,可在聚合物膜80上、及沿著開口165之側壁、及於作用終端墊85上濺鍍沉積最初的鈦或鈦-鎢膜。鈦膜作為容易黏著於聚合物膜80之黏著層。其次,將由鎳、鎳-釩或其他材料所組成之屏障層鍍覆,或在鈦膜上另行沉積其他
材料。最後,藉由鍍覆、濺鍍沉積或其他技術,將由銅、金或其他材料所組成之焊錫-可濕性層施加至鎳膜。沉積材料之後,進行濕式蝕刻以產生第10圖所示之經圖案化之UBM 75。然而,在使用凸塊鍍覆程序以建立之後形成之焊錫凸塊之情形下,則UBM結構75可由上述類型之黏著層所組成,然後為鍍覆晶種層(諸如,藉由無電鍍覆或濺鍍沉積而沉積之銅),然後為上述類型之鎳或鎳-釩屏障層。至於經鍍覆之凸塊程序,可同樣地進行濕式蝕刻。然而,鎳之屏障層可能不需要蝕刻圖案化。
UBM結構75在適當的位置時,如第11圖所示,可在UBM結構75上印刷、鍍覆或另外置放適當的焊錫材料170。概要地描繪之焊錫材料170預訂成為第2圖中所描繪之焊錫凸塊60。為了建立第2圖中所描繪之焊錫凸塊60,可結合經沉積之焊錫170使用多種程序。於一個闡釋性具體例中,使用印刷程序。在這點上,可在聚合物層80上施加適當的微影遮罩(未顯示)。接著,藉由網印程序,沉積焊錫170。於一個另外的例示性具體例中,可使用鍍覆程序。在這方面,可形成具有開口以暴露UBM結構75之適當的微影遮罩,其並非不同於前述遮罩(但未顯示)。於此階段,可在UBM結構75上鍍覆焊錫170。無視於施加技術,然後進行半導體晶片15之熱迴焊以建立第2圖所示之凸塊60。
第12和13圖描繪UBM結構之具體例之連續平面圖。第12圖描繪具有大略八角形之占晶面積之UBM結構75。注意僅一小部分的聚合物膜80是可見的。第13圖描繪具
有大略圓形之占晶面積之另外的UBM結構75’之平面圖。再次,僅描繪一小部分的聚合物膜80。當然,UBM結構75和75’可具有呈現多種不同類型之占晶面積。
第14圖為類似第3圖之側面圖,但為另外的例示性具體例之側面圖且包含傳統的交叉法。這例示性具體例具有許多本文中其他處所述之具體例之相同特徵,並且概要地描繪於第2圖中。因此,半導體晶片15包含複數個導電體墊15(顯示其中之一者,並將其標記為90)以及作用金屬線100和105。鈍化結構45以在導電體100和105上面之方式置於半導體晶片15上,並且至少部分在半導體墊90上面。可將作用終端墊85和虛擬墊120組構和製造為本文中其他處之一般描述。重要的警告為聚合物膜80’可以本文中其他處所述之同樣方式製造。於此闡釋性具體例中,可製造具稍小厚度之聚合物膜80’,致使僅一小部分的聚合物膜80’覆蓋虛擬墊120。然而,這闡釋性具體例包含設計為在UBM結構75和另外會靠向鈍化結構之置於缺口125中之一部份之聚合物膜80’中之相對貼合的材料之間提供應力支撐之第二虛擬墊180。可結合第4至8圖而通常進行第14圖所揭露之具體例之製造,但有顯著的差異。於與第8圖相關之流程中,聚合物膜80具有在作用終端墊85與虛擬墊120之上之相當的材料厚度。至於目前另外的具體例,聚合物膜80’係相對較薄,致使在作用終端墊85和虛擬墊120上有更薄的塗層。在這階段且如第15圖中所描繪,可使用相同類型之技術在聚合物膜80’上製造第二
虛擬膜180,以製造作用終端墊85和虛擬墊120,即,物理氣相沉積、鍍覆或其他材料施加技術以及本文中其他處所述之材料塑形技術。注意第二虛擬墊180可在缺口上,以保護鈍化結構。就占晶面積而論,第二虛擬墊180可為顯示之環狀或其他形狀。只要作用終端墊85未縮短,第二虛擬墊180可與虛擬墊120機械綑綁。
現在參照第16圖,製造第二虛擬墊180後,可使用本文中其他處所述之形成聚合物膜80和80’之材料與技術,在聚合物膜80’上形成另外的聚合物膜185。其後,可結合第9至11圖,以流程追蹤本文中所述之技術,以建立UBM結構75和焊錫凸塊60以及與作用終端墊85(但並非虛擬墊120)之連接,電路板20之安裝、以預錫65和底膠填充25沉積建立焊接點50。
第17圖描繪類似第14圖之側面圖,但為另一個替換的例示性具體例之具體例。這換代的具體例具有第14圖所描繪之具體例之許多相同特徵,即,半導體晶片15、導電體墊90、導電體金屬線100和105、作用終端墊85、終端墊120以及相對較薄的聚合物膜80’。然而,為了提供與缺口125中之貼合的材料相關之應力之期望保護程度,可將第14圖中描繪之第二虛擬墊180轉化成本質上為非虛擬導電體墊190,其具有中央接觸位置195以與作用終端墊85建立歐姆接觸與設計成置於靠近缺口125之聚合物膜80’上以提供必要的應力保護之凸緣部分200。建立第17圖中描繪之另外的具體例之流程可結合第4至8圖再度追
蹤本文中其他處所述之流程,前提為製造具有較第8圖中所描繪者相對更小厚度之聚合物膜80’。在這階段,應在聚合物膜80’中形成適當的開口,其後利用材料沉積或鍍覆程序製造墊190。沉積及/或鍍覆程序後,可藉由蝕刻或其他材料移除技術將墊190圖案化至所描繪之組態,其後可在聚合物膜80’和導電體墊190上形成另外的聚合物膜185。在這階段,製造UBM結構75與焊錫凸塊60及連接至作用終端墊但並非虛擬墊120,包含安裝電路板20之安裝、以預錫65和底膠填充25沉積建立焊接點50。
本文中所揭露之任何例示性具體例可在電腦可讀取媒介中所設置(例如,半導體、磁碟、光碟或其他儲存媒介或作為電腦數據訊號)之指令中具體化。本文中揭露能合成及/或模擬電路結構之指令或軟體。在例示性具體例中,可使用電子設計自動程式,諸如,Cadence APD、Encore或類似者,合成所揭露之電路結構。所產生之字碼可用以製造所揭露之電路結構。
雖然本發明可能容易進行各種修飾和替換的形式,已藉由圖式中之實施例之方式顯示特定具體例且已於本文中詳細描述。然而,應了解本發明不意欲受限於所揭露之特定形式。而是,本發明為涵蓋所有落入以下附加的申請專利範圍所界定之本發明之精神和範疇內之修飾、均等物以及替換物。
10‧‧‧半導體晶片裝置
15‧‧‧半導體晶片
20‧‧‧基板、電路板
25‧‧‧底層填充材料層
30‧‧‧邊緣
35‧‧‧散裝半導體層
40‧‧‧半導體裝置層、半導體區域
45‧‧‧鈍化結構
50、55‧‧‧焊接點
60‧‧‧焊錫凸塊
65‧‧‧預錫、焊錫結構
70‧‧‧邊界
75/75’‧‧‧UBM結構
80/80’/185‧‧‧聚合物膜、聚合物層
85‧‧‧作用終端墊、導電體墊
90‧‧‧導電體墊、導電體結構、凸墊塊
95/100/105‧‧‧導電體/金屬線
110‧‧‧導電體結構、導電體、導電體墊
115‧‧‧焊錫遮罩
120‧‧‧虛擬墊、第二導電體墊
125‧‧‧缺口
130‧‧‧箭頭
135‧‧‧橢圓虛線
140‧‧‧微影遮罩、遮罩
145/150/165‧‧‧開口
155‧‧‧非接觸遮罩
在閱讀以下詳細描述時和參照圖式時,本發明之前述
與其他優點將變成顯而易見的,其中:
第1圖為包含安裝在電路板上之半導體晶片之半導體晶片裝置之例示性具體例之圖式。
第2圖為取第1圖之2-2部分之側面圖。
第3圖為以更大的放大率顯示之第2圖之一部份。
第4圖為描繪半導體晶片之導電體結構之開口之例示性形成之側面圖。
第5圖為類似第4圖之側面圖,但描繪例示性作用終端墊與虛擬墊之製造。
第6圖為例示性作用終端墊與虛擬墊之平面圖。
第7圖為類似第5圖之側面圖,但描繪在例示性作用終端和虛擬墊上施加聚合物膜。
第8圖為類似第7圖之側面圖,但描繪聚合物膜之例示性微影遮罩與曝光。
第9圖為類似第8圖之側面圖,但描繪在聚合物膜中之開口之例示性微影製造。
第10圖為類似第9圖之側面圖,但描繪例示性凸塊底層金屬結構之製造。
第11圖為類似第10圖之側面圖,但概要地描繪焊錫結構在凸塊底層金屬結構上之形成。
第12圖為例示性凸塊底部金屬結構之平面圖。
第13圖為替換的例示性凸塊底部金屬結構之平面圖。
第14圖為類似第3圖之側面圖,但為半導體晶片之替換的例示性具體例之側面圖。
第15圖為描繪例示性作用終端和虛擬墊、聚合物膜以及另外的虛擬墊之製造之側面圖。
第16圖為類似第15圖之側面圖,但描繪例示性另外的聚合物膜在第一聚合物膜之製造。
第17圖為類似第3圖之側面圖,但為半導體晶片之另一個替換的例示性具體例之側面圖。
10‧‧‧半導體晶片裝置
15‧‧‧半導體晶片
20‧‧‧電路板
25‧‧‧底層填充材料層
30‧‧‧邊緣
Claims (24)
- 一種製造半導體晶片之方法,包括:提供具有第一導電體墊之半導體晶片,其中,該第一導電體墊形成在鈍化結構下;在該鈍化結構上及該第一導電體墊周圍製造第二導電體墊,但該第二導電體墊不與該第一導電體墊實體接觸以留下缺口;以及製造與該第一導電體墊電性接觸之凸塊底層金屬結構,該凸塊底層金屬結構包含與該第二導電體墊垂直重疊之部分,藉以可操作該第二導電體墊以保護該鈍化結構之部分不受由該重疊部分給予之應力。
- 如申請專利範圍第1項所述之方法,其中,該第二導電體墊完全地延伸環繞該第一導電體墊。
- 如申請專利範圍第1項所述之方法,其中,該凸塊底層金屬結構具有八角形之占晶面積。
- 如申請專利範圍第1項所述之方法,包括將焊錫結構耦合至該凸塊底層金屬結構。
- 如申請專利範圍第4項所述之方法,其中,該焊錫結構包括焊錫凸塊和焊接點之一者。
- 如申請專利範圍第4項所述之方法,包括將電路板電性耦合至該焊錫結構。
- 如申請專利範圍第6項所述之方法,其中,該電路板包括半導體晶片封裝基板。
- 如申請專利範圍第1項所述之方法,包括使用儲存於電 腦可讀取媒介中之指令形成該第一與第二導電體墊。
- 如申請專利範圍第1項所述之方法,其中,包括在該半導體晶片上製造聚合物膜,以及在靠近該缺口之該聚合物膜上製造第三導電體墊以保護靠近該缺口之一部分之該鈍化結構。
- 如申請專利範圍第9項所述之方法,其中,該第三導電體墊不與該第二導電體墊實體接觸。
- 一種將半導體晶片耦合至電路板之方法,該半導體晶片具有鈍化結構、第一導電體墊、靠近該第一導電體墊之第二導電體墊,其中,該第一導電體墊形成在該鈍化結構下,該第一與第二導電體墊被聚合物膜分離以留下缺口,該第一導電體墊與延伸於該第二導電體墊上且垂直重疊該第二導電體墊之凸塊底層金屬結構電性接觸,但該凸塊底層金屬結構與該第二導電體墊被該聚合物膜分離,包括:將焊錫結構耦合至該凸塊底層金屬結構;以及將該焊錫結構耦合至該電路板。
- 如申請專利範圍第11項所述之方法,其中,該焊錫結構包括焊錫凸塊與焊接點之一者。
- 如申請專利範圍第11項所述之方法,其中,該將焊錫結構耦合至該電路板包括將該焊錫結構耦合至與該電路板耦合之預錫。
- 如申請專利範圍第11項所述之方法,其中,該電路板包括半導體晶片封裝基板。
- 如申請專利範圍第11項所述之方法,包括在靠近該缺口之該聚合物膜上製造第三半導體墊,以保護靠近該缺口之一部分之該鈍化結構。
- 如申請專利範圍第15項所述之方法,其中,該第三導電體墊不與該第二導電體墊實體接觸。
- 一種半導體儀器,包括:半導體晶片,其具有第一導電體墊,其中,該第一導電體墊形成在鈍化結構下;第二導電體墊,其在該鈍化結構上及該第一導電體墊周圍,但並非與該第一導電體墊實體接觸以留下缺口;以及凸塊底層金屬結構,其與該第一導電體墊電性接觸,該凸塊底層金屬結構包含與該第二導電體墊垂直重疊之部分,藉以可操作該第二導電體墊以保護該鈍化結構之部分不受由該重疊部分給予之應力。
- 如申請專利範圍第17項所述之半導體儀器,其中,該第二導電體墊完全地延伸環繞該第一導電體墊。
- 如申請專利範圍第17項所述之半導體儀器,其中,該凸塊底層金屬結構具有八角形之占晶面積。
- 如申請專利範圍第19項所述之半導體儀器,包括耦合至該凸塊底層金屬結構之焊錫結構。
- 如申請專利範圍第20項所述之半導體儀器,其中,該焊錫結構包括焊錫凸塊與焊接點之一者。
- 如申請專利範圍第17項所述之半導體儀器,包括耦合 至該半導體晶片之電路板。
- 如申請專利範圍第17項所述之半導體儀器,包括在該半導體晶片上之聚合物膜與靠近該缺口之該聚合物膜上之第三導電體墊以保護靠近該缺口之一部分之該鈍化結構。
- 如申請專利範圍第23項所述之半導體儀器,其中,該第三導電體結構不與該第二導電體結構實體接觸。
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CN103460379A (zh) | 2013-12-18 |
WO2012134710A8 (en) | 2012-12-06 |
KR101508669B1 (ko) | 2015-04-07 |
JP5764256B2 (ja) | 2015-08-19 |
WO2012134710A1 (en) | 2012-10-04 |
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