JP5385452B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims description 136
- 238000004519 manufacturing process Methods 0.000 title claims description 54
- 239000004020 conductor Substances 0.000 claims description 174
- 239000002184 metal Substances 0.000 claims description 82
- 229910052751 metal Inorganic materials 0.000 claims description 82
- 238000000034 method Methods 0.000 claims description 40
- 239000000758 substrate Substances 0.000 claims description 40
- 238000005530 etching Methods 0.000 claims description 14
- 238000007747 plating Methods 0.000 description 29
- 230000008569 process Effects 0.000 description 26
- 239000010949 copper Substances 0.000 description 19
- 238000001039 wet etching Methods 0.000 description 16
- 230000001681 protective effect Effects 0.000 description 12
- 229910000679 solder Inorganic materials 0.000 description 12
- 239000000463 material Substances 0.000 description 10
- 238000007796 conventional method Methods 0.000 description 9
- 238000007772 electroless plating Methods 0.000 description 8
- 238000009713 electroplating Methods 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 6
- 229920003986 novolac Polymers 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 5
- 230000015556 catabolic process Effects 0.000 description 5
- 238000006731 degradation reaction Methods 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 239000003795 chemical substances by application Substances 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
- 239000004642 Polyimide Substances 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 239000007788 liquid Substances 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 229920001721 polyimide Polymers 0.000 description 3
- 238000004380 ashing Methods 0.000 description 2
- 230000007797 corrosion Effects 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 230000003628 erosive effect Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 230000035882 stress Effects 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 230000008646 thermal stress Effects 0.000 description 2
- 238000009736 wetting Methods 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000001953 recrystallisation Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
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Description
図1は、本発明の第1実施形態における半導体装置の製造工程のフローチャートである。図2A〜図2Rに示す各図は、本第1実施形態における各製造工程での半導体装置の状態を示す断面図又は平面図である。
図3は、本発明の第2実施形態における半導体装置の製造工程のフローチャートである。図4A〜図4Iは、本第2実施形態における各製造工程での半導体装置の状態を示す断面図又は平面図である。本第2実施形態において、第3導電材層406及び第4導電材層401の形成までの工程は、図2A〜図2Hにて説明した前記第1実施形態の第1導電材層209及び第2導電材層210の形成までの工程と同じ工程である。なお、第2実施形態において、第1実施形態と同じ部材については同じ符号を付けて説明を省略する。
Claims (4)
- 基板の表面と前記基板に形成された穴部とに下地導電部材を形成し、
前記下地導電部材上の前記穴部を少なくとも除く領域にレジストを形成し、
前記レジストが形成されていない部分に導電材層を形成した後、前記導電材層上にマスクメタルを形成する前に、前記レジストをその膜厚が前記導電材層の膜厚より薄くなるまで除去し、
途中まで除去された前記レジストにより前記下地導電部材の表面を保護した状態で前記導電材層上及び前記導電材層の側部の端面にマスクメタルを形成し、
前記マスクメタルを形成した後、途中まで除去された前記レジストを除去し、
前記マスクメタルをマスクとして前記下地導電部材をエッチングして、前記導電材層を所定の形状に形成する、
半導体装置の製造方法。 - 前記レジストが形成されていない部分に前記導電材層を形成するとき、前記基板に形成された前記穴部内の側壁及び底面にも前記導電材層を形成すると共に、
前記導電材層上及び前記導電材層の前記側部の前記端面に前記マスクメタルを形成するとき、前記穴部内の前記側壁及び前記底面に形成された前記導電材層上にも前記マスクメタルを形成する、
請求項1に記載の半導体装置の製造方法。 - 前記マスクメタルを形成するとき、前記導電材層により構成される電極パッド部にキャップメタルを形成する、
請求項1に記載の半導体装置の製造方法。 - 前記マスクメタルが、Niの下地層と、前記下地層の上のAu層とで形成される、
請求項1に記載の半導体装置の製造方法。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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JP2012504297A JP5385452B2 (ja) | 2010-03-09 | 2011-02-17 | 半導体装置の製造方法 |
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Application Number | Priority Date | Filing Date | Title |
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JP2010051516 | 2010-03-09 | ||
JP2010051516 | 2010-03-09 | ||
PCT/JP2011/000864 WO2011111308A1 (ja) | 2010-03-09 | 2011-02-17 | 半導体装置の製造方法及び半導体装置 |
JP2012504297A JP5385452B2 (ja) | 2010-03-09 | 2011-02-17 | 半導体装置の製造方法 |
Publications (2)
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JPWO2011111308A1 JPWO2011111308A1 (ja) | 2013-06-27 |
JP5385452B2 true JP5385452B2 (ja) | 2014-01-08 |
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JP2012504297A Active JP5385452B2 (ja) | 2010-03-09 | 2011-02-17 | 半導体装置の製造方法 |
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US (1) | US8349736B2 (ja) |
EP (1) | EP2546868B1 (ja) |
JP (1) | JP5385452B2 (ja) |
CN (1) | CN102473639B (ja) |
WO (1) | WO2011111308A1 (ja) |
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JP5541233B2 (ja) * | 2011-06-06 | 2014-07-09 | Tdk株式会社 | 半導体チップの製造方法 |
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CN102473639A (zh) | 2012-05-23 |
EP2546868A1 (en) | 2013-01-16 |
WO2011111308A1 (ja) | 2011-09-15 |
JPWO2011111308A1 (ja) | 2013-06-27 |
EP2546868B1 (en) | 2020-01-08 |
CN102473639B (zh) | 2017-09-15 |
US20120115323A1 (en) | 2012-05-10 |
US8349736B2 (en) | 2013-01-08 |
EP2546868A4 (en) | 2014-04-09 |
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