JP2019083250A - 半導体装置及び半導体装置の製造方法 - Google Patents
半導体装置及び半導体装置の製造方法 Download PDFInfo
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- JP2019083250A JP2019083250A JP2017209319A JP2017209319A JP2019083250A JP 2019083250 A JP2019083250 A JP 2019083250A JP 2017209319 A JP2017209319 A JP 2017209319A JP 2017209319 A JP2017209319 A JP 2017209319A JP 2019083250 A JP2019083250 A JP 2019083250A
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- conductive member
- insulating film
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
- H01L2224/13111—Tin [Sn] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
Abstract
Description
11 半導体基板
20 下層絶縁膜
30 再配線
30A 窪み部
31 UBM膜
31a 密着層
31b シード層
32 第1の導電膜
33 第2の導電膜
40 上層絶縁膜
50 外部接続端子
Claims (13)
- 半導体基板上に設けられた第1の導電部材と、前記第1の導電部材の表面に設けられ且つ前記第1の導電部材よりもイオン化傾向が小さい第2の導電部材と、を含む配線を備え、
前記第1の導電部材の、前記第2の導電部材側の第1の面の幅は、前記第1の導電部材の、前記半導体基板側の第2の面の幅よりも狭く、
前記第2の導電部材の幅は、前記第1の導電部材の前記第1の面における幅よりも広く且つ前記第1の導電部材の前記第2の面における幅よりも狭い
半導体装置。 - 前記半導体基板と前記配線との間に設けられた第1の絶縁膜と、
前記第1の絶縁膜及び前記配線を覆う第2の絶縁膜と、
を更に含む
請求項1に記載の半導体装置。 - 前記配線は、前記第1の絶縁膜に形成された開口部を介して、前記半導体基板に形成された電極に接続され、前記第2の絶縁膜に形成された開口部を介して外部接続端子に接続されている
請求項2に記載の半導体装置。 - 前記配線は、前記第1の導電部材と前記第2の導電部材との界面の周辺領域に、前記配線の幅方向内側に向けて窪んだ窪み部を有し、
前記第2の絶縁膜が、前記窪み部に侵入している
請求項2または請求項3に記載の半導体装置。 - 前記第1の導電部材と、前記第1の絶縁膜との間に設けられた導電膜を更に含む
請求項2から請求項4のいずれか1項に記載の半導体装置。 - 前記第1の導電部材は、前記第2の面の側に設けられたベース部と、前記第1の面の側に設けられた狭小部と、を有し、
前記ベース部の側壁は、前記半導体基板の主面に対して垂直であり、前記ベース部の上面は、前記半導体基板の主面に対して平行であり、
前記ベース部の上面に接続された前記狭小部の底部の幅は、前記ベース部の上面の幅よりも狭く、前記狭小部の断面形状が順テーパ形状である
請求項1から請求項5のいずれか1項に記載の半導体装置。 - 前記第1の導電部材は、Cuを含み、
前記第2の導電部材は、Auを含む
請求項1から請求項6のいずれか1項に記載の半導体装置。 - 半導体基板の表面に第1の絶縁膜を形成する工程と、
第1の絶縁膜の表面にシード層を形成する工程と、
前記シード層を介して通電を行う電界めっき法によって、前記第1の絶縁膜の表面に第1の導電部材を形成する工程と、
前記シード層を介して通電を行う電界めっき法によって、前記第1の導電部材の表面に、前記第1の導電部材の幅よりも狭い幅を有し且つ前記第1の導電部材よりもイオン化傾向が小さい第2の導電部材を、前記第1の導電部材の内側に形成する工程と、
エッチングにより前記シード層を除去する工程と、
を含む
半導体装置の製造方法。 - 前記第1の絶縁膜に第1の開口部を形成する工程を更に含み、
前記第1の導電部材及び前記第2の導電部材を含む配線を、前記第1の開口部を介して、前記半導体基板に形成された電極に接続する
請求項8に記載の製造方法。 - 前記シード層を除去する工程において、前記第1の導電部材及び前記第2の導電部材を含む配線の、前記第1の導電部材と前記第2の導電部材との界面の周辺領域に、前記配線の幅方向内側に向けて窪んだ窪み部を形成する
請求項8または請求項9に記載の製造方法。 - 前記第1の絶縁膜及び前記配線を覆う第2の絶縁膜を形成する工程を更に含み、
前記第2の絶縁膜は、前記窪み部に侵入している
請求項10に記載の製造方法。 - 前記配線の表面を部分的に露出させる第2の開口部を、前記第2の絶縁膜に形成する工程と、
前記配線の前記第2の開口部から露出した部分に、外部接続端子を形成する工程と、
を更に含む
請求項11に記載の製造方法。 - 前記第1の導電部材は、Cuを含み、
前記第2の導電部材は、Auを含む
請求項8から請求項12のいずれか1項に記載の製造方法。
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