JP4055015B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP4055015B2 JP4055015B2 JP2005107315A JP2005107315A JP4055015B2 JP 4055015 B2 JP4055015 B2 JP 4055015B2 JP 2005107315 A JP2005107315 A JP 2005107315A JP 2005107315 A JP2005107315 A JP 2005107315A JP 4055015 B2 JP4055015 B2 JP 4055015B2
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- 239000004065 semiconductor Substances 0.000 title claims description 134
- 238000004519 manufacturing process Methods 0.000 title claims description 59
- 238000000034 method Methods 0.000 claims description 58
- 239000000758 substrate Substances 0.000 claims description 34
- 238000007599 discharging Methods 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims description 3
- 239000011347 resin Substances 0.000 claims description 3
- 229920005989 resin Polymers 0.000 claims description 3
- 238000004544 sputter deposition Methods 0.000 claims description 3
- 239000000463 material Substances 0.000 description 24
- 238000010586 diagram Methods 0.000 description 11
- 239000002904 solvent Substances 0.000 description 8
- 238000002161 passivation Methods 0.000 description 4
- 239000002612 dispersion medium Substances 0.000 description 3
- 239000010419 fine particle Substances 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- 229920001721 polyimide Polymers 0.000 description 3
- 239000009719 polyimide resin Substances 0.000 description 3
- 230000003014 reinforcing effect Effects 0.000 description 3
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 230000001678 irradiating effect Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 229920002577 polybenzoxazole Polymers 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000000379 polymerizing effect Effects 0.000 description 1
- 239000002243 precursor Substances 0.000 description 1
- 230000002787 reinforcement Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
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Description
前記半導体基板上に設けられてなり、前記半導体基板と対向する第1の面とは反対側の第2の面に形成された溝を有する絶縁層と、
前記絶縁層上に設けられた導電部と、
を有し、
前記導電部は、前記溝の底面及び側面と接触するように形成された配線部を有する。本発明によると、配線部は、溝の底面及び側面と接触するように形成されてなる。これによると、配線部と溝との接触面積を広くすることができる。そのため、配線部と溝部との密着性を高めることができる。そのため、本発明によると、配線を微細化した場合でも配線部の剥離が生じにくい、信頼性の高い半導体装置を提供することができる。
(2)この半導体装置において、
前記配線部は、前記溝の内側のみに形成されていてもよい。
(3)この半導体装置において、
前記溝に沿って、前記配線部を覆うように形成された絶縁膜をさらに有してもよい。
(4)この半導体装置において、
前記導電部は、前記配線部に電気的に接続された電気的接続部を有してもよい。
(5)この半導体装置において、
前記電気的接続部は、前記絶縁層の第2の面上に形成されていてもよい。
(6)この半導体装置において、
前記絶縁層には、前記溝に連通された凹部が形成されてなり、
前記電気的接続部は、前記凹部の内側に形成されていてもよい。
(7)この半導体装置において、
前記電気的接続部上に形成された外部端子をさらに有してもよい。
(8)この半導体装置において、
前記絶縁層上に設けられてなり、前記絶縁層と対向する面とは反対側の面に形成された第2の溝を有する第2の絶縁層と、
前記第2の絶縁層上に設けられた第2の導電部と、
をさらに有し、
前記第2の導電部は、前記第2の溝の底面及び側面と接触するように形成された第2の配線部を有してもよい。
(9)この半導体装置において、
前記絶縁層には、貫通穴が形成されてなり、
前記溝は、前記貫通穴に連通されていてもよい。
(10)本発明に係る半導体装置の製造方法は、半導体基板上に、前記半導体基板と対向する第1の面とは反対側の第2の面に溝を有するように、絶縁層を形成すること、及び、
前記絶縁層上に、配線部を有する導電部を、前記配線部が前記溝の底面及び側面と接触するように形成することを含む。本発明によると、配線部の剥離が生じにくい、信頼性の高い半導体装置を製造することができる。
(11)この半導体装置の製造方法において、
前記配線部を、前記溝の内側のみに形成してもよい。
(12)この半導体装置の製造方法において、
前記溝に沿って、前記配線部を覆う絶縁膜を形成することをさらに含んでもよい。
(13)この半導体装置の製造方法において、
前記絶縁膜を形成する工程は、
前記配線部を覆うように絶縁ペーストを設けること、及び、
前記絶縁ペーストを硬化させることを含んでもよい。これによると、効率よく半導体装置を製造することができる。
(14)この半導体装置の製造方法において、
ノズルから前記絶縁ペーストを吐出して、前記絶縁ペーストを設けてもよい。
(15)この半導体装置の製造方法において、
前記導電部を、前記配線部に電気的に接続された電気的接続部を有するように形成してもよい。
(16)この半導体装置の製造方法において、
前記電気的接続部を、前記絶縁層の第2の面上に形成してもよい。
(17)この半導体装置の製造方法において、
前記絶縁層を、前記溝に連通された凹部を有するように形成し、
前記電気的接続部を、前記凹部の内側に形成してもよい。
(18)この半導体装置の製造方法において、
前記電気的接続部上に外部端子を形成することをさらに含んでもよい。
(19)この半導体装置の製造方法において、
前記絶縁層上に、前記絶縁層と対向する面とは反対側の面に形成された第2の溝を有するように、第2の絶縁層を形成すること、及び、
前記第2の絶縁層上に、第2の配線部を含む第2の導電部を、前記第2の配線部が前記第2の溝の底面及び側面と接触するように形成することをさらに含んでもよい。
(20)この半導体装置の製造方法において、
前記絶縁層を、貫通穴を有し、前記溝が前記貫通穴に連通されるように形成してもよい。
以下、本発明を適用した第1の実施の形態に係る半導体装置の製造方法について説明する。図1(A)〜図7は、本発明を適用した第1の実施の形態に係る半導体装置の製造方法について説明するための図である。
以下、本発明を適用した第2の実施の形態に係る半導体装置の製造方法について説明する。図12(A)〜図17は、本発明を適用した第2の実施の形態に係る半導体装置の製造方法について説明するための図である。
Claims (7)
- 半導体基板上に、前記半導体基板と対向する第1の面とは反対側の第2の面に溝を有するように、エネルギーの照射及び現像によるパターニングを含む方法によって、樹脂から絶縁層を形成すること、
前記絶縁層上に、前記溝の内側のみに位置する配線部を有する導電部を、スパッタリングによって、前記配線部が前記溝の底面及び側面と接触し、前記底面及び前記側面に沿った表面によって凹部を有するように形成すること、及び、
前記溝に沿って、ノズルから前記絶縁ペーストを吐出して前記配線部を覆うように絶縁ペーストを設け、前記絶縁ペーストを硬化させることで、前記配線部を覆う絶縁膜を形成すること、
を含む半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記導電部を、前記配線部に電気的に接続された電気的接続部を有するように形成する半導体装置の製造方法。 - 請求項2記載の半導体装置の製造方法において、
前記電気的接続部を、前記絶縁層の第2の面に形成する半導体装置の製造方法。 - 請求項2記載の半導体装置の製造方法において、
前記絶縁層を、前記溝に連通された凹部を有するように形成し、
前記電気的接続部を、前記凹部の内側に形成する半導体装置の製造方法。 - 請求項2から請求項4のいずれかに記載の半導体装置の製造方法において、
前記電気的接続部上に外部端子を形成することをさらに含む半導体装置の製造方法。 - 請求項1から請求項4のいずれかに記載の半導体装置の製造方法において、
前記絶縁層上に、前記絶縁層と対向する面とは反対側の面に形成された第2の溝を有するように、第2の絶縁層を形成すること、及び、
前記第2の絶縁層上に、第2の配線部を含む第2の導電部を、前記第2の配線部が前記第2の溝の底面及び側面と接触するように形成することをさらに含む半導体装置の製造方法。 - 請求項1から請求項6のいずれかに記載の半導体装置の製造方法において、
前記絶縁層を、貫通穴を有し、前記溝が前記貫通穴に連通されるように形成する半導体装置の製造方法。
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TWI281699B (en) * | 2005-07-26 | 2007-05-21 | Siliconware Precision Industries Co Ltd | Semiconductor device and fabrication method thereof |
JP4874005B2 (ja) * | 2006-06-09 | 2012-02-08 | 富士通セミコンダクター株式会社 | 半導体装置、その製造方法及びその実装方法 |
KR100787894B1 (ko) * | 2007-01-24 | 2007-12-27 | 삼성전자주식회사 | 반도체 칩 구조물과 반도체 칩 구조물 제조 방법 그리고반도체 칩 패키지 및 반도체 칩 패키지 제조 방법 |
JP4273356B2 (ja) * | 2007-02-21 | 2009-06-03 | セイコーエプソン株式会社 | 半導体装置の製造方法 |
US7682959B2 (en) * | 2007-03-21 | 2010-03-23 | Stats Chippac, Ltd. | Method of forming solder bump on high topography plated Cu |
TWI353644B (en) * | 2007-04-25 | 2011-12-01 | Ind Tech Res Inst | Wafer level packaging structure |
JP2010040599A (ja) * | 2008-07-31 | 2010-02-18 | Sanyo Electric Co Ltd | 半導体モジュールおよび半導体装置 |
KR101585217B1 (ko) * | 2009-10-30 | 2016-01-14 | 삼성전자주식회사 | 재배선 구조를 갖는 반도체 소자와 그것을 포함하는 반도체 패키지, 패키지 적층 구조, 반도체 모듈, 전자 회로 기판, 및 전자 시스템과 그 제조 방법들 |
WO2013157080A1 (ja) * | 2012-04-17 | 2013-10-24 | 株式会社ディスコ | 半導体装置およびその製造方法 |
US9576912B1 (en) * | 2015-12-03 | 2017-02-21 | Stmicroelectronics Pte Ltd | Wafer level chip scale package (WLCSP) having edge protection |
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US6441487B2 (en) * | 1997-10-20 | 2002-08-27 | Flip Chip Technologies, L.L.C. | Chip scale package using large ductile solder balls |
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