JP4874005B2 - 半導体装置、その製造方法及びその実装方法 - Google Patents
半導体装置、その製造方法及びその実装方法 Download PDFInfo
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- JP4874005B2 JP4874005B2 JP2006161128A JP2006161128A JP4874005B2 JP 4874005 B2 JP4874005 B2 JP 4874005B2 JP 2006161128 A JP2006161128 A JP 2006161128A JP 2006161128 A JP2006161128 A JP 2006161128A JP 4874005 B2 JP4874005 B2 JP 4874005B2
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- wiring layer
- semiconductor device
- multilayer wiring
- layer
- semiconductor substrate
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- H01L2924/1579—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19043—Component type being a resistor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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- H01L2924/30105—Capacitance
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
Description
前記半導体基板上に配設され、前記複数個の機能素子を相互に接続する配線層と層間絶縁層とを含む多層配線層と、を具備する半導体装置であって、前記配線層が形成された領域を囲繞して前記多層配線層を貫通する複数本の溝が配設され、前記複数本の溝の夫々に有機絶縁物材料が充填され、前記複数本の溝は、前記半導体基板と前記多層配線層の間に配設されている酸化シリコン層を貫通して前記半導体基板に達していることを特徴とする半導体装置が提供される。前記溝の幅は約2μm以上約50μm以下であってもよい。
本発明の実施の形態に係る参考例としての半導体装置の断面構造を図4に示す。図5は、図4に於いて点線により囲まれた部分を拡大して示す。
図9乃至図15を参照し、半導体装置100の製造方法について説明する。
しかる後、感光性ポリイミド25Aを現像処理して、紫外線の非照射部分、即ち個片化される半導体チップの端部、及び電極パッド23の略中央に相当する箇所に於ける感光性ポリイミドが除去される。(図14−(b)参照)
尚、有機絶縁膜25を構成する有機絶縁材料として、非感光性ポリイミドを用いる場合には、フォトレジスト層を用いた選択エッチング法により、当該非感光性ポリイミドをパターニングする。
(付記1) 複数個の機能素子が形成された半導体基板と、
前記半導体基板上に配設され、前記複数個の機能素子を相互に接続する配線層と層間絶縁層とを含む多層配線層と、を具備する半導体装置であって、
前記配線層が形成された領域を囲繞して前記多層配線層を貫通する溝が配設され、
前記溝に有機絶縁物材料が充填されてなることを特徴とする半導体装置。
(付記2) 付記1記載の半導体装置であって、
前記溝の幅は約2μm以上約50μm以下であることを特徴とする半導体装置。
(付記3) 付記1又は2記載の半導体装置であって、
前記溝の前記多層配線層における貫通長さは、約0.1μm以上であることを特徴とする半導体装置。
(付記4) 付記1乃至3いずれか一項記載の半導体装置であって、
前記溝は、前記配線層が形成された領域を囲繞して前記多層配線層に複数本貫通して形成され、前記複数の溝の夫々に前記有機絶縁物材料が充填されてなることを特徴とする半導体装置。
(付記5) 付記1乃至4いずれか一項記載の半導体装置であって、
前記有機絶縁物材料は、ポリイミド、ベンゾシクロブテン、フェノール樹脂、及びポリベンゾオキサゾールから構成される群から選択される材料から成ることを特徴とする半導体装置。
(付記6) 付記1乃至5いずれか一項記載の半導体装置であって、
前記多層配線層上に形成された複数の電極パッドを開口し、前記多層配線層上に設けられた第1の絶縁層と、
前記電極パッドに接続され、前記第1の絶縁層上に設けられた第2の配線層と、
前記第2の配線上に設けられた金属柱と、
前記第1の絶縁層及び前記第2の配線層上に形成され前記金属柱の一端を露出する樹脂と、を具備することを特徴とする半導体装置。
(付記7)付記1乃至6いずれか一項記載の半導体装置であって、
前記金属柱の前記樹脂から露出する一端には外部接続用突起電極が形成されていることを特徴とする半導体装置。
(付記8) 付記6又は7記載の半導体装置であって、
前記樹脂は、ポリイミド、ベンゾシクロブテン、ポリベンゾオキサゾール、フェノール樹脂、ビスマレイミド樹脂又はエポキシ樹脂から構成される群から選択される材料から成ることを特徴とする半導体装置。
(付記9)複数個の機能素子が形成された半導体基板と、
前記半導体基板上に配設され、前記複数個の機能素子を相互に接続する配線層と層間絶縁層とを含む多層配線層とを具備し、
前記配線層が形成された領域を囲繞して前記多層配線層を貫通する溝が配設され、前記溝に有機絶縁物材料が充填され、
前記多層配線層上に樹脂は配設され、前記樹脂面に外部接続用突起電極が形成されている半導体装置の実装方法であって、
当該半導体装置を回路基板に実装する際に、前記回路基板と前記半導体装置との間を充填するアンダーフィル樹脂を、前記半導体装置の側面に表出する前記多層配線層まで被覆することを特徴とする半導体装置の実装方法。
(付記10) 半導体基板の一方の主面に複数個の機能素子を形成する工程と、
前記半導体基板の主面上に、前記複数個の機能素子を相互に接続する配線層と層間絶縁層とからなる多層配線層を形成する工程と、
前記多層配線層に、前記配線層が形成された領域を囲繞し、前記多層配線層を貫通する溝を形成する工程と、
前記溝内に有機絶縁物材料を充填する工程と、
を具備することを特徴とする半導体装置の製造方法。
(付記11) 付記10記載の半導体装置の製造方法であって、
前記溝を、レーザ照射により前記多層配線層に貫通形成することを特徴とする半導体装置の製造方法。
(付記12) 付記10又は11記載の半導体装置の製造方法であって、
前記溝を複数本形成し、前記複数の溝の夫々に前記有機絶縁物材料を充填することを特徴とする半導体装置の製造方法。
(付記13) 付記10乃至12いずれか一項記載の半導体装置の製造方法であって、
当該有機絶縁物材料を前記溝に充填し、
約400℃以下の温度で熱処理を行って当該有機絶縁膜の材料を硬化させることにより、前記溝に前記有機絶縁膜を配設することを特徴とする半導体装置の製造方法。
(付記14) 付記13記載の半導体装置の製造方法であって、
前記有機絶縁物材料は、ベンゾシクロブテン、フェノール樹脂、及びポリベンゾオキサゾールから構成される群から選択される材料であって、
前記熱処理を、約350℃以下の温度で行うことを特徴とする半導体装置の製造方法。
(付記15) 付記13又は14記載の半導体装置の製造方法であって、
前記溝及び前記多層配線層の上方に設けられた前記有機絶縁物材料にマスクを介して光を照射して現像処理を行い、所定の箇所における前記有機絶縁物材料を除去した後に、前記熱処理を行うことを特徴とする半導体装置の製造方法。
(付記16) 付記13又は14記載の半導体装置の製造方法であって、
前記有機絶縁物材料は液状であり、
マスクを介して前記溝及び前記多層配線層の上方の所定の箇所に前記有機絶縁物材料を印刷塗布した後に、前記熱処理を行うことを特徴とする半導体装置の製造方法。
(付記17) 付記13乃至16記載の半導体装置の製造方法であって、
前記溝に有機絶縁膜を充填し、前記多層配線層の前記配線領域の上方を前記有機絶縁膜により被覆した後に、
前記多層配線中に設けられた配線に接続された電極パッドであって前記多層配線層の上面に設けられた電極パッドに、配線層を介して金属柱を接続し、
前記金属柱の上部を除いて樹脂封止をし、
前記金属柱の上部に外部接続用突起電極を形成し、
前記封止樹脂、前記多層配線層、及び前記多層配線層が設けられた基板を切断することを特徴とする半導体装置の製造方法。
(付記18) 付記10乃至17記載の半導体装置の製造方法であって、
前記溝に有機絶縁物材料を充填し、前記多層配線層の前記配線層形成領域の上方を前記有機絶縁膜により被覆した後に、
前記多層配線中に設けられた配線層に接続され前記多層配線層の上面に設けられた電極パッドに第2の配線層を接続して樹脂封止をし、
前記樹脂封止にアッシングにより穴を形成して、当該穴に、上部が前記封止樹脂よりも上方に位置するように金属柱を形成し、
前記封止樹脂、前記多層配線層、及び前記多層半導体基板を切断することを特徴とする半導体装置の製造方法。
2、22 多層配線層
3、23、201 電極パッド
4、24 無機絶縁膜
5、25 有機絶縁膜
6、26 配線層
7、27 金属柱
8、28 封止樹脂
9、29 外部接続用突起電極
10 ダイシングブレード
15、100、110、120、130 半導体装置
30 溝
200 実装基板
300 アンダーフィル
Claims (8)
- 複数個の機能素子が形成された半導体基板と、
前記半導体基板上に配設され、前記複数個の機能素子を相互に接続する配線層と層間絶縁層とを含む多層配線層と、を具備する半導体装置であって、
前記配線層が形成された領域を囲繞して前記多層配線層を貫通する複数本の溝が配設され、
前記複数本の溝の夫々に有機絶縁物材料が充填され、
前記複数本の溝は、前記半導体基板と前記多層配線層の間に配設されている酸化シリコン層を貫通して前記半導体基板に達していることを特徴とする半導体装置。 - 請求項1記載の半導体装置であって、
前記複数本の溝の幅は約2μm以上約50μm以下であることを特徴とする半導体装置。 - 請求項1又は2記載の半導体装置であって、
前記有機絶縁物材料は、ポリイミド、ベンゾシクロブテン、フェノール樹脂、及びポリベンゾオキサゾールから構成される群から選択される材料から成ることを特徴とする半導体装置。 - 請求項1乃至3いずれか一項記載の半導体装置であって、
前記多層配線層上に形成された複数の電極パッドを開口し、前記多層配線層上に設けられた第1の絶縁層と、
前記電極パッドに接続され、前記第1の絶縁層上に設けられた第2の配線層と、
前記第2の配線上に設けられた金属柱と、
前記第1の絶縁層及び前記第2の配線層上に形成され前記金属柱の一端を露出する樹脂と、を具備することを特徴とする半導体装置。 - 請求項4記載の半導体装置であって、
前記金属柱の前記樹脂から露出する一端には外部接続用突起電極が形成されていることを特徴とする半導体装置。 - 複数個の機能素子が形成された半導体基板と、
前記半導体基板上に配設され、前記複数個の機能素子を相互に接続する配線層と層間絶縁層とを含む多層配線層とを具備し、
前記配線層が形成された領域を囲繞して前記多層配線層を貫通する複数本の溝が配設され、前記複数本の溝の夫々に有機絶縁物材料が充填され、前記複数本の溝は、前記半導体基板と前記多層配線層の間に配設されている酸化シリコン層を貫通して前記半導体基板に達しており、
前記多層配線層上に樹脂は配設され、前記樹脂面に外部接続用突起電極が形成されている半導体装置の実装方法であって、
当該半導体装置を回路基板に実装する際に、前記回路基板と前記半導体装置との間を充填するアンダーフィル樹脂を、前記半導体装置の側面に表出する前記多層配線層まで被覆することを特徴とする半導体装置の実装方法。 - 半導体基板の一方の主面に複数個の機能素子を形成する工程と、
前記半導体基板の主面上に、前記複数個の機能素子を相互に接続する配線層と層間絶縁層とからなる多層配線層を形成する工程と、
前記多層配線層に、前記配線層が形成された領域を囲繞し、前記多層配線層を貫通し前記半導体基板と前記多層配線層の間に配設されている酸化シリコン層を貫通して前記半導体基板に達する複数本の溝を形成する工程と、
前記複数の溝の夫々に有機絶縁物材料を充填する工程と、を具備することを特徴とする半導体装置の製造方法。 - 請求項7記載の半導体装置の製造方法であって、
前記複数本の溝を、レーザ照射により前記多層配線層に貫通形成することを特徴とする半導体装置の製造方法。
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EP2648218B1 (en) | 2012-04-05 | 2015-10-14 | Nxp B.V. | Integrated circuit and method of manufacturing the same |
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KR102422460B1 (ko) * | 2017-08-22 | 2022-07-19 | 삼성전자주식회사 | 반도체 소자 |
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JPS5943557A (ja) | 1982-09-06 | 1984-03-10 | Hitachi Ltd | 半導体装置 |
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JP2002289740A (ja) | 2001-03-23 | 2002-10-04 | Toshiba Corp | 半導体装置及びその製造方法 |
JP3813079B2 (ja) * | 2001-10-11 | 2006-08-23 | 沖電気工業株式会社 | チップサイズパッケージ |
US6617655B1 (en) * | 2002-04-05 | 2003-09-09 | Fairchild Semiconductor Corporation | MOSFET device with multiple gate contacts offset from gate contact area and over source area |
US7285867B2 (en) * | 2002-11-08 | 2007-10-23 | Casio Computer Co., Ltd. | Wiring structure on semiconductor substrate and method of fabricating the same |
JP2004349610A (ja) | 2003-05-26 | 2004-12-09 | Casio Comput Co Ltd | 半導体装置およびその製造方法 |
JP2004288816A (ja) * | 2003-03-20 | 2004-10-14 | Seiko Epson Corp | 半導体ウエハ、半導体装置及びその製造方法、回路基板並びに電子機器 |
JP2004296905A (ja) * | 2003-03-27 | 2004-10-21 | Toshiba Corp | 半導体装置 |
JP3983205B2 (ja) * | 2003-07-08 | 2007-09-26 | 沖電気工業株式会社 | 半導体装置及びその製造方法 |
US7489032B2 (en) | 2003-12-25 | 2009-02-10 | Casio Computer Co., Ltd. | Semiconductor device including a hard sheet to reduce warping of a base plate and method of fabricating the same |
JP3945483B2 (ja) * | 2004-01-27 | 2007-07-18 | カシオ計算機株式会社 | 半導体装置の製造方法 |
JP4265997B2 (ja) * | 2004-07-14 | 2009-05-20 | 富士通マイクロエレクトロニクス株式会社 | 半導体装置及びその製造方法 |
US7714448B2 (en) * | 2004-11-16 | 2010-05-11 | Rohm Co., Ltd. | Semiconductor device and method for manufacturing semiconductor device |
JP4055015B2 (ja) * | 2005-04-04 | 2008-03-05 | セイコーエプソン株式会社 | 半導体装置の製造方法 |
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2006
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- 2006-11-13 TW TW095141873A patent/TWI330392B/zh not_active IP Right Cessation
- 2006-11-13 US US11/595,854 patent/US7863745B2/en not_active Expired - Fee Related
- 2006-12-01 CN CNB2006101639747A patent/CN100533711C/zh not_active Expired - Fee Related
- 2006-12-01 KR KR1020060120597A patent/KR100867968B1/ko active IP Right Grant
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CN100533711C (zh) | 2009-08-26 |
KR100867968B1 (ko) | 2008-11-11 |
JP2007329396A (ja) | 2007-12-20 |
TWI330392B (en) | 2010-09-11 |
TW200746323A (en) | 2007-12-16 |
KR20070117986A (ko) | 2007-12-13 |
US20070284755A1 (en) | 2007-12-13 |
CN101086979A (zh) | 2007-12-12 |
US7863745B2 (en) | 2011-01-04 |
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