CN109727942B - 半导体装置以及半导体装置的制造方法 - Google Patents

半导体装置以及半导体装置的制造方法 Download PDF

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CN109727942B
CN109727942B CN201811275895.4A CN201811275895A CN109727942B CN 109727942 B CN109727942 B CN 109727942B CN 201811275895 A CN201811275895 A CN 201811275895A CN 109727942 B CN109727942 B CN 109727942B
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conductive member
insulating film
semiconductor device
film
width
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CN109727942A (zh
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小汲泰一
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Lapis Semiconductor Co Ltd
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Lapis Semiconductor Co Ltd
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Abstract

本发明涉及半导体装置以及半导体装置的制造方法。本发明抑制由构成再布线的导电部件的局部电池效果所造成的过度的蚀刻。半导体装置具备布线，该布线包括设置在半导体基板上的第一导电部件、和设置在第一导电部件的表面且离子化倾向比第一导电部件小的第二导电部件。第一导电部件的、第二导电部件侧的第一面的宽度比第一导电部件的、上述半导体基板侧的第二面的宽度窄。上述第二导电部件的宽度比第一导电部件的上述第一面中的宽度宽且比第一导电部件的第二面中的宽度窄。

Description

半导体装置以及半导体装置的制造方法
技术领域
本发明涉及半导体装置以及半导体装置的制造方法。
背景技术
WL－CSP(晶圆级芯片尺寸封装)是在晶圆工序中进行到再布线、 电极的形成、树脂密封以及切割为止的半导体装置的封装技术。
例如，在专利文献1中记载了与WL－CSP同样地具备再布线的半导 体装置的结构。在专利文献1中记载了在形成于半导体基板上的绝缘膜上 设置有再布线的半导体装置。
专利文献1：日本特开2015－138874号公报
在WL－CSP中所使用的再布线一般由Cu膜构成。本发明人以降低 再布线的布线电阻为目的，进行了由包含Au膜以及Cu膜的层叠膜构成 再布线的尝试。通过由包含Cu膜以及Au膜的层叠膜构成再布线，不仅 能够实现再布线的低电阻化，还能够抑制制造工序内的Cu膜的氧化。而 且，通过由Au膜构成再布线的最表面，从而能够进行向再布线的接线键 合。由此，能够根据用途而将同一芯片分开制成为WL－CSP以及通常的封装两种。
构成再布线的Cu膜以及Au膜分别通过经由包含Cu的种子层进行通 电的电解电镀方法而形成。本发明人发现了在由包含Cu膜以及Au膜的 层叠膜构成再布线的情况下，在用于除去种子层的蚀刻工序中，Au膜和 Cu膜产生局部电池效果，产生构成再布线的Cu膜被过度蚀刻这种现象。
在再布线的布线宽度较窄的情况下，由于局部电池效果所造成的Cu 膜的过度的蚀刻，Cu膜完全消失，Au有可能膜剥离。该情况下，剥离 的Au膜残留在制造装置内，也有可能附着于其它产品。即使在Cu膜没有完全消失的情况下，由于Cu膜的过度的蚀刻，成为再布线的基底的绝 缘膜与Cu膜的接触面积变小，由此，再布线对绝缘膜的紧贴力降低，再 布线有可能从绝缘膜剥离。
另外，由于Au膜呈檐状地覆盖被过度蚀刻的Cu膜，所以不能够通 过从上面的观察来确认Cu膜的状态。即，以往在制造工序中所实施的再 布线的完成情况确认的实施变得困难。
发明内容
本发明是鉴于上述的点而完成的，其目的在于抑制构成再布线的导电 部件的局部电池效果所造成的过度的蚀刻。
本发明所涉及的半导体装置具备布线，上述布线包括设置在半导体基 板上的第一导电部件、和设置在上述第一导电部件的表面、且离子化倾向 比上述第一导电部件小的第二导电部件。上述第一导电部件在上述第二导 电部件侧的第一面的宽度比上述第一导电部件在上述半导体基板侧的第 二面的宽度窄。上述第二导电部件的宽度比上述第一导电部件的上述第一面的宽度宽且比上述第一导电部件的上述第二面的宽度窄。
本发明所涉及的半导体装置的制造方法包括：在半导体基板的表面形 成第一绝缘膜的工序；在第一绝缘膜的表面形成种子层的工序；利用经由 上述种子层来进行通电的电解电镀方法在上述第一绝缘膜的表面形成第 一导电部件的工序；利用经由上述种子层进行通电的电解电镀方法在上述 第一导电部件的表面中在上述第一导电部件的内侧形成第二导电部件的工序，上述第二导电部件具有比上述第一导电部件的宽度窄的宽度且离子化倾向比上述第一导电部件小；以及通过蚀刻将上述种子层除去的工序。
根据本发明，能够抑制由构成再布线的导电部件的局部电池效果所造 成的过度的蚀刻。
附图说明
图1A是表示本发明的实施方式所涉及的半导体装置具备的再布线的 形成区域的结构的俯视图。
图1B是沿着图1A中的1B－1B线的剖视图。
图1C是沿着图1A中的1C－1C线的剖视图。
图2A是表示本发明的实施方式所涉及的半导体装置的制造方法的一 个例子的剖视图。
图2B是表示本发明的实施方式所涉及的半导体装置的制造方法的一 个例子的剖视图。
图2C是表示本发明的实施方式所涉及的半导体装置的制造方法的一 个例子的剖视图。
图2D是表示本发明的实施方式所涉及的半导体装置的制造方法的一 个例子的剖视图。
图2E是表示本发明的实施方式所涉及的半导体装置的制造方法的一 个例子的剖视图。
图2F是表示本发明的实施方式所涉及的半导体装置的制造方法的一 个例子的剖视图。
图2G是表示本发明的实施方式所涉及的半导体装置的制造方法的一 个例子的剖视图。
图2H是表示本发明的实施方式所涉及的半导体装置的制造方法的一 个例子的剖视图。
图2I是表示本发明的实施方式所涉及的半导体装置的制造方法的一 个例子的剖视图。
图2J是表示本发明的实施方式所涉及的半导体装置的制造方法的一 个例子的剖视图。
图2K是表示本发明的实施方式所涉及的半导体装置的制造方法的一 个例子的剖视图。
图2L是表示本发明的实施方式所涉及的半导体装置的制造方法的一 个例子的剖视图。
图2M是表示本发明的实施方式所涉及的半导体装置的制造方法的一 个例子的剖视图。
图2N是表示本发明的实施方式所涉及的半导体装置的制造方法的一 个例子的剖视图。
图2O是表示本发明的实施方式所涉及的半导体装置的制造方法的一 个例子的剖视图。
图2P是表示本发明的实施方式所涉及的半导体装置的制造方法的一 个例子的剖视图。
图2Q是表示本发明的实施方式所涉及的半导体装置的制造方法的一 个例子的剖视图。
图2R是表示本发明的实施方式所涉及的半导体装置的制造方法的一 个例子的剖视图。
图2S是表示本发明的实施方式所涉及的半导体装置的制造方法的一 个例子的剖视图。
图3A是表示在本发明的实施方式所涉及的种子层的蚀刻工序中，由 于局部电池效果而在第一导电部件的内部中流动的电子的流动的图。
图3B是表示本发明的实施方式所涉及的再布线的结构的剖视图。
图4A是表示比较例所涉及的制造工序的一个例子的剖视图。
图4B是表示比较例所涉及的制造工序的一个例子的剖视图。
图4C是表示比较例所涉及的制造工序的一个例子的剖视图。
图4D是表示比较例所涉及的制造工序的一个例子的剖视图。
图4E是表示比较例所涉及的制造工序的一个例子的剖视图。
图4F是表示比较例所涉及的制造工序的一个例子的剖视图。
图5A是表示在比较例所涉及的种子层的蚀刻工序中，由于局部电池 效果而在第一导电部件的内部中流动的电子的流动的图。
图5B是表示比较例所涉及的再布线的结构的剖视图。
符号说明
10…半导体装置；11…半导体基板；20…下层绝缘膜；30…再布线； 30A…凹陷部；31…UBM膜；31a…紧贴层；31b…种子层；32…第一导电 膜；33…第二导电膜；40…上层绝缘膜；50…外部连接端子
具体实施方式
以下，参照附图，对本发明的实施方式进行说明。另外，在各附图中， 对实际相同或者等效的构成要素或者部分附加相同的参照符号。
图1A是表示本发明的实施方式所涉及的半导体装置10具备的再布 线30的形成区域的结构的俯视图，图1B是沿着图1A中的1B－1B线的 剖视图，图1C是沿着图1A中的1C－1C线的剖视图。此外，在图1A中， 图1B所示的下层绝缘膜20、上层绝缘膜40以及外部连接端子50省略图 示。
半导体装置10的封装的方式具有WL－CSP的方式。即，半导体装 置10的封装的平面尺寸与半导体基板11的平面尺寸大致相同。半导体装 置10具备设置在半导体基板11上的下层绝缘膜20、设置在下层绝缘膜 20的表面的再布线30、和覆盖下层绝缘膜20以及再布线30的上层绝缘 膜40。
在半导体基板11的表面形成有晶体管、电阻元件以及电容器等半导 体元件(未图示)。半导体基板11的表面被由SiO2等绝缘体构成的层间 绝缘膜12覆盖。在层间绝缘膜12内设置有与形成在半导体基板11的半 导体元件连接的布线13。层间绝缘膜12的表面被由SiO2等绝缘体构成的 层间绝缘膜14覆盖。在层间绝缘膜14的表面设置有经由导通孔16与布 线13连接的芯片电极15、以及具有使芯片电极15的表面部分地露出的 开口部的钝化膜(保护膜)17。
钝化膜17的表面被由聚酰亚胺以及PBO(聚苯并恶唑)等感光性有 机系绝缘部件构成的、厚度5～10μm左右的下层绝缘膜20覆盖。在下层 绝缘膜20设置有使芯片电极15的表面部分地露出的开口部20A。
在下层绝缘膜20的表面设置有再布线30。再布线30构成为包括UBM 膜(UnderBarrier Metal膜)31、第一导电部件32以及第二导电部件33。 UBM膜31构成为为了提高下层绝缘膜20和再布线30的紧贴性而包括包 含Ti膜的紧贴层。
第一导电部件32被设置在UBM膜31的表面，第二导电部件33被 设置在第一导电部件32的表面。作为第一导电部件32，能够适合使用Cu 膜。作为第二导电部件33，能够适合使用Au膜。通过再布线30包括由 Au膜构成的第二导电部件33，能够减小再布线30的电阻值。再布线30在下层绝缘膜20的开口部20A中与芯片电极15连接。
下层绝缘膜20以及再布线30被由聚酰亚胺以及PBO等感光性有机 系绝缘部件构成的、厚度5～10μm左右的上层绝缘膜40覆盖。在上层绝 缘膜40设置有在外部连接端子50的形成位置使再布线30部分地露出的 开口部40A。外部连接端子50构成为包括例如SnAg，并与在上层绝缘膜 40的开口部40A中露出的再布线30(第二导电部件33)的表面连接。
这样，再布线30通过在一端侧中经由形成在下层绝缘膜20的开口部 20A与芯片电极15连接而与形成在半导体基板11的半导体元件连接，在 另一端侧中经由形成在层绝缘膜40的开口部40A与外部连接端子50连 接。再布线30的与半导体元件连接的一端侧成为连接部30A，与外部连接端子50连接的另一端侧成为焊盘部(盘部)30B，使连接部30A和焊 盘部30B连接的部分成为布线部30C。
以下，详细地对再布线30的结构进行说明。如上述那样，再布线30 具备包括紧贴层的UBM膜31、设置在UBM膜31上的由Cu膜构成的第 一导电部件32和设置在第一导电部件32上的由Au膜构成的第二导电部 件33。
如图1C所示，第一导电部件32具有在经由UBM膜31与下层绝缘 膜20相接的面(以下，称为下表面)的一侧设置的基座部32B、和在与 第二导电部件33相接的面(以下，称为上表面)的一侧设置的狭小部32A。 基座部32B的侧壁与半导体基板11的主面大致垂直，基座部32B的上表 面与半导体基板11的主面大致平行。即，基座部32B的剖面形状为矩形 状。与基座部32B的上表面连接的狭小部32A的底部的宽度比基座部32B 的上表面的宽度窄，狭小部32A的剖面形状为正锥形形状。即，狭小部 32A的侧壁相对于半导体基板11的主面倾斜，狭小部32A的宽度朝向上 面而逐渐变窄。这样，第一导电部件32的上表面的宽度W1a比下表面的 宽度W1b窄。
第二导电部件33的宽度W2比第一导电部件32的下表面中的宽度 W1b窄、且比第一导电部件32的上表面中的宽度W1a宽。如图1A所示， 第二导电部件33被配置在再布线30的宽度方向上第一导电部件32的内 侧，但第二导电部件33的宽度方向两端部如图1C所示，从第一导电部件 32的狭小部32A伸出。换言之，狭小部32A的宽度方向两端部被配置在第二导电部件33的内侧。此外，宽度W1a、W1b以及W2为与再布线30 的引出方向(伸长方向)交叉的方向的长度。
通过如上述那样构成第一导电部件32以及第二导电部件33，从而在 再布线30的、第一导电部件32与第二导电部件33的界面的周边区域中 形成朝向再布线30的宽度方向内侧凹陷的凹陷部35。覆盖再布线30的 上层绝缘膜40侵入再布线30的凹陷部35，第二导电部件33的、从狭小 部32A伸出的部分与上层绝缘膜40相接。凹陷部35通过在用于除去构成UBM膜31的种子层31b(参照图2F)的蚀刻工序中，由于第一导电部件 32以及第二导电部件33的局部电池效果而蚀刻第一导电部件32来形成。 此外，在图1B所示的剖面中，凹陷部35也能够在再布线30的连接部30A 侧的端部以及焊盘部30B侧的端部中观测到。
以下，参照图2A～图2S对半导体装置10的制造方法进行说明。此 外，图2A～图2E、图2P～图2S分别示出与沿着图1A中的1B－1B线 的剖面相当的剖面，图2F～图2O分别示出与沿着图1A中的1C－1C线 的剖面相当的剖面。
首先，准备晶圆工序完成的半导体基板11(图2A)。晶圆工序包括： 在半导体基板11上形成晶体管等半导体元件(未图示)的工序；在半导 体基板11的表面形成由SiO2等绝缘体构成的层间绝缘膜12的工序；形 成与半导体元件连接的布线13的工序；在布线13的表面形成由SiO2等 绝缘体构成的层间绝缘膜14的工序；在层间绝缘膜14的表面形成经由导通孔16与布线13连接的芯片电极15的工序；以及在层间绝缘膜14的表 面形成使芯片电极15部分地露出的钝化膜17的工序。
接下来，例如使用旋涂法在晶圆工序完成的半导体基板11的表面上， 以8μm左右的膜厚涂布聚酰亚胺以及PBO等感光性有机系绝缘部件，形 成覆盖钝化膜17以及芯片电极15的表面的下层绝缘膜20(图2B)。
接下来，通过对下层绝缘膜20实施曝光以及显影处理，从而在下层 绝缘膜20形成使芯片电极15的表面部分地露出的开口部20A(图2C)。
之后，通过热处理来使下层绝缘膜20固化。通过热固化，下层绝缘 膜20收缩，膜厚成为5um左右，另外，大致垂直形状的开口部20A的侧 面成为正锥形形状(图2D)。
接下来，形成覆盖下层绝缘膜20的表面、在下层绝缘膜20的开口部 20A中露出的芯片电极15的表面的UBM膜31(图2E、图2F)。UBM膜 31如图2F所示，由紧贴层31a以及种子层31b的层叠膜构成。紧贴层31a 担当提高下层绝缘膜20与再布线30的紧贴性的作用，例如由厚度150nm 左右的Ti膜构成。种子层31b担当作为利用电镀法形成第一导电部件32 以及第二导电部件33时的通电层的作用，例如由厚度300nm左右的Cu 膜构成。紧贴层31a以及种子层31b分别例如利用溅射法来形成。
接下来，在UBM膜31上形成在再布线30的形成区域具备开口部 200A的抗蚀剂掩模200(图2G)。通过使用旋涂法在UBM膜31上涂布 由感光性有机系绝缘部件构成的抗蚀剂材料后，再通过曝光以及显影处理 对该抗蚀剂材料进行图案化来形成抗蚀剂掩模200。
接下来，使用电解电镀方法，在抗蚀剂掩模200的开口部200A中露 出的UBM膜31上形成作为第一导电部件32的厚度5μm左右的Cu膜(图 2H)。在电解电镀中，在将半导体基板11的表面浸渍在电镀液中的状态下， 使电流经由设置在半导体基板11的外周的电镀电极(未图示)流向构成 UBM膜31的种子层31b。由此，在UBM膜31的露出部分中析出Cu， 在UBM膜31上形成第一导电部件32。构成UBM膜31的种子层31b被 第一导电部件32的Cu吸收。因此，成为在第一导电部件32与下层绝缘 膜20之间夹设作为紧贴层31a发挥作用的Ti膜的结构。
接下来，使用灰化工序或者有机溶剂等来除去抗蚀剂掩模200(图2I)。 接下来，在第一导电部件32的表面形成在第二导电部件33的形成区域中 具备开口部201A的抗蚀剂掩模201(图2J)。通过使用旋涂法在UBM膜 31上以及第一导电部件32上涂布由感光性有机系绝缘部件构成的抗蚀剂 材料后，再通过曝光以及显影处理对该抗蚀剂材料进行图案化来形成抗蚀 剂掩模201。抗蚀剂掩模201的开口部201A的端部以沿着第一导电部件 32的外缘的方式被配置于第一导电部件32的外缘的内侧。
接下来，使用电解电镀方法，在抗蚀剂掩模201的开口部201A中露 出的第一导电部件32的表面形成作为第二导电部件33的厚度1μm左右 的Au膜(图2K)。第二导电部件33形成在比第一导电部件32的端部靠 内侧。在该时刻，第一导电部件32的宽度W1在第一导电部件32的厚度 方向的全部区域中大致均等。第二导电部件的宽度W2形成为比第一导电 部件32的宽度W1窄。优选第二导电部件33的表面积S1与第一导电部 件32的露出部分(第一导电部件32的侧面以及从第二导电部件33露出 的上表面)的表面积S2之比S2/S1为0.08以上。在电解电镀中，在将 半导体基板11的表面浸渍在电镀液中的状态下，使电流经由设置在半导 体基板11的外周的电镀电极(未图示)流向构成UBM膜31的种子层31b。 由此，在第一导电部件32的露出部分析出Au，在第一导电部件32的表 面形成第二导电部件33。由UBM膜31、第一导电部件32以及第二导电 部件33构成再布线30。
接下来，使用灰化工序或者有机溶剂等来除去抗蚀剂掩模201(图 2L)。
接下来，通过使用了软蚀刻液等的湿式蚀刻处理来除去种子层31b(图 2M)。通过用于种子层31b的除去的软蚀刻液使构成种子层31b以及第一 导电部件32的Cu膜的一部分溶解，但没有溶解构成第二导电部件33的 Au膜。蚀刻时间被设定为除去膜厚较小的种子层31b所需的时间。在本 蚀刻工序中，起因于将离子化倾向大的第一导电部件32(Cu膜)、和离子 化倾向比第一导电部件32小的第二导电部件33(Au膜)层叠，而产生局 部电池效果。由于该局部电池效果，第一导电部件32的蚀刻速度高于种 子层31b的蚀刻速度。结果在再布线30中，在第一导电部件32与第二导 电部件33的界面的周边区域中形成朝向再布线30的宽度方向内侧凹陷的 凹陷部35。即，在第一导电部件32的上表面侧形成宽度比下表面侧窄的 狭小部32A，第二导电部件33的宽度比第一导电部件32的下表面中的宽 度窄、且比第一导电部件32的上表面中的宽度宽。
接下来，将第一导电部件32作为掩模，除去紧贴层31a(图2N)。接 下来，例如使用旋涂法，以18μm左右的膜厚涂布聚酰亚胺以及PBO等 感光性有机系绝缘部件，从而形成覆盖再布线30以及下层绝缘膜20的上层绝缘膜40。上层绝缘膜40侵入到形成在再布线30的凹陷部35(图2O、 图2P)。
接下来，通过对上层绝缘膜40实施曝光以及显影处理，从而在上层 绝缘膜40形成使再布线30的焊盘部30B的表面露出的开口部40A(图2Q)。
之后，通过热处理使上层绝缘膜40固化。通过热固化，上层绝缘膜 40收缩，膜厚成为15um左右，另外，大致垂直形状的开口部40A的侧 面成为正锥形形状(图2R)。
接下来，在上层绝缘膜40的开口部40A中露出的再布线30的焊盘 部30B的表面形成外部连接端子50(图2S)。通过在再布线30的焊盘部 30B中例如搭载SnAg球后进行回流焊处理来形成外部连接端子50。另外， 也能够通过在利用丝网印刷在再布线30的焊盘部30B例如形成SnAg糊 剂后进行回流焊处理来形成外部连接端子50。此外，也可以在外部连接端子50的形成前在上层绝缘膜40的表面粘贴保护带，并从半导体基板11 的反面研削半导体基板11来进行半导体基板11的薄膜化。
在上述工序之后，将半导体基板11分割为多个半导体器件，从而WL －CSP型的半导体装置10完成。
此处，图4A～图4F是表示比较例所涉及的制造工序的一个例子的剖 视图。在图4A～图4F中分别示出与沿着图1A中的1C－1C线的剖面相 当的剖面。
在比较例所涉及的制造工序中，利用使用了同一抗蚀剂掩模300的电 解电镀方法来形成构成再布线30的第一导电部件32(Cu膜)以及第二导 电部件33(Au膜)，第一导电部件32和第二导电部件33以相同的宽度形 成(图4A)。
形成第一导电部件32以及第二导电部件33后，使用灰化工序、有机 溶剂等来将抗蚀剂掩模300除去(图4B)。
接下来，通过使用了软蚀刻液等的湿式蚀刻处理将种子层31b除去。 在种子层31b的蚀刻工序中，起因于将离子化倾向大的第一导电部件32 (Cu膜)、和离子化倾向比第一导电部件32小的第二导电部件33(Au 膜)层叠，而产生局部电池效果。根据比较例所涉及的制造方法，由于该 局部电池效果，第一导电部件32的侧面被过度地蚀刻(图4C)。
图5A是表示在比较例所涉及的种子层31b的蚀刻工序中，由于局部 电池效果而在第一导电部件32的内部中流动的电子的流动的图。由于局 部电池效果，构成第一导电部件32的Cu离子化，放出到蚀刻液中。由此， 在厚度方向的全部区域中蚀刻第一导电部件32的侧面。如图5B所示，在被第二导电部件33和第一导电部件32围起的区域A中，蚀刻液形成浓密 的电解质溶液环境，加速离子从第一导电部件32的放出，促进第一导电 部件32的侧面的蚀刻。结果第一导电部件32的侧面被过度地蚀刻。此外，局部电池效果例如也在Au膜与Cu膜间夹着Ni膜等的Au/Ni/Cu层叠膜 中产生。
在除去种子层31b后，将第一导电部件32作为掩模，除去紧贴层31a (图4D)。伴随着第一导电部件32的过度蚀刻，在第一导电部件32的下 方残留的紧贴层31a的宽度变细。由此，下层绝缘膜20与再布线30的紧 贴力不足，如图4E所示，再布线30有可能从下层绝缘膜20剥离。
另外，在再布线30的布线宽度较细的情况下，在种子层31b的蚀刻 工序中，第一导电部件32完全消失，如图4F所示，第二导电部件33有 可能剥离。该情况下，剥离的第二导电部件33残留在制造装置内，也有 可能附着于其它产品。
另外，根据经过比较例所涉及的制造工序所制造的半导体装置，如图 4D所示，由于第二导电部件33呈檐状地覆盖被过度地蚀刻的第一导电部 件32，所以不易通过从上面的观察来确认第一导电部件32的状态。即， 再布线的完成情况确认的实施变得困难。
另一方面，图3A是表示在本发明的实施方式所涉及的种子层31b的 蚀刻工序中，由于局部电池效果而在第一导电部件32的内部中流动的电 子的流动的图。由于局部电池效果，构成第一导电部件32的Cu离子化而 放出到蚀刻液中。然而，根据本发明的实施方式所涉及的制造方法，第二 导电部件33以比第一导电部件32窄的宽度形成。即，第一导电部件32 的露出部分的表面积相对于第二导电部件33的表面积的比率与应用上述 的比较例的所涉及制造方法的情况相比较变高。由此，由于局部电池效果， 流向第一导电部件32的内部的电流的密度与应用比较例所涉及的制造方 法的情况相比较变低，结果抑制从第一导电部件32放出离子，每单位面 积的第一导电部件32(Cu)的溶出速度降低。
另外，如图3B所示，被第一导电部件32和第二导电部件33围起的 区域A的形成与应用比较例所涉及的制造方法的情况相比较变得缓慢，不 易产生从第一导电部件32的离子的放出的加速。结果由于在种子层31b 的蚀刻工序中抑制第一导电部件32的过度的蚀刻，所以能够抑制在再布 线30从下层绝缘膜20剥离这种不良状况、以及第一导电部件32消失且 第二导电部件33剥离这种不良状况的产生。
另外，根据本发明的实施方式所涉及的半导体装置10，如图1C所示， 由于第一导电部件32的下表面中的宽度W1b比第二导电部件33的宽度 W2窄，所以能够通过从上面的观察来确认第一导电部件32的状态。即， 能够实施再布线的完成情况确认。这是因为能够根据抗蚀剂开口的尺寸与 第一导电部件32的下表面中的宽度W1b之差来计算第一导电部件32的 上表面中的宽度W1a，所以能够通过来自再布线30的上表面的完成情况 确认来把握第一导电部件32与第二导电部件33的接合宽度。
此处，由Au膜构成的第二导电部件33、和由有机绝缘膜构成的上层 绝缘膜40的紧贴力比较小，上层绝缘膜40从再布线30剥离，在上层绝 缘膜40与再布线30之间有可能形成空隙。而且，在水分侵入到该空隙内 的情况下，再布线30腐蚀，因半导体装置10的长期间的使用而再布线 30有可能断线。这样，第二导电部件33与上层绝缘膜40的紧贴力给半 导体装置10的长期可靠性带来影响。根据本发明的实施方式所涉及的半 导体装置10，如图1C所示，由于上层绝缘膜40侵入到形成在再布线30 的凹陷部35，所以产生固定效果，不易产生上层绝缘膜40从再布线30 的剥离。即，能够提高半导体装置10的长期可靠性。
另外，根据本发明的实施方式所涉及的半导体装置10，再布线30由 包括由Cu膜构成的第一导电部件32和由Au膜构成的第二导电部件33 的层叠膜构成，所以不仅能够实现再布线30的低电阻化，还能够抑制半 导体装置10的制造工序内的第一导电部件32的氧化。另外，通过Au膜 构成再布线30的最表面，可以进行向再布线30的接线键合。由此，能够 根据用途将同一芯片分别制成为WL－CSP以及通常的封装两种。此外， 在本实施方式中，例示了由Au膜构成第二导电部件33的情况，但也可以 由包含Ni膜以及Au膜的层叠膜构成第二导电部件33。该情况下，将Au 膜配置在再布线30的最表面，将Ni膜配置在Au膜与第一导电部件32(Cu 膜)之间。

Claims (11)

1.一种半导体装置，其中，
具备布线，上述布线包括设置在半导体基板上的第一导电部件、和设置在上述第一导电部件的表面且离子化倾向比上述第一导电部件小的第二导电部件，
上述第一导电部件在上述第二导电部件侧的第一面的宽度比上述第一导电部件在上述半导体基板侧的第二面的宽度窄，
上述第二导电部件的宽度比上述第一导电部件的上述第一面的宽度宽、且比上述第一导电部件的上述第二面的宽度窄，
上述第一导电部件具有设置在上述第二面的一侧的基座部、和设置在上述第一面的一侧的狭小部，
上述基座部的侧壁与上述半导体基板的主面垂直，上述基座部的上表面与上述半导体基板的主面平行，
与上述基座部的上表面连接的上述狭小部的底部的宽度比上述基座部的上表面的宽度窄，上述狭小部的剖面形状为正锥形形状。
2.根据权利要求1所述的半导体装置，其中，还包括：
第一绝缘膜，被设置在上述半导体基板与上述布线之间；以及
第二绝缘膜，覆盖上述第一绝缘膜以及上述布线。
3.根据权利要求2所述的半导体装置，其中，
上述布线经由形成于上述第一绝缘膜的开口部而与形成于上述半导体基板的电极连接，并经由形成于上述第二绝缘膜的开口部与外部连接端子连接。
4.根据权利要求2或者权利要求3所述的半导体装置，其中，
上述布线在上述第一导电部件与上述第二导电部件的界面的周边区域具有朝向上述布线的宽度方向内侧凹陷的凹陷部，
上述第二绝缘膜侵入到上述凹陷部。
5.根据权利要求2或者权利要求3所述的半导体装置，其中，
还包括导电膜，上述导电膜被设置在上述第一导电部件与上述第一绝缘膜之间。
6.根据权利要求1或权利要求2所述的半导体装置，其中，
上述第一导电部件包含Cu，
上述第二导电部件包含Au。
7.一种半导体装置的制造方法，包括：
在半导体基板的表面形成第一绝缘膜的工序；
在第一绝缘膜的表面形成种子层的工序；
利用经由上述种子层来进行通电的电解电镀方法在上述第一绝缘膜的表面形成第一导电部件的工序；
利用经由上述种子层进行通电的电解电镀方法在上述第一导电部件的表面将第二导电部件形成在上述第一导电部件的内侧的工序，上述第二导电部件具有比上述第一导电部件的宽度窄的宽度且离子化倾向比上述第一导电部件小；以及
通过蚀刻将上述种子层除去的工序，
在除去上述种子层的工序中，在包括上述第一导电部件以及上述第二导电部件的布线的、上述第一导电部件与上述第二导电部件的界面的周边区域形成朝向上述布线的宽度方向内侧凹陷的凹陷部。
8.根据权利要求7所述的制造方法，其中，
还包括在上述第一绝缘膜形成第一开口部的工序，
使包括上述第一导电部件以及上述第二导电部件的布线经由上述第一开口部与形成于上述半导体基板的电极连接。
9.根据权利要求7所述的制造方法，其中，
还包括形成覆盖上述第一绝缘膜以及上述布线的第二绝缘膜的工序，上述第二绝缘膜侵入到上述凹陷部。
10.根据权利要求9所述的制造方法，其中，还包括：
在上述第二绝缘膜形成使上述布线的表面局部地露出的第二开口部的工序；以及
在从上述布线的上述第二开口部露出的部分形成外部连接端子的工序。
11.根据权利要求7～权利要求10中的任意一项所述的制造方法，其中，
上述第一导电部件包含Cu，
上述第二导电部件包含Au。
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1404135A (zh) * 2001-09-07 2003-03-19 富士通株式会社 能够抑制电流在焊盘里集中的半导体器件及其制造方法
JP2008016514A (ja) * 2006-07-03 2008-01-24 Renesas Technology Corp 半導体装置の製造方法および半導体装置
CN106206535A (zh) * 2015-05-29 2016-12-07 株式会社东芝 半导体装置及半导体装置的制造方法
JP2016219749A (ja) * 2015-05-26 2016-12-22 ローム株式会社 半導体装置および半導体装置の製造方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6435985A (en) * 1987-07-30 1989-02-07 Mitsubishi Electric Corp Manufacture of printed board
US5229647A (en) * 1991-03-27 1993-07-20 Micron Technology, Inc. High density data storage using stacked wafers
JPH05206098A (ja) * 1992-01-28 1993-08-13 Hitachi Metals Ltd 金属多層膜を有するセラミックス基材のエッチング方法
JP4588046B2 (ja) * 2007-05-31 2010-11-24 三洋電機株式会社 回路装置およびその製造方法
KR101458958B1 (ko) * 2008-06-10 2014-11-13 삼성전자주식회사 반도체 칩, 반도체 패키지 및 반도체 칩의 제조 방법
US10269747B2 (en) * 2012-10-25 2019-04-23 Taiwan Semiconductor Manufacturing Company Semiconductor devices, methods of manufacture thereof, and packaged semiconductor devices
JP6235353B2 (ja) 2014-01-22 2017-11-22 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP6492930B2 (ja) 2015-04-23 2019-04-03 大日本印刷株式会社 半導体装置用リードフレームおよびその製造方法
US10103114B2 (en) * 2016-09-21 2018-10-16 Nanya Technology Corporation Semiconductor structure and manufacturing method thereof

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1404135A (zh) * 2001-09-07 2003-03-19 富士通株式会社 能够抑制电流在焊盘里集中的半导体器件及其制造方法
JP2008016514A (ja) * 2006-07-03 2008-01-24 Renesas Technology Corp 半導体装置の製造方法および半導体装置
JP2016219749A (ja) * 2015-05-26 2016-12-22 ローム株式会社 半導体装置および半導体装置の製造方法
CN106206535A (zh) * 2015-05-29 2016-12-07 株式会社东芝 半导体装置及半导体装置的制造方法

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