CN1404135A - 能够抑制电流在焊盘里集中的半导体器件及其制造方法 - Google Patents

能够抑制电流在焊盘里集中的半导体器件及其制造方法 Download PDF

Info

Publication number
CN1404135A
CN1404135A CN02106180A CN02106180A CN1404135A CN 1404135 A CN1404135 A CN 1404135A CN 02106180 A CN02106180 A CN 02106180A CN 02106180 A CN02106180 A CN 02106180A CN 1404135 A CN1404135 A CN 1404135A
Authority
CN
China
Prior art keywords
pad
film
interlayer dielectric
wiring
hole
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN02106180A
Other languages
English (en)
Other versions
CN1231960C (zh
Inventor
渡边健一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Semiconductor Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of CN1404135A publication Critical patent/CN1404135A/zh
Application granted granted Critical
Publication of CN1231960C publication Critical patent/CN1231960C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76808—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving intermediate temporary filling with material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02123—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body inside the bonding area
    • H01L2224/02125—Reinforcing structures
    • H01L2224/02126—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05005—Structure
    • H01L2224/05006—Dual damascene structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05073—Single internal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05085—Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
    • H01L2224/05089—Disposition of the additional element
    • H01L2224/05093—Disposition of the additional element of a plurality of vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05085—Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
    • H01L2224/05089—Disposition of the additional element
    • H01L2224/05093—Disposition of the additional element of a plurality of vias
    • H01L2224/05095—Disposition of the additional element of a plurality of vias at the periphery of the internal layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/05186—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2224/05187—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05541—Structure
    • H01L2224/05546—Dual damascene structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4845—Details of ball bonds
    • H01L2224/48451—Shape
    • H01L2224/48453—Shape of the interface with the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01018—Argon [Ar]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01038—Strontium [Sr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01073—Tantalum [Ta]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0494—4th Group
    • H01L2924/04941—TiN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0495—5th Group
    • H01L2924/04953—TaN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0504—14th Group
    • H01L2924/05042—Si3N4
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Abstract

在半导体衬底上形成一层间绝缘膜。在层间绝缘膜上形成一内层绝缘膜。穿过层内膜形成一凹槽。凹槽具有一个焊盘部分和一个连着焊盘部分的布线部分。焊盘部分的宽度宽于布线部分的宽度。焊盘部分留有许多凸出区域。凸出区域以这样一种方式分布，即邻近布线区的凹槽区比率高于第二框形区的凹槽区比率，邻近布线区重叠于布线地区延伸进焊盘地区的区域之上，且处在把焊盘部分的外边界线作为外边界线并具有第一宽度的第一框形区之内，而第二框形区则把第一框形区的内边界线作为外边界线并具有第二宽度。在凹槽中填充导电膜。

Description

能够抑制电流在焊盘里集中的半导体器件及其制造方法
参照的相关申请
本申请是基于日本专利申请2001-271416，它于2001年9月7日提交，其中所有的内容在此引入作为参考
技术领域
本发明涉及半导体器件和它的制造方法，尤其涉及这样一种半导体器件的制造方法，当布线和焊盘是通过镶嵌工艺法形成的时候，这种方法能够防止比较低的制造产出率，以及具有适合这种制造方法的结构的半导体器件。
背景技术
随着半导体集成电路器件的集成和微型构图的程度越来越高，多层布线结构的设计规格也越来越小。通过部分腐蚀金属层来形成布线的方法现在和一些技术上的限制相联系。为了解决这个问题，使用镶嵌工艺法，即，通过绝缘层而形成布线的沟槽或者导电栓塞的通孔，然后在槽中或者通孔中填充导电材料。
在通过微型构图形成的多层布线结构上，最后形成了焊盘以便于与外部电路连接和用来检查。和多层布线结构中的其他图形比起来，焊盘有相对较大的尺寸。
参照图9A，下面描述通过使用镶嵌工艺方法形成焊盘的传统方法。
图9A是通过镶嵌工艺方法形成的焊盘的剖面图。首先，在形成于硅衬底上的层间绝缘膜500的表面上，淀积了蚀刻阻止膜501和绝缘膜502。孔503穿过这两层而形成。
然后，形成阻挡金属层504覆盖了孔503的内表面和绝缘膜502的上表面。通过溅射在阻挡金属层504的表面形成铜层。把这一铜层当作籽晶层，通过电镀形成厚的铜层。电镀形成的铜层填充在孔503中。
淀积在绝缘膜502上的铜层和阻挡金属层通过化学机械抛光(CMP)清除掉。如图9A所示，在孔503里留下了通过电镀形成的由铜层制成的焊盘505。
如果焊盘505的面积很大，它的上表面降低。这种现象称作凹陷。绝缘膜502的上表面逐渐朝焊盘505降低，这种现象称作侵蚀。经过化学机械抛光后的焊盘有降低的表面。
如图9B所示，在凹陷和侵蚀的表面上，淀积了氮化硅蚀刻阻挡膜506和氧化硅层间绝缘膜507。层间绝缘膜506的表面和它下面层的表面一样有降低的表面。在层间绝缘膜507的表面形成抗蚀膜。当通过光刻形成图形时，在曝光过程中焦点深度容差很小。如果布线是通过镶嵌工艺方法形成在这个降低的表面，在CMP之后形成导电膜的残余，并且栓塞将可能电短路。
图9C是焊盘的剖面图，其中图9A所示的绝缘膜502被包含下绝缘层502A和上绝缘层502B的二层结构代替。下绝缘层502A是由氟掺杂氧化硅制成，而上绝缘层502B是由氧化硅制成。当侵蚀形成时，在某些情况下下绝缘层502A在和孔503边缘接触的地区是暴露的。氟掺杂氧化硅有高的吸湿性以致暴露的绝缘层502A吸收水蒸气。氟掺杂氧化硅膜和吸收的水蒸气在随后的热处理过程中能产生气体或者能引起紧致粘附的降低。
如果下绝缘膜是由绝缘的有机材料如多烯丙醚制成，加之水蒸气吸收和紧致粘附的降低，如下的问题发生了。如图9D所示，在通过镶嵌工艺法在焊盘505上形成布线之前，形成了氮化硅蚀刻阻止膜506。当所述蚀刻阻止膜506是通过等离子加强化学汽相淀积法(PE-CVD)形成时，产生了H2和NH3的等离子体。因此，暴露的绝缘层502A暴露在H2和NH3的等离子体中被等离子体蚀刻，并且在某些情况下形成间隙。这个层本身可能被分解并且紧致粘附可能降低。
为了在蚀刻阻止层506形成之前清除形成在Cu焊盘表面上的薄的氧化铜膜，通过使用例如NH3等离子体来完成还原反应。在这个还原反应中，绝缘层502A可能被分解。
图10A到10C是计划用来抑制凹陷和侵蚀产生的焊盘的平面图。图10A和10C所示的焊盘是JP-A-11-150114公开的，而图10B所示的焊盘则是JP-A-10-229085公开的。在任一情形中，图9A所示的绝缘层502的绝缘区域502a保留下来了。这些绝缘区域502a对CMP起着抛光阻止层的作用以致于凹陷和侵蚀的产生能得到抑制。
图11是焊盘和连着这个焊盘的布线图形的平面图。布线图形510连着方形焊盘505的一边。许多方形绝缘区域502a呈矩阵形状布置在焊盘505里。为了提高抑制凹陷和侵蚀产生的效果，和图10C所示的这些区域相比，每个绝缘区域502a的尺寸都做得更小，它们的数量也增多了。
布线图形510的宽度用W1表示，从焊盘505的外边界线到最外绝缘区域502a的距离用W2表示，相邻的绝缘区域502a之间的距离用W3表示。考虑封闭线511，它横过布线图形510并且沿着许多离焊盘505和布线图形510之间的边界线最近的绝缘区域502a延伸。在图11所示的焊盘中，封闭的线511沿着6个绝缘区域502a的内部延伸。在下面，假定封闭线511沿着(n+1)个绝缘区域延伸。
当电流从线路510流向焊盘505时，流进封闭线511的电流与流出封闭线511的电流相等。这就是说，流经封闭线511和线路510交叉段W1的电流，和流经封闭线511与线路510交叉段2×W2+n×W3的电流是相等的。
如果满足如下不等式并且线路510中的电流密度取允许的限定值，则沿着穿过封闭线511方向流动的电流的密度超过允许的限定值：
W1＞2×W2+n×W3
形成在硅衬底上的半导体器件的特性能被检验例如通过导电探针和焊盘505接触。如果绝缘区域502a分散在焊盘505的内部，焊盘505和导电探针的接触可变得不稳定。
发明内容
本发明的一个目的是提供一种半导体器件，它具有的焊盘结构能够抑制过多电流集中在焊盘中，以及它的制造方法。
本发明的另一个目的是提供一种半导体器件，它具有的焊盘结构能够缓和焊盘与检验探针之间接触的不稳定性，以及它的制造方法。
根据本发明的一个方面，提供了制造半导体器件的方法，包含如下步骤：a)在表面上已形成有半导体元件的半导体衬底上形成由绝缘材料制成的第一层间绝缘膜；b)在第一层间绝缘膜上形成由绝缘材料制成的第一层内绝缘膜；c)穿过第一层内绝缘膜形成沟槽，其中沟槽包括焊盘部分和连着这个焊盘部分的布线部分，焊盘部分的宽度宽于布线部分的宽度，在焊盘部分留有许多凸出区域，并且形成沟槽以便于凸出区域以这样一种方式分布，即邻近布线区的沟槽区比率高于第二框形区的沟槽区比率，邻近布线区重叠于布线地区延伸进焊盘地区的区域之上，且处在把焊盘部分的外边界线作为外边界线并具有第一宽度的第一框形区之内，而第二框形区则把第一框形区的内边界线作为外边界线并具有第二宽度；d)在半导体衬底上形成由导电材料制成的第一层薄膜，第一层薄膜填充进沟槽；和e)清除第一层薄膜的上面区域以便形成留在沟槽中的第一层薄膜制成的焊盘。
根据本发明的另一方面，提供了半导体器件包括：半导体衬底；由绝缘材料制成并形成在半导体衬底上的第一层间绝缘膜；由绝缘材料制成并形成在第一层间绝缘膜上的第一层内绝缘膜，在所述层内绝缘膜中形成到达它的下底面的沟槽，沟槽包括焊盘部分和连着这个焊盘的布线部分，焊盘部分的宽度宽于布线部分的宽度，在焊盘部分留有许多凸出区域，并且沟槽的形成以便于凸出区域以这样一种方式分布，即邻近布线区的沟槽区比率高于第二框形区的沟槽区比率，邻近布线区重叠于布线地区延伸进焊盘地区的区域之上，且处在把焊盘部分的外边界线作为外边界线并具有第一宽度的第一框形区之内，而第二框形区则把第一框形区的内边界线作为外边界线并具有第二宽度；在沟槽的焊盘部分填充第一焊盘；在沟槽的布线部分填充布线。
由于沟槽的焊盘部分留有许多凸出区域，在步骤(e)中蚀刻第一薄膜时，抑制焊盘部分中的第一薄膜形成一个降低的上表面是可能的。由于邻近布线区的沟槽区比率相对较大，临近布线区的第一焊盘区比率也比较大。因此当电流从布线流向焊盘时避免过量的电流在第一焊盘的某一特定区域集中是可能的。
附图说明
图1是根据第一实施方案的半导体器件的剖面图。
图2A是和第一实施方案的半导体器件一起使用的焊盘的平面图，而图2B是检验探针和焊盘接触的说明图。
图3A到3E是根据第一实施方案制造半导体器件的方法的剖面说明图。
图4A到4C是显示焊盘绝缘区域和通孔位置关系的平面图。
图5是通孔仅分布在焊盘中心区域的焊盘的剖面图。
图6A和6B是显示其他焊盘结构的平面图。
图7A到7C是显示其他焊盘结构的平面图。
图8A到8E是根据第二实施方案制造半导体器件的方法的剖面说明图。
图9A到9D是和传统的半导体器件一起使用的焊盘的剖面图。
图10A到10C是和传统的半导体器件一起使用的焊盘的平面图。
图11是用来解释电流集中原因的焊盘和布线图形的平面图。
图12是显示电流经过焊盘区域的总宽度Wt和布线宽度W1之间关系的曲线图。
图13是显示焊盘另一种结构的平面图。
具体实施方式
图1是根据本发明第一实施方案的半导体器件的剖面图。在半导体衬底1的表面层形成元件分离绝缘膜5，它限定了有源区域。元素分离绝缘层5是由硅的定位氧化(LOCOS)或浅沟分离(STI)制成。在有源区域的表面上形成了MOS场效应晶体管(MOSFET)6。
在半导体衬底1上形成一层间绝缘膜10覆盖MOSFET6。层间绝缘膜10具有两层的结构包括由氮化硅制成的下层10A和由氧化硅制成的上层10B。通孔11穿过层间绝缘膜10而形成。通孔11形成在与MOSFET6的源/漏区相对应的区域。通孔11的内表面覆盖了一层由氮化钛(TiN)制成的阻挡层12A，并在通孔11里面填充了由钨(W)制成的导电栓塞12B。
上面描述的结构能通过众所周知的膜形成技术，光刻技术，化学机械抛光和类似技术形成。
在层间绝缘膜10的上面形成了四个布线层20。在上下两个布线层20之间布置了层间绝缘30。每个布线层20包括内层绝缘膜21，布线图形25和焊盘27。布线图形25和焊盘27填充在到达内层绝缘膜21底面的沟槽(凹口)中。阻挡金属层26布置在沟槽内表面与布线图形25的界面以及沟槽内表面与焊盘27的界面上。例如，布线图形25和焊盘27是由铜(Cu)制成而阻挡金属膜26是由氮化钽(TaN)制成。例如，阻挡层26的厚度是30nm。
每个内层绝缘膜21具有三层的结构，从半导体衬底1侧开始依次叠着蚀刻阻止膜22，中间膜23和上层膜24。例如，蚀刻阻止膜22是由氮化硅制成并厚50nm，中间膜23是由氟掺杂氧化硅制成并厚350nm，上层膜24由氧化硅制成并厚150nm。
蚀刻阻止层31布置在层间绝缘膜30和下面的布线层20之间。例如，层间绝缘膜30由氧化硅制成并且厚500nm，蚀刻阻止层31由氮化硅制成并厚50nm。
通孔35穿过层间绝缘膜30和蚀刻阻止层31这两层薄膜而形成。导电栓塞36填充在通孔35里面。阻挡金属层37布置在通孔35的内表面和栓塞36之间。例如，阻挡金属层37由氮化钽制成并厚30nm，栓塞36由Cu制成并且电连接上下层的布线图形或焊盘。
具有同样构图的焊盘27分布在处于衬底平面同一位置的所有布线层20中。焊盘27的形状将在后面详述。
在第四布线层40上，依次叠放蚀刻阻止膜41和层间绝缘膜40，通孔45穿过层间绝缘膜40和蚀刻阻止膜41这两层而形成。在通孔45里填充导电栓塞46，一个粘合层47布置在通孔45的内表面和栓塞46之间，例如，粘合层47由TiN制成并且厚200nm，栓塞46由钨(W)制成。
在层间绝缘膜40上与焊盘27对应的区域中形成焊盘50。在焊盘50和层间绝缘膜40之间分布着阻挡金属层51。焊盘50通过栓塞46与下面的栓塞27相连。在层间绝缘膜40的另一上表面，形成布线图形60和焊盘。这些焊盘用于：例如，电路测试，线丝键合或形成凸块。
覆盖膜70形成于层间绝缘膜40之上，覆盖焊盘50和布线图形60。覆盖膜70具有两层结构包括1000nm厚的氧化硅薄膜70A和500nm厚的氮化硅薄膜70B。穿过覆盖膜70形成开口71以便暴露焊盘50的上表面。阻挡金属层52形成于焊盘50的上表面中焊盘50未暴露部分和覆盖膜70之间的界面。
例如，焊盘50由AlCu合金制成(Cu含量：0.5wt％)并且厚1000nm，阻挡金属层51和52均由TiN制成并且厚50nm。导电线75引线键合到焊盘50的上表面。导电线75通过焊盘27和下面布线层中的栓塞36与形成于半导体衬底1表面上的半导体器件，例如，MOSFET6，保持电连接。
图2A是分布在第一布线层20里的焊盘27的平面图。图1的剖面图是沿着图2A所示的点划线A1-A1获得的。焊盘27连着布线图形25。分布在如图1所示的第二到第四布线层20里的焊盘27具有与图2A所示的焊盘27一样的平面图。
焊盘27的内部分为第一框形区27a，第二框形区27c和中间地区27d。第一框形区27a把焊盘27的外边界线作为自己的外边界线并且宽L1。第二框形区27c把第一框形区27a的内边界线作为自己的外边界线并且宽L2。中间地区27d处在第二框形区27c的内边界线里面。延长布线图形25到焊盘27里面且重叠于第一框形区27a之上所决定的区域27b称为邻近布线区。
许多方形的绝缘区域21a分布在第二框形区27c。在第一框形区27a和中间地区27d之内不布置绝缘区域21a。沿着水平和垂直的方向，绝缘区域21a都是以间距为P规则(周期)分布在第二框形区27c里。绝缘区域21a的一边长度表示为P1，相邻绝缘区域21a的距离表示为P2。
第一框形区27a的宽L1等于或宽于距离P2。
在图2A所示的焊盘27中，绝缘区域21a不布置在第一框形区27a中，尤其是邻近布线区27b中。因此，能阻止从线路25流进焊盘27或从焊盘27流进线路25的电流发生过量电流集中。为了更有效地避免过量电流集中，优选使宽度L1等于或宽于距离P2，更优选使它等于或宽于间距P。如果绝缘区域分布不是周期性，优选使宽度L1宽于相邻两绝缘区域21a之间的最短距离。
然后，将描述宽度L1和布线25的宽度W1之间的关系。图12显示了布线宽度W1和从布线25中来的电流流经焊盘27中的区域总宽度Wt之间的关系。宽度Wt等于图11和不等式(1)中所示的2×W2+n×W3。如图2A所示的宽度L1和距离P2分别对应图11中所示的宽度W2和W3。
在图12所示的曲线图中，间距P为2.5μm而距离P1是1.0μm。横坐标代表用单位“μm”表示的布线宽度W1，而纵坐标代表用单位“μm”表示的电流流经焊盘区域的总宽度Wt。
图12所示的从a1到a8的直线分别对应宽度L1等于1μm，2μm，3μm，4μm，5μm，6μm，7μm和8μm。在Wt≥W1的区域(一条虚线的左上方)，不会发生过量电流集中。
例如，如果布线宽度W1为10μm而宽度L1等于或宽于3.5μm，从图中能知道不会发生过量电流集中。如果布线宽度W1为5μm而宽度L1为1.5μm或更宽，也不会发生过量电流集中。更一般而言，可以这样认为，如果布线宽度W1为5μm-10μm，L1/W1的优选范围为35％或更高，如果布线宽度W1窄于5μm，L1/W1的优选范围为30％或更高。
严格地说，虽然优选范围可能随着间距P和距离P2的不同而不同，但如果焊盘的设计满足了上面描述的条件，过量电流集中引起的问题能够得到避免。
在某些情况下，当如图1所示的第一布线层20形成之后，在上布线层上形成第二个之前，检查形成于半导体衬底表面上的半导体元件的特性。在这一检验中，如图2B所示，检验探针29与形成于第一布线层20里的焊盘27接触，以提供电源电压或探测输出信号。由于焊盘布置在每个布线层20的同样位置，故可以待每个布线层20都形成之后，再进行这样的检验。
如图2A和2B所示，由于焊盘27的中心区域27d不布置有绝缘区域21a，故能够获得检验探针和焊盘27之间的稳定接触。为了获得高的接触稳定性，优选使中心地区27d的尺寸和形状被包括在一个直径为20μm的圆内。优选使中间区域27d的面积为焊盘27面积(这一面积包括绝缘区域21a)的四分之一或更小。
然后，参照图3A到3E，描述如图1所示的焊盘27和其上栓塞36。在图3A到3E中，通过举例来描述在第一布线层20中形成焊盘27和其上栓塞36的方法。在其它布线层20中的焊盘27和其上栓塞36能用同样的方法形成。
如图3A所示，在层间绝缘膜10上，形成了一层由氮化硅(SiN)制成的厚50nm蚀刻阻止膜22。例如，通过使用硅烷(SiH4)和氨气(NH3)作为源气体的等离子加强化学气相淀积(PE-CVD)形成蚀刻阻止膜22。
在蚀刻阻止膜22上面形成了一层由掺氟氧化硅(SiOF)制成的中间膜23，它厚350nm。例如，通过使用氟硅烷(SiF4)和氧气(O2)作为源气体的PE-CVD形成中间膜23。
在中间膜23上面，形成由氧化硅(SiO2)制成的上层膜24，它厚150nm。例如，通过使用硅烷和氧气(O2)作为源气体PE-CVD形成上层膜24。
在上层膜24上面形成抗蚀图形80。抗蚀图形80具有与焊盘27和布线图形25对应的开口。通过把抗蚀图形80作为掩膜，蚀刻了上层膜24和中间层23。蚀刻能通过使用含CF类气体(例如气体包括：CF4  C4O8或类似)的反应离子腐蚀(RIE)来完成。
此后，通过使用氧等离子体使抗蚀图形灰化。通过把图形化的上层膜24和中层膜23作为掩膜，蚀刻了蚀刻阻止层22。这一腐蚀能通过使用含CHF类气体(例如气体包括CHF3)的RIE来完成。
如图3B所示，这样就留下了三层结构的内层绝缘膜21，包括蚀刻阻止膜22，中间膜22和上层膜24。内层绝缘膜21中有凹口101，其中形成了焊盘27。
如图3C所示，通过溅射在衬底的整个表面上形成了厚30nm的TaN层26L。在这个TaN层26L表面上，通过溅射形成Cu层。把这个Cu层作为籽晶层，通过电镀形成厚1500nm的Cu层27L。
如图3D所示，为了清除不必要的Cu层27L和TaN层26L，进行CMP直到上层膜24的上表面暴露出来。由一部分TaN层26L制成的阻挡金属层26和由一部分Cu层27L制成的焊盘27留在开孔101里。由于焊盘27里布置着绝缘区域21a，故CMP过程中凹陷和侵蚀的形成能得到抑制。
如图3E所示，形成了由氮化硅制成的蚀刻阻止膜31，它厚50nm。例如，蚀刻阻止层31能通过使用硅烷和氨气作为源气体的PE-CVD形成。在蚀刻阻止膜31上面，形成了由氧化硅制成的厚500nm的层间绝缘膜30。例如，层间绝缘膜30能通过使用硅烷和氧气作为源气体的PE-CVD形成。
通孔35穿过层间绝缘膜30和蚀刻阻止膜31而形成。与形成焊盘27的方法类似，通过形成TaN层和Cu层并且进行CMP过程在通孔35中形成金属阻挡层37和栓塞36。
通过重复以上过程，形成图1所示的第一到第四布线层20。
然后，参照图1，描述在第四布线层20上形成多层结构的方法。
在第四布线层20上，相继形成了氮化硅蚀刻阻止膜41和氧化硅层间绝缘膜40。层间绝缘膜40的表面通过CMP变得平坦。通孔穿过这两层而形成。厚200nm的TiN层覆盖了通孔45的内表面和层间绝缘膜40的上表面。在这个TiN层上，形成了厚400nm的W层并填充了通孔。通过CMP清除了W层和TiN层不必要的区域，在通孔45里留TiN粘合层47和由W制成的栓塞46。
在层间绝缘膜40上，相继形成厚50nm的TiN层，厚1000nm的AlCu合金层和厚50nm的TiN层。这三层经过构图而留下TiN阻挡金属层51，AlCu合金焊盘50和TiN阻挡金属层52。蚀刻这三层能通过使用包含氯气类气体(例如Cl2，O2和Ar的混合气体)的RIE完成。经过这个过程，形成了布线60。
在层间绝缘膜40上，相继形成了覆盖焊盘50和布线60的1000nm厚的氧化硅膜70A和500nm厚的氮化硅薄膜70B。穿过氮化硅膜70B，氧化硅膜70A和阻挡金属层52这三层形成一个开口71。蚀刻氮化硅薄膜70B和氧化硅薄膜70A这两层能通过使用含CF类气体的RIE来完成。而蚀刻阻挡金属层52能通过使用含氯气类气体的RIE来完成。
形成于半导体衬底1表面上的半导体元件能通过使检验探针与焊盘50接触得到检验。如果检验结果成功，半导体衬底1沿着刻画线划成分立的芯片。如果焊盘布置在刻画线区域，如图1所示的焊盘和下面的焊盘27的最初结构被破坏。然而，在一些情况下一部分焊盘50和下面焊盘27保留下来。如果焊盘50布置在一个芯片区，那么焊盘50和下面的焊盘27留在了这个芯片里。
接着，参照图4A到4C，描述栓塞和焊盘中绝缘区域的位置关系。
图4A显示了通孔45和分布在焊盘27里的绝缘区域21a的位置关系的一个例子。通孔45布置为使得它叠在绝缘区域21a之上。这就是说，通孔45被包含在焊盘27的导电区域中。
这样布置，即使当图1所示的通孔45形成时发生了腐蚀过度，下面的内层绝缘膜21也不会暴露。因此可能防止由于内层绝缘膜21的中间层23吸收湿气引起紧致粘附降低。
图4A所示的通孔45都一般均匀地分布在焊盘27中。在图4B所示的例子中，中间区域27d不布置有通孔45。图4B所示的结构的作用将在下面描述。
由于绝缘区域21a不分布在中间区域27d，通过CMP可能在焊盘27的中间区域27d形成凹陷。如果凹陷形成了，处在图1所示的在第四布线层中的焊盘27的中间区域27d之上的层间绝缘膜40实际上将变厚。在某些情况下中间区域27d中的通孔将不穿透层间绝缘膜40，通孔的穿透缺陷能够通过图4B所示的不分布通孔在中间区域27d中得到防止。
如果有穿透缺陷的通孔，连接上下焊盘的栓塞的实际数量将减少。因此，每一个栓塞的电流超过设计值。与图4B所示的结构类似的结构能应用于其它布线层中的焊盘27，而不是仅局限于第四布线层。
如图4C所示，可以在不布置绝缘区域21a的中间区域27d中布置单个大通孔45。
图5是图4C所示焊盘的剖面图。在第四布线层20上，形成了蚀刻阻止膜41和层间绝缘膜40。穿过这两层的通孔45形成的区域被包括在焊盘27的中间地区27d之中。焊盘50形成在层间绝缘膜40的上方。焊盘50通过通孔45与分布在第四布线层20中的焊盘27的中间区域27d电连接。阻挡金属51分布在焊盘50的底面和它下面层的表面之间。处在焊盘50上面的结构与图1所示的半导体器件的结构类似。
导电线75和焊盘50之间的接触区域相对于通孔45延伸到外面。因此，当沿着平行于衬底法线的方向看时，导电线75和焊盘50之间的接触区域与层间绝缘膜40部分重叠。由氧化硅制成的层间绝缘膜40比由Cu制成的焊盘27硬。在导电线75和焊盘50接触区域重叠于层间绝缘膜40的地方，能获得导电线75和焊盘50之间的高紧致粘附。图6A和6B显示了焊盘27的其它结构的例子。在图6A所示的结构中，绝缘区域21a分布在图2A所示的除邻近布线区27b之外的第一框形区27a里。由于邻近布线区27b中不布置绝缘区域21a，过量电流集中能得到避免。
在图6B所示的结构中，布线图形25与方形焊盘27的三边连接。邻近布线区27b与三个布线图形25相一致而分布。这样设计，当电流在任何一个布线图形25中流动时，都能避免过量电流集中。
图7A到7C显示了焊盘27的其它结构的例子。在图2A以及图6A和6B所示结构中，绝缘区域21a不布置在中间区域27d。在图7A到7C所示结构的例子中，中间区域27d中也分布绝缘区域21a。绝缘区域21a在图7A到7C所示的焊盘27中除中间区域27d之外的区域的设计与图6A和6B以及图2A中焊盘27的设计是相似的。
不需要与检验探针接触的焊盘27可以具有图7A到7C的结构。由于中间区域27d也分布了绝缘区域21a，中间区域27d不会形成凹陷。
在如上所描述的第一种实施方案中，内层绝缘膜21包括由氟掺杂氧化硅制成的中间膜23。中间膜23可以由多烯丙醚制成。内层绝缘膜21可以具有包含蚀刻阻止膜和氧化硅膜的二层结构。
然后，参照图8A到8E，描述本发明的第二实施方案的半导体器件和它的制造方法。在第一实施方案中，布线图形和栓塞都是单镶嵌工艺法形成的。在第二实施方案中，它们都通过双镶嵌工艺法形成。
下面描述了图8A所示结构的形成过程。在图8A所示的层间绝缘膜10之下的结构和在图1所示的第一种实施方案中半导体器件的层间绝缘膜10之下的结构是相同的。
第一布线层20形成于层间绝缘膜10上面。图1所示的第一布线层20里的内层绝缘膜21具有包含蚀刻阻止层22，氟掺杂氧化硅层23和氧化硅层24的三层结构。第二种实施方案的半导体器件的内层绝缘膜21具有包含氮化硅蚀刻阻止膜和氧化硅层的两层结构。焊盘27填充在形成于层内绝缘膜21中的凹槽中。在凹槽的内表面和焊盘27之间布置了阻挡金属层26。
在第一布线层20上，依次形成第一蚀刻阻止膜100，层间绝缘膜101，第二蚀刻阻止膜102和层内绝缘膜103。第一和第二蚀刻阻止膜100和102都由氮化硅制成且厚50nm。层间绝缘膜101和内层绝缘膜103都是由氧化硅制成且厚350nm。
抗蚀图形105形成于内层绝缘膜103之上。与图1所示的通孔35相应的开口105a穿过抗蚀图形105。通过把抗蚀图形105作为掩膜，蚀刻内层绝缘膜103，第二蚀刻阻止膜102和层间绝缘膜101以便于部分地暴露第一蚀刻阻止膜100。蚀刻这些膜能通过使用含CF类气体的各向异性RIE来完成。通过使用C和F之间的含量比率不同的各种气体，蚀刻氮化硅膜或者把氮化硅膜作为蚀刻阻止膜使用是可能的。通过在蚀刻过程中改变蚀刻剂气体，蚀刻第二蚀刻阻止膜102和在第一蚀刻阻止膜100的上表面停止蚀刻是可能的。在蚀刻之后，抗蚀图形105被除掉。
如图8B所示，因此形成穿过内层绝缘膜103，第二蚀刻阻止膜102和层间绝缘膜101的通孔108。在衬底表面涂上树脂之后，树脂融化以便于树脂109填充在通孔108比第二蚀刻阻止层102的下底面深的地方。通过加热使树脂109变硬。例如清除了感光材料的抗蚀材料可以用作树脂109的材料。
抗蚀图形110形成于内层绝缘膜103的表面。与如图1所示的焊盘27对应的开口110a穿过抗蚀图形110而形成。通过把抗蚀图形110作为掩膜，蚀刻内层绝缘膜103。这一腐蚀能通过使用含CF类气体的各向异性RIE来完成。在蚀刻之后，抗蚀图形110和树脂109都通过灰化清除掉。
如图8C所示，因此形成到达层内绝缘膜103下底面的凹槽112。通孔108开在凹槽112下底面的部分地区。通过把内层绝缘膜103作为掩膜，蚀刻第二蚀刻阻止膜102并且同时，通过把层间绝缘膜101作为掩膜，蚀刻了第一蚀刻阻止膜100。
如图8D所示，蚀刻阻止膜100和102暴露区域被清除掉。淀积了阻挡金属层115覆盖了通孔108的内表面，沟槽112的内表面和内层绝缘膜103的表面。例如，阻挡金属层115是由TaN或Ta制成并且厚30nm。
在阻挡金属层115的上面形成导电薄膜116。例如，导电薄膜116是由Cu制成并且厚1500nm，导电薄膜116可以通过先溅射形成Cu籽晶层再镀Cu而形成。通孔108和沟槽112的内部埋以导电薄膜116。
如图8E所示，进行CMP直到内层绝缘膜103的上表面暴露出来，以清除导电膜116和阻挡金属层115的不必要的区域。因此导电薄膜116留在了通孔108和沟槽112里。内层绝缘膜103的一些岛形区域留在了沟槽中，它们限定了焊盘。因此在CMP过程中抑制凹陷和侵蚀的形成是可能的。通过重复相似的过程，能形成多层布线结构。
通过使用双镶嵌工艺法形成焊盘的第二种实施方案也能取得和第一种实施方案相似的作用。
图13是显示焊盘27另一种结构的平面图。在上面描述的实施方案中，例如，如图2A所示，绝缘区域21a通常呈矩阵形状规则分布在焊盘27的第二框形区。如图13所示，许多延长的绝缘区域21a可分布在与方形第二框形区27C的两个对边相对应的地区。在这种情况下，布线图形25与焊盘27中与第二框形区27C没有布置绝缘区域21a的那一边对应的外边界连接。
在这种情况下，由于绝缘区域21a部分地布置，也能够抑制腐蚀和凹陷。由于整个中心地区27d是一个导电区，导电探针能与这一区域可靠地接触，并且能够避免过量电流集中。
已经与优选实施方案一起描述了本发明。本发明不仅仅局限于以上实施方案。很明显，熟练的技术人员能够作出各种修改，改进，结合和类似的变化。

Claims (13)

1.一种制造半导体器件的方法，包括以下步骤：
(a)在衬底表面上形成了半导体元件的半导体衬底上形成由绝缘材料制成的第一个层间绝缘膜；
(b)在第一个层间绝缘膜上形成由绝缘材料制成的第一个内层绝缘膜；
(c)穿过第一内层绝缘膜形成凹槽，其中凹槽有一个焊盘部分和连着这个焊盘部分的布线部分，焊盘部分的宽度宽于布线部分的宽度，在焊盘部分留有许多凸出区域，并且形成凹槽使得凸出区域以这样一种方式分布，即邻近布线区的凹槽区比率高于第二框形区的凹槽区比率，该邻近布线区重叠于布线地区延伸进焊盘地区的区域之上，且处在把焊盘部分的外边界线作为外边界线并具有第一宽度的第一框形区之内，而第二框形区则把第一框形区的内边界线作为外边界线并具有第二宽度；
(d)在半导体衬底上形成由导电材料制成的第一薄膜，第一薄膜填充进凹槽；以及
(e)除去第一薄膜的上面区域以形成留在凹槽中的第一薄膜制成的第一焊盘。
2.根据权利要求1的方法，(e)步之后进一步包括以下步骤：
(f)在第一内层绝缘膜和剩下的第一薄膜上形成第二个由绝缘材料制成的层间绝缘膜；
(g)穿过第二层间绝缘膜至少形成一个通孔，当沿着平行于衬底法线方向看时，该通孔被包括在第一焊盘里；以及
(h)在第二层间绝缘膜上形成第二焊盘，第二焊盘通过通孔中的区域与第一焊盘相连。
3.根据权利要求2的方法，在步骤(h)之后，进一步包括下面一步：
(i)使导电探针与第二焊盘接触来检验半导体元件。
4.根据权利要求3的方法，在步骤(i)之后进一步包含下面一步：
(j)沿着第二焊盘内的一条线刻划半导体衬底。
5.根据权利要求1的方法，其中凸出区域不布置在第一框形区中。
6.根据权利要求1的方法，其中
凸出区域不留在第二框形区内侧的中心区域中；并且在(e)步骤之后，
这种方法进一步包含下列步骤：
在第一内层绝缘膜和剩下的第一薄膜上形成由绝缘材料制成的第二层间绝缘膜；
穿过第二层间绝缘膜形成通孔，当沿着平行于衬底法线的方向看时，通孔被包括在中心区域中；
在第二层间绝缘膜上形成第二焊盘，第二焊盘通过通孔中的区域与第一焊盘连接；并且
导线与第二焊盘引线接合，当沿着平行于衬底法线的方向看时，导线与第二焊盘之间的接触地区延伸到了通孔的更外侧上的区域。
7.半导体器件包括：
半导体衬底；
在半导体衬底上形成的由绝缘材料制成的第一层间绝缘膜；
在第一层间绝缘膜上形成的由绝缘材料制成的第一内层绝缘膜，形成的第一内层绝缘膜有一个到达它底面的凹槽，该凹槽有一个焊盘部分和连着这个焊盘部分的布线部分，焊盘部分的宽度宽于布线部分的宽度，焊盘部分留有许多凸出区域，并且凹槽的形成使得凸出区域以这样一种方式分布，即邻近布线区的凹槽区比率高于第二框形区的凹槽区比率，该邻近布线区重叠于布线地区延伸进焊盘地区的区域之上，且处在把焊盘部分的外边界线作为外边界线并具有第一个宽度的第一框形区之内，而第二框形区则把第一框形区的内边界线作为外边界线并具有第二个宽度；
第一焊盘填充在凹槽的焊盘部分；并且
布线填充在凹槽的布线部分。
8.根据权利要求7的半导体器件，进一步包括：
在第一内层绝缘膜、第一焊盘和布线上形成第二层间绝缘膜，第二层间绝缘膜至少有一个通孔，当沿着平行于衬底法线的方向看时，该通孔部分地重叠在第一焊盘上；并且
在第二层间绝缘膜上形成第二焊盘，第二焊盘通过通孔中的区域与第一焊盘连接。
9.根据权利要求7的半导体器件，其中的凸出区域不布置在邻近布线区。
10.根据权利要求7的半导体器件，其中的凸出区域不布置在第二框形区内侧的中心区域里。
11.根据权利要求7的半导体器件，其中当沿着与衬底法线平行的方向看时，通孔被包括在第一焊盘中。
12.根据权利要求7的半导体器件，其中凸出区域沿第一方向以第一间距规则地布置在第二框形区中，并且沿着该第一方向第一框形区的宽度等于或宽于第一间距。
13.根据权利要求8的半导体器件，进一步包括与第二焊盘引线结合的导电线，其中凸出区域不分布在第二框形区内侧的中心区域，通孔分布在中心区域，并且当沿着平行于衬底法线方向看时，导电线和第二焊盘之间的接触地区延伸到通孔更外侧上的区域。
CNB021061807A 2001-09-07 2002-04-08 能够抑制电流在焊盘里集中的半导体器件及其制造方法 Expired - Fee Related CN1231960C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP271416/2001 2001-09-07
JP2001271416A JP4801296B2 (ja) 2001-09-07 2001-09-07 半導体装置及びその製造方法

Publications (2)

Publication Number Publication Date
CN1404135A true CN1404135A (zh) 2003-03-19
CN1231960C CN1231960C (zh) 2005-12-14

Family

ID=19096929

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB021061807A Expired - Fee Related CN1231960C (zh) 2001-09-07 2002-04-08 能够抑制电流在焊盘里集中的半导体器件及其制造方法

Country Status (5)

Country Link
US (2) US7315072B2 (zh)
JP (1) JP4801296B2 (zh)
KR (1) KR100752026B1 (zh)
CN (1) CN1231960C (zh)
TW (1) TW544810B (zh)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100416581C (zh) * 2006-04-13 2008-09-03 华为技术有限公司 Fanout设计中自动调整线宽的方法及装置
CN102683313B (zh) * 2012-06-11 2017-03-08 上海华虹宏力半导体制造有限公司 半导体接合焊盘结构以及集成电路
CN108140577A (zh) * 2016-02-23 2018-06-08 瑞萨电子株式会社 半导体器件及其制造方法
CN109309019A (zh) * 2017-07-26 2019-02-05 中芯国际集成电路制造（天津）有限公司 测试结构和测试方法
CN109727942A (zh) * 2017-10-30 2019-05-07 拉碧斯半导体株式会社 半导体装置以及半导体装置的制造方法
CN110010544A (zh) * 2013-06-25 2019-07-12 台湾积体电路制造股份有限公司 具有与凹槽相对准的焊料区的封装件
CN111599794A (zh) * 2019-02-20 2020-08-28 夏普株式会社 半导体集成电路及耐压试验方法

Families Citing this family (56)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8021976B2 (en) * 2002-10-15 2011-09-20 Megica Corporation Method of wire bonding over active area of a semiconductor circuit
TWI300971B (en) * 2002-04-12 2008-09-11 Hitachi Ltd Semiconductor device
US7692315B2 (en) * 2002-08-30 2010-04-06 Fujitsu Microelectronics Limited Semiconductor device and method for manufacturing the same
JP4170103B2 (ja) * 2003-01-30 2008-10-22 Ｎｅｃエレクトロニクス株式会社 半導体装置、および半導体装置の製造方法
US6864578B2 (en) * 2003-04-03 2005-03-08 International Business Machines Corporation Internally reinforced bond pads
JP3891299B2 (ja) 2003-05-06 2007-03-14 セイコーエプソン株式会社 半導体装置の製造方法、半導体装置、半導体デバイス、電子機器
US20040262762A1 (en) * 2003-06-25 2004-12-30 Ming-Shuoh Liang Method of providing via in a multilayer semiconductor device
US20050230005A1 (en) * 2003-06-25 2005-10-20 Taiwan Semiconductor Manufacturing Co., Ltd. Test pad for reducing die sawing damage
DE10337569B4 (de) * 2003-08-14 2008-12-11 Infineon Technologies Ag Integrierte Anschlussanordnung und Herstellungsverfahren
JP4342892B2 (ja) 2003-09-30 2009-10-14 Ｎｅｃエレクトロニクス株式会社 半導体装置およびその製造方法
US7919864B2 (en) * 2003-10-13 2011-04-05 Stmicroelectronics S.A. Forming of the last metallization level of an integrated circuit
KR100705937B1 (ko) * 2003-12-19 2007-04-11 에스티마이크로일렉트로닉스 엔.브이. 실리콘 질화막의 스트레스를 방지 및 완충하는 패드구조를 구비한 반도체 장치
JP4280204B2 (ja) 2004-06-15 2009-06-17 Ｏｋｉセミコンダクタ株式会社 半導体装置
JP4063796B2 (ja) 2004-06-30 2008-03-19 日本電気株式会社 積層型半導体装置
US7242102B2 (en) * 2004-07-08 2007-07-10 Spansion Llc Bond pad structure for copper metallization having increased reliability and method for fabricating same
US8552559B2 (en) * 2004-07-29 2013-10-08 Megica Corporation Very thick metal interconnection scheme in IC chips
JP2006108329A (ja) 2004-10-04 2006-04-20 Fujitsu Ltd 半導体装置
US20060244156A1 (en) * 2005-04-18 2006-11-02 Tao Cheng Bond pad structures and semiconductor devices using the same
JP4713936B2 (ja) 2005-05-09 2011-06-29 株式会社東芝 半導体装置
WO2007066400A1 (ja) * 2005-12-08 2007-06-14 Fujitsu Limited 半導体装置
US7592710B2 (en) * 2006-03-03 2009-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Bond pad structure for wire bonding
JP5367235B2 (ja) * 2007-06-07 2013-12-11 スパンション エルエルシー 半導体装置の製造方法
JP2009021528A (ja) * 2007-07-13 2009-01-29 Toshiba Corp 半導体装置
JP5034740B2 (ja) * 2007-07-23 2012-09-26 ルネサスエレクトロニクス株式会社 半導体装置及びその製造方法
US20090087992A1 (en) * 2007-09-28 2009-04-02 Chartered Semiconductor Manufacturing Ltd. Method of minimizing via sidewall damages during dual damascene trench reactive ion etching in a via first scheme
US7851346B2 (en) * 2008-07-21 2010-12-14 Taiwan Semiconductor Manufacturing Company, Ltd. Bonding metallurgy for three-dimensional interconnect
US8288872B2 (en) 2008-08-05 2012-10-16 Taiwan Semiconductor Manufacturing Company, Ltd. Through silicon via layout
US7968975B2 (en) * 2008-08-08 2011-06-28 International Business Machines Corporation Metal wiring structure for integration with through substrate vias
US20100072615A1 (en) * 2008-09-24 2010-03-25 Maxim Integrated Products, Inc. High-Electrical-Current Wafer Level Packaging, High-Electrical-Current WLP Electronic Devices, and Methods of Manufacture Thereof
JP5537016B2 (ja) * 2008-10-27 2014-07-02 株式会社東芝 半導体装置および半導体装置の製造方法
US8581423B2 (en) * 2008-11-17 2013-11-12 Taiwan Semiconductor Manufacturing Company, Ltd. Double solid metal pad with reduced area
EP2444999A4 (en) * 2009-06-18 2012-11-14 Rohm Co Ltd SEMICONDUCTOR DEVICE
CN102013403B (zh) * 2009-09-04 2013-01-30 中芯国际集成电路制造(上海)有限公司 晶圆级芯片尺寸封装结构及其制造方法
JP5383446B2 (ja) * 2009-11-18 2014-01-08 パナソニック株式会社 半導体装置
JP5582879B2 (ja) * 2010-06-09 2014-09-03 株式会社東芝 半導体装置及びその製造方法
DE102011107349B4 (de) * 2010-06-30 2016-05-12 Micronas Gmbh Bondkontaktstelle auf einem Halbleitersubstrat
JP5610905B2 (ja) * 2010-08-02 2014-10-22 パナソニック株式会社 半導体装置
US8896125B2 (en) * 2011-07-05 2014-11-25 Sony Corporation Semiconductor device, fabrication method for a semiconductor device and electronic apparatus
US9064707B2 (en) * 2011-09-14 2015-06-23 Micronas Gmbh Bonding contact area on a semiconductor substrate
US8785248B2 (en) 2011-10-10 2014-07-22 Maxim Integrated Products, Inc. Wafer level packaging using a lead-frame
US8785244B2 (en) 2011-10-10 2014-07-22 Maxim Integrated Products, Inc. Wafer level packaging using a lead-frame
US9431039B1 (en) 2013-05-21 2016-08-30 Western Digital (Fremont), Llc Multiple sensor array usable in two-dimensional magnetic recording
US8891207B1 (en) 2013-06-07 2014-11-18 Western Digital (Fremont), Llc Connection schemes for a multiple sensor array usable in two-dimensional magnetic recording
US8908333B1 (en) 2013-08-13 2014-12-09 Western Digital (Fremont), Llc Shield designed for middle shields in a multiple sensor array
US9431032B1 (en) 2013-08-14 2016-08-30 Western Digital (Fremont), Llc Electrical connection arrangement for a multiple sensor array usable in two-dimensional magnetic recording
US8988812B1 (en) 2013-11-27 2015-03-24 Western Digital (Fremont), Llc Multi-sensor array configuration for a two-dimensional magnetic recording (TDMR) operation
US9245846B2 (en) * 2014-05-06 2016-01-26 International Business Machines Corporation Chip with programmable shelf life
US9087527B1 (en) 2014-10-28 2015-07-21 Western Digital (Fremont), Llc Apparatus and method for middle shield connection in magnetic recording transducers
JP2016092061A (ja) * 2014-10-30 2016-05-23 株式会社東芝 半導体装置および固体撮像装置
US9786301B1 (en) 2014-12-02 2017-10-10 Western Digital (Fremont), Llc Apparatuses and methods for providing thin shields in a multiple sensor array
US9831193B1 (en) * 2016-05-31 2017-11-28 Texas Instruments Incorporated Methods and apparatus for scribe street probe pads with reduced die chipping during wafer dicing
KR200488291Y1 (ko) 2018-11-19 2019-01-09 안창선 블루투스스피커가 내장된 칫솔 살균장치
JP2020123697A (ja) * 2019-01-31 2020-08-13 キヤノン株式会社 半導体装置、半導体ウエハ、機器、製造方法
JP7459490B2 (ja) 2019-11-28 2024-04-02 株式会社ソシオネクスト 半導体ウェハ及び半導体装置
KR20220033598A (ko) 2020-09-08 2022-03-17 삼성전자주식회사 반도체 패키지
CN113053846B (zh) * 2021-03-19 2023-04-11 云南创视界光电科技有限公司 芯片和具有其的显示模组

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0677278A (ja) * 1992-08-28 1994-03-18 Kawasaki Steel Corp 半導体装置およびボンディング方法
JP3482779B2 (ja) * 1996-08-20 2004-01-06 セイコーエプソン株式会社 半導体装置およびその製造方法
JP3526376B2 (ja) * 1996-08-21 2004-05-10 株式会社東芝 半導体装置及びその製造方法
JP3481812B2 (ja) * 1997-02-14 2003-12-22 株式会社ルネサステクノロジ 配線層にスリットを有する半導体装置または半導体ウエーハ及びその製造方法
JPH1154508A (ja) * 1997-07-30 1999-02-26 Sanyo Electric Co Ltd 半導体装置及び半導体装置の製造方法
JPH11150114A (ja) 1997-11-19 1999-06-02 Ricoh Co Ltd 半導体装置及びその製造方法
US6016000A (en) * 1998-04-22 2000-01-18 Cvc, Inc. Ultra high-speed chip semiconductor integrated circuit interconnect structure and fabrication method using free-space dielectrics
JP3239843B2 (ja) * 1998-05-11 2001-12-17 関西日本電気株式会社 半導体装置の製造方法
JPH11345847A (ja) * 1998-06-02 1999-12-14 Matsushita Electric Ind Co Ltd 半導体ウエハ及び半導体装置の製造方法
US6163074A (en) * 1998-06-24 2000-12-19 Samsung Electronics Co., Ltd. Integrated circuit bonding pads including intermediate closed conductive layers having spaced apart insulating islands therein
JP3898350B2 (ja) * 1998-08-06 2007-03-28 富士通株式会社 半導体装置
JP2974022B1 (ja) * 1998-10-01 1999-11-08 ヤマハ株式会社 半導体装置のボンディングパッド構造
JP2001196413A (ja) * 2000-01-12 2001-07-19 Mitsubishi Electric Corp 半導体装置、該半導体装置の製造方法、ｃｍｐ装置、及びｃｍｐ方法
JP4979154B2 (ja) * 2000-06-07 2012-07-18 ルネサスエレクトロニクス株式会社 半導体装置
KR20030001590A (ko) * 2001-06-25 2003-01-08 주식회사 하이닉스반도체 듀얼 다마센 공정을 이용한 배선 형성 방법
US7119006B2 (en) * 2002-11-26 2006-10-10 Texas Instruments Incorporated Via formation for damascene metal conductors in an integrated circuit
JP5089850B2 (ja) * 2003-11-25 2012-12-05 ルネサスエレクトロニクス株式会社 半導体装置

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100416581C (zh) * 2006-04-13 2008-09-03 华为技术有限公司 Fanout设计中自动调整线宽的方法及装置
CN102683313B (zh) * 2012-06-11 2017-03-08 上海华虹宏力半导体制造有限公司 半导体接合焊盘结构以及集成电路
CN110010544A (zh) * 2013-06-25 2019-07-12 台湾积体电路制造股份有限公司 具有与凹槽相对准的焊料区的封装件
US10879198B2 (en) 2013-06-25 2020-12-29 Taiwan Semiconductor Manufacturing Company, Ltd. Package with solder regions aligned to recesses
CN108140577A (zh) * 2016-02-23 2018-06-08 瑞萨电子株式会社 半导体器件及其制造方法
CN109309019A (zh) * 2017-07-26 2019-02-05 中芯国际集成电路制造（天津）有限公司 测试结构和测试方法
CN109309019B (zh) * 2017-07-26 2020-08-28 中芯国际集成电路制造（天津）有限公司 测试结构和测试方法
CN109727942A (zh) * 2017-10-30 2019-05-07 拉碧斯半导体株式会社 半导体装置以及半导体装置的制造方法
CN109727942B (zh) * 2017-10-30 2023-11-07 拉碧斯半导体株式会社 半导体装置以及半导体装置的制造方法
CN111599794A (zh) * 2019-02-20 2020-08-28 夏普株式会社 半导体集成电路及耐压试验方法
CN111599794B (zh) * 2019-02-20 2022-11-04 深圳通锐微电子技术有限公司 半导体集成电路及耐压试验方法

Also Published As

Publication number Publication date
US20030047794A1 (en) 2003-03-13
US7315072B2 (en) 2008-01-01
JP2003086589A (ja) 2003-03-20
KR20030022017A (ko) 2003-03-15
US20070287283A1 (en) 2007-12-13
KR100752026B1 (ko) 2007-08-28
JP4801296B2 (ja) 2011-10-26
TW544810B (en) 2003-08-01
US7550376B2 (en) 2009-06-23
CN1231960C (zh) 2005-12-14

Similar Documents

Publication Publication Date Title
CN1231960C (zh) 能够抑制电流在焊盘里集中的半导体器件及其制造方法
CN1309070C (zh) 半导体器件及其制造方法
US7795128B2 (en) Method of manufacturing a semiconductor device having an enhanced electrode pad structure
CN1893020A (zh) 半导体器件及其制造方法
US20090008750A1 (en) Seal ring for semiconductor device
CN1893076A (zh) 半导体器件及其制造方法
CN1819124A (zh) 半导体器件及其制造方法
CN1250951A (zh) 半导体器件及其制造方法
CN1790702A (zh) 改进的hdp氮化物基ild盖层
US6495448B1 (en) Dual damascene process
US7759803B2 (en) Semiconductor device and method of manufacturing the same
JP2019012738A (ja) 半導体装置およびその製造方法
US6794732B2 (en) Semiconductor device and method of manufacturing the same
CN1134835C (zh) 半导体器件及其制造方法
US6960492B1 (en) Semiconductor device having multilayer wiring and manufacturing method therefor
CN1750249A (zh) 集成电路中的半导体装置及其制造方法
CN1230790A (zh) 具有导线插头的半导体器件及其生产方法
CN101047163A (zh) 半导体器件及其制造方法
CN1957465A (zh) 半导体器件及配线基板
CN1237787A (zh) 半导体器件及其制造方法
JP5041088B2 (ja) 半導体装置
CN1399329A (zh) 半导体器件
KR100445077B1 (ko) 반도체소자의 제조방법
CN1652330A (zh) 半导体器件及其制造方法
CN107527821A (zh) 半导体装置及其制造方法

Legal Events

Date Code Title Description
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
C41 Transfer of patent application or patent right or utility model
TR01 Transfer of patent right

Effective date of registration: 20081219

Address after: Tokyo, Japan

Patentee after: Fujitsu Microelectronics Ltd.

Address before: Kanagawa, Japan

Patentee before: Fujitsu Ltd.

ASS Succession or assignment of patent right

Owner name: FUJITSU MICROELECTRONICS CO., LTD.

Free format text: FORMER OWNER: FUJITSU LIMITED

Effective date: 20081219

C56 Change in the name or address of the patentee

Owner name: FUJITSU SEMICONDUCTOR CO., LTD.

Free format text: FORMER NAME: FUJITSU MICROELECTRON CO., LTD.

CP01 Change in the name or title of a patent holder

Address after: Kanagawa

Patentee after: FUJITSU MICROELECTRONICS Ltd.

Address before: Kanagawa

Patentee before: Fujitsu Microelectronics Ltd.

CP02 Change in the address of a patent holder

Address after: Kanagawa

Patentee after: Fujitsu Microelectronics Ltd.

Address before: Tokyo, Japan

Patentee before: Fujitsu Microelectronics Ltd.

CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20051214

Termination date: 20200408

CF01 Termination of patent right due to non-payment of annual fee