CN1819124A - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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Publication number
CN1819124A
CN1819124A CNA2005100824568A CN200510082456A CN1819124A CN 1819124 A CN1819124 A CN 1819124A CN A2005100824568 A CNA2005100824568 A CN A2005100824568A CN 200510082456 A CN200510082456 A CN 200510082456A CN 1819124 A CN1819124 A CN 1819124A
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Prior art keywords
conversion coating
remove
pad electrode
semiconductor device
electrode
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CNA2005100824568A
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CN100440460C (zh
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村田浩一
生云雅光
渡边英二
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Fujitsu Semiconductor Ltd
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Fujitsu Ltd
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Abstract

一种半导体器件制造方法，包括以下步骤：(a)在半导体器件上形成焊盘电极；(b)将有机电介质膜涂于该半导体器件的表面，以露出该焊盘电极的中心部分；(c)通过干蚀刻处理该焊盘电极的露出表面；以及(d)使用无氧干处理去除因用于表面处理的干蚀刻引起的、在有机电介质膜中产生的转化层。

Description

半导体器件及其制造方法
技术领域
本发明主要涉及一种具有突起电极(或突出电极)的半导体器件及其制造方法，特别涉及因从金属表面(例如金属焊盘)去除自然氧化物的干蚀刻工艺引起的、在有机电介质表面区域中生成的转化层的去除，以防止表面漏电(leakage)。
背景技术
在半导体器件例如IC芯片上设置突出电极或突起电极已成为主流，该技术可将芯片直接安装在衬底上。近些年以来，随着半导体器件和封装的微型化，突起间距变得越来越窄。
突起形成于焊盘电极上以提供与内部电极的电连接。通常，为了保护器件，半导体器件的表面覆盖有钝化膜，其上又涂覆有机电介质例如聚酰亚胺的涂覆膜。在有机电介质和钝化膜中形成开口，以露出焊盘表面。在露出的焊盘表面上形成籽晶层之前，作为预处理，使用氩(Ar)气进行干蚀刻(RF蚀刻)，以便从焊盘表面去除自然氧化物。
在干蚀刻过程中，有机电介质表面区域的膜性质被改变，并且由于转化层引起有机涂层的电绝缘能力降低。为解决此问题，提出了在制造突起电极之后，通过利用微波(MW)灰化机或RF灰化机进行O2灰化而去除转化层。例如，参见JP 10-56020A和JP 7-130750A。
图1示出了如何使用传统技术去除聚酰亚胺转化层。经由电介质层111而在半导体晶片110上形成铝(Al)或铝合金焊盘101。焊盘101电连接至内部电极，例如栅电极(未示出)。
在钝化膜102和聚酰亚胺膜103中形成开口108，以便露出焊盘101的中心。为了从焊盘101的露出表面去除自然氧化层(未示出)，利用氩离子进行干蚀刻。由于干蚀刻的影响，在聚酰亚胺膜103的表面区域生成转化层104。
然后，通过溅射，在已经去除了自然氧化膜的焊盘101和聚酰亚胺层103(包括转化层104)上依序沉积钛(Ti)膜105和铜(Cu)膜106。在铜(Cu)膜106上设置具有预定图案的抗蚀掩模(未示出)以形成突起电极107。然后，去除抗蚀掩模，并使用突起电极107作为掩模去除Cu膜106和Ti膜105的多余部分。然后，利用O2气进行微波(WM)灰化，以去除突起电极107之间的聚酰亚胺转化层104。
通常从有机电介质包围的导电表面，而不是从焊盘表面去除自然氧化物层。如果使用干处理去除自然氧化层，则在有机电介质膜上生成转化层。例如，当在内插板(interposer)或再分布层上制造电连接至焊盘电极的铜(Cu)互连时，或者在上层和下层互连之间形成用于电连接的接触孔时，导电表面在开口或接触孔中露出。由于用于从导电表面去除自然氧化层的等离子蚀刻的影响，中间层有机电介质的上表面退化或转化。在WO 99/38208中提出通过利用O2气、氧基团或臭氧进行光激发灰化来去除多层接线板中的中间层有机电介质转化层。
图1所示用于去除有机电介质的转化或退化层的传统方法是基于如下假设，即使用TAB(卷带自动接合)型镀金(Au)突起。由于金(Au)是一种稳定金属，在O2灰化过程中突起表面很难被氧化。然而，根据图1所述方法，由于对聚酰亚胺的蚀刻速率较低，因此转化层不能被完全去除。因此，在电阻约为1.0×106Ω时会发生漏电。可以推断出突起可作为避雷器(lightning arresters)而引起蚀刻速率的降低。特别当电极107以突起或底部突起(under bump)金属(UBM)形式形成于聚酰亚胺层102之上时，就变得很难去除相邻焊盘之间的聚酰亚胺转化层103。
图1所示的传统方法的另一问题是该技术不适用于焊接突起或铜(Cu)互连。如果在形成焊接突起后执行O2灰化以去除转化层，则突起表面被氧化，并且氧化碎片落到有机电介质(例如聚酰亚胺层)的表面。此外，微波离子蚀刻通常使聚酰亚胺层的表面退化，导致其被锈蚀(tarnish)。
发明内容
为了克服上述问题，如图2所示，可以建议提前在聚酰亚胺层103上形成切口109以保证电极的隔离。基于该结构，即使聚酰亚胺层103的表面区域的性质改变，因用于去除自然氧化物的干蚀刻处理产生了转化层104，由于切口109的存在而能够防止漏电。
然而，随着突起间距变得越来越窄，就变得越难保证界定切口109的充分面积。此外，钝化膜102和聚酰亚胺层103的侧边在切口109中露出。由于钝化膜102与底层填充材料的附着力与聚酰亚胺层103不同，则在装配过程中很难保持统一。
因此，本发明的一个目的是提供一种在防止有机涂层锈蚀的同时有效去除有机电介质上的转化层的技术。
本发明的另一目的是提供一种具有可靠特性并减少了表面漏电的半导体器件。
为实现本发明的目的，不使用O2灰化而去除在半导体器件的有机电介质上产生的转化层。
在本发明的一个方案中，提供一种使用只受到较少损坏的有机电介质层的半导体器件。该半导体器件包括：
(a)焊盘电极，设置于半导体晶片上的预定位置；
(b)有机电介质膜，覆盖该半导体晶片且露出该焊盘电极的中心部分；
(c)转化层，位于该有机电介质膜的表面区域；以及
(d)导体，连接到该焊盘电极；
其中，设置转化层去除区域以将该导体与相邻的导体相隔离，并且在该转化层去除区域过蚀刻该有机电介质膜，过蚀刻深度为10nm到100nm。
在本发明的另一方案中，提供一种制造半导体器件的方法，其中设置在有机电介质层的表面区域中产生的转化层被去除的部分。该方法包括以下步骤：
(a)在该半导体器件上形成焊盘电极；
(b)用有机电介质膜涂于该半导体器件的表面，以露出该焊盘电极的中心部分；
(c)通过干蚀刻处理该焊盘电极的露出表面；
(d)使用无氧干处理，去除因用于表面处理的干蚀刻引起的、在有机电介质膜中产生的转化层。
通过不使用氧，在去除转化层的过程中就能够防止导体表面的氧化。
在一优选实例中，该无氧干处理是在无氧气体供给条件下的射频(RF)等离子体蚀刻。
无氧RF等离子体蚀刻可有效去除转化层，同时在去除转化层过程中能够防止有机电介质膜的表面退化，例如锈蚀。
附图说明
通过结合附图阅读下面的详细说明，本发明的其他目的、特征和优点将会变得更清楚。附图中：
图1是解释用于去除聚酰亚胺转化层的传统方法的视图；
图2是说明在聚酰亚胺转化层和钝化膜中形成切口以电性隔离相邻电极的提议的视图；
图3A到图3F说明了基于本发明第一实施例的半导体器件制造过程；
图4A到图4G说明了第一实施例的半导体器件制造过程的修改；
图5A到图5G说明了基于本发明第二实施例的半导体器件制造过程；
图6A到图6C说明了图5D步骤的后续步骤，示出了第二实施例的半导体器件制造过程的修改；
图7A到图7D说明了图5D步骤的后续步骤，示出了第二实施例的半导体器件制造过程的另一修改；
图8A到图8F说明了基于本发明第三实施例的半导体器件制造过程；
图9A和图9B说明了基于本发明第四实施例的半导体器件制造过程。
具体实施方式
下面参考附图说明本发明的优选实施例。
图3A到图3F说明了基于本发明第一实施例的半导体器件制造过程。
首先，如图3A所示，在半导体晶片20的预定位置上形成铝(Al)焊盘11，在该半导体晶片20中形成内部电路(未示出)并被电介质层覆盖。焊盘11提供与内部电路的电连接。焊盘11和半导体晶片20的整个表面被钝化膜(覆盖膜)12覆盖。在钝化膜12中形成开口，以露出Al焊盘11的表面。然后，在露出的Al焊盘11和钝化膜12上形成感光性或非感光性的聚酰亚胺保护层(有机涂层)13。按照设计，聚酰亚胺膜13的厚度是1μm到20μm。在聚酰亚胺膜13的预定位置进行蚀刻以形成开口23，从而露出Al焊盘11。然后，作为溅射前的预处理，使用氩(Ar)气进行射频RF蚀刻，以从露出的铝焊盘11表面去除自然氧化物层(未示出)。在干蚀刻过程中，改变了聚酰亚胺膜13的表面区域，并产生转化层14。在转化层14中，电阻水平下降到1.0×104Ω，并且作为漏电层。因此，在后面的步骤中转化层被去除。
然后，如图3B所示，通过溅射依次形成钛(Ti)膜15和铜(Cu)膜16，从而形成籽晶层25。
然后，如图3C所示，形成抗蚀层(resist)17，该抗蚀层17在对应于Al焊盘11的位置具有开口图案，并通过电镀依序形成镍(Ni)膜18和焊料19。焊料19可由适当的材料，例如Sn/Cu、Sn/Ag、Sn/Ag/Cu或Pb/Sn而形成。
然后，如图3D所示，利用例如有机溶剂去除抗蚀层17。将Ni镀膜18用作掩模，Cu膜16和Ti膜15的多余部分也通过湿蚀刻的方法而被去除。
然后，如图3E所示，利用配有13.56MHzRF电源的蚀刻/灰化装置(未示出)，通过氮(N2)蚀刻而从相邻焊料镀层19之间延伸的区域去除转化层14。在以40Pa的气压供给500sccm氮(N2)气的条件下，以200W的功率执行60秒的干蚀刻。处理温度小于等于焊料的熔点。在去除转化层14之后，电阻水平上升到1.0×1011Ω或更高，并且聚酰亚胺膜13的电绝缘层被恢复。
然后，如图3F所示，进行回流处理以形成突起22，从而完成了一个半导体器件10。在转化层14中形成凹槽或去除区域21，从该区域通过不使用氧的蚀刻而去除转化层14。凹槽或去除区域21保证相邻突起22之间的电隔离。
在第一实施例中，射频(RF)蚀刻被用于去除转化层。即使相邻电极间的间隙较窄，RF等离子体也能够到达聚酰亚胺层13的上表面。从而，即使在形成了焊料镀层19之后也能够去除转化层14。
如图3E中所示的实例，相邻焊料镀层19问的间隙约10μm到20μm这样窄；然而，可以通过使用RF蚀刻以可靠的方法去除转化层14。预期相邻焊料镀层19间的间隙能够随着半导体器件的微型化而变成10μm或更小。根据第一实施例的技术，只要间隙在2μm到100μm的范围内就能够去除转化层14。
突起或突出电极22需要具有一定的高度，以便在半导体器件10安装到主插件板或封装板之后避免不利的影响例如热应力。即使间距较窄的焊料镀层19具有100μm到120μm的高度，第一实施例的布置也能够允许通过RF蚀刻而去除转化层14。
由于在RF蚀刻过程中未使用氧气，就能够防止对焊料镀层19表面的不希望有的氧化。这意味着在回流处理之前或之后都可进行转化层14的去除。
在去除转化层14的过程中，聚酰亚胺膜13的上表面被轻度过蚀刻(未示出)。与微波O2灰化不同，过蚀刻深度小到10nm到20nm，且装配特性仍然符合要求。由于聚酰亚胺膜13的过蚀刻深度可以在10nm到100nm的范围内变化，该范围允许较好地维持装配特性，根据焊料镀层19的高度和间距，能够在该范围内适当地调节蚀刻条件。
RF蚀刻的另一优势是可以防止由微波(MW)蚀刻引起的聚酰亚胺表面的表面退化或锈蚀。
作为用于去除转化层14的蚀刻气体，除了N2气，可以使用H2气、Ne气、He气或者其混合物(例如，N2-H2)。
图4A到图4G说明了第一实施例的半导体器件制造过程的修改。图4A到图4D所示的步骤与图3A到图3D所示的步骤相同，因而省略对他们的解释。
在图4E中，在图4D的步骤后进行回流处理以形成焊料突起22，其中去除了多余的抗蚀层17和籽晶层25。
然后，如图4F所示，利用配有13.56MHzRF电源的蚀刻/灰化装置(未示出)，通过氮(N2)蚀刻而从在相邻的焊料突起22间延伸的区域去除转化层14。在以40Pa的气压供给500sccm氮(N2)气的条件下，以200W的功率执行60秒的干蚀刻。在去除转化层14之后，电阻恢复到了1.0×1011Ω或更高。
然后，如图4G所示，再一次进行回流处理以净化(purge)焊料突起22的表面。图4G所示的回流处理是可选的，只要装配特性未被破坏也可以不执行。通常，可在图4F的步骤中结束制造过程，这是因为无氧RF蚀刻被用来去除转化层14，因而突起22的表面保持了充分的清洁。
该修改能够实现与结合图3A到图3F所示处理所描述的相同的优点。
图5A到图5G说明了基于本发明第二实施例的半导体器件的制造过程。在第二实施例中，由于Ti粒子防止灰化处理，所以在去除转化层14的干处理之前，在Ti膜15(籽晶层25的底层)的溅射过程中注入聚酰亚胺(包括转化层14)的钛(Ti)粒子通过轻度湿蚀刻而从转化层14被去除。
图5A到图5D所示的步骤与图3A到图3D所示的步骤相同。也就是，通过使用氩(Ar)气的RF蚀刻而从在开口23中露出的铝(Al)焊盘11去除自然氧化层。形成包括钛(Ti)膜15和铜(Cu)膜16的籽晶层25。利用具有预定开口图案的抗蚀层17，依序进行镍(Ni)电镀和焊料电镀。然后，去除抗蚀层17和Cu膜16与Ti膜15的多余部分。
然后，如图5E所示，使用0.5％的氢氟(HF)酸进行轻度湿蚀刻，以去除注入聚酰亚胺(包括转化层14)表面区域的钛(Ti)粒子。该湿处理保证了后续步骤的干蚀刻速率。
然后，如图5F所示，进行使用氮(N2)气的RF蚀刻，或者使用现有的微波灰化机，在供给氮(N2)气的条件下进行灰化处理。为了方便，用“MW灰化”表示使用现有的微波(MW)灰化机以用于去除转化层14的干处理。
在进行RF蚀刻中，蚀刻条件可与第一实施例中设置的相同。由于已经去除了钛(Ti)粒子，可以将RF功率设置的更低。当使用了现有的MW灰化机时，重复进行三次N2灰化，每一次都在以0.6乇(torr)的气压供给500sccm到1000sccm的氮(N2)气的条件下，以1500W的功率和150℃的温度执行60秒。在该干处理之后，聚酰亚胺层13的电阻水平恢复到1.0×1011Ω或更高。
最后，如图5G所示，进行回流处理以形成突起22，从而完成半导体器件10。由于相邻突起22通过转化层去除区域21而彼此电性隔离，减少了结漏电并提高了运行可靠性。尽管未在图中示出，在转化层去除区21中，以10nm到20nm的深度轻度过蚀刻聚酰亚胺层的上表面。
在第二实施例中，在干处理之前进行湿处理，以去除注入转化层14中的钛(Ti)粒子。该布置允许将现有的微波(MW)灰化机用于转化层的去除。然而，考虑到聚酰亚胺层13的过蚀刻深度和表面退化(例如锈蚀)，即使当干处理与湿处理相结合时也需要使用RF蚀刻。
图6A到图6C示出了第二实施例的半导体器件制造过程的修改。图6A所示步骤位于图5D所示步骤之后。
在图6A中，在去除了Cu膜16和Ti膜15的多余部分之后进行回流处理，从而形成突起或突出电极22。在回流后，使用0.5％的氢氟(HF)酸进行轻度湿蚀刻，以去除注入转化层14的钛(Ti)粒子。由于回流处理引起焊料镀层19产生变形以包围突起22下面的钛(Ti)膜15，在回流后通过进行轻度湿蚀刻，能够防止钛(Ti)膜15的侧面蚀刻。
然后，如图6B所示，通过使用氮(N2)气的RF蚀刻或在氮气供给的条件下使用现有的MW灰化机的微波(MW)蚀刻而去除转化层14。
然后，如图6C所示，再一次进行回流处理以净化突起22的表面。该步骤是可选的，特别是当N2 RF蚀刻用于去除转化层14时，可以不执行该步骤。
图7A到图7D示出了第二实施例的半导体器件制造过程的另一修改。在该修改中，在籽晶层的多余部分被去除后进行轻度湿蚀刻，然后，进行回流处理。然后，通过N2 RF蚀刻或N2 MW灰化去除转化层。
图7A所示步骤位于图5D所示步骤之后。在图7A中，通过湿蚀刻去除形成籽晶层25的铜(Cu)膜16和钛(Ti)膜15的多余部分，然后，通过轻度湿蚀刻去除注入转化层14的钛(Ti)粒子。该布置的优势在于可以连续进行湿处理，并且可以防止由Ti蚀刻剂引起的铜(Cu)的溶解。
然后，如图7B所示，进行回流处理以形成突起(或突出电极)22。
然后，如图7C所示，通过在氮(N2)气供给的条件下的RF蚀刻或者通过在氮气供给条件下使用现有的MW灰化机的微波灰化而去除转化层14。
此时可以结束处理，或者，如图7D所示，可以选择进行回流处理以净化突起22的表面。
在任一修改中，都能够通过结合轻度湿处理和无氧干处理以可靠的方式去除在相邻突起22间延伸的转化层14。
图8A到图8F说明了基于本发明第三实施例的半导体器件的制造过程。在第三实施例中，在底部突起金属化(UBM)之后，通过干处理而去除转化层14。
如图8A所示，通过使用氩(Ar)气的RF蚀刻而从铝(Al)焊盘11的露出表面去除自然氧化物层。在该图中，为了方便起见略去了形成有铝焊盘11的半导体晶片。自然氧化物去除蚀刻引起聚酰亚胺膜13的表面区域的改变。
然后，如同8B所示，依序溅射钛(Ti)膜15和铜(Cu)膜16以形成籽晶层25。
然后，如同8C所示，在相应于铝焊盘11的位置形成具有开口图案的抗蚀层17。利用抗蚀图案17，依序进行镍(Ni)电镀和金(Au)电镀以形成用于底部突起金属化(UBM)的Ni镀层18和Au镀层24。
然后，如图8D所示，去除抗蚀图案17，并将Ni镀层18用作掩模以去除Cu膜16和Ti膜15的多余部分。
然后，如图8E所示，通过使用例如N2、N2-H2、He、H2和Ne气体的RF蚀刻而去除转化层14。在底部突起金属化之后去除转化层14，并在这种情况下，没有必要在突起间的狭窄间隙中引入等离子体。此时，可用现有的微波(MW)灰化机进行MW灰化来替代无氧RF蚀刻。当使用MW灰化机时，可以使用N2、N2-H2、He、H2、Ne和氧混合气体。
作为氧混合气体的实例，可以使用CHF3/O2。这种情况下，在功率为1000W、阶段(stage)温度为150℃、气压为0.6乇以及气流为15/485sccm的条件下进行30秒的灰化。当在此MW灰化中使用例如O2/CF4或者O2/SF4的氧(O2)气或其他类型的氧混合气体时，在进行预定量的蚀刻之前，聚酰亚胺层13的表面会退化，引起锈蚀。
最后，如图8F所示，使用印刷方法形成突起(突出电极)22，从而完成半导体器件10。
在第三实施例中，在底部突起金属化之后去除转化层14，从而可以使用现有的微波(MW)灰化机。通过在UBM顶部上设置金(Au)薄膜，可以使用特定类型的氧混合气体以用于微波灰化。然而，从防止镍(Ni)镀层18的侧边氧化的角度将优选使用无氧蚀刻气体。
图9A和图9B说明了基于本发明第四实施例的半导体器件的制造过程。在第四实施例中，转化层的去除被应用于再分布层(RDL)上铜(Cu)互连的形成。
图9A包括再分布层的横截面图和俯视图，在该再分布层中形成铜(Cu)互连31，且转化层14仍留在晶片上。
在形成铜(Cu)互连31之前，连接到内部电极(未示出)的铝(Al)焊盘11形成于半导体晶片20上，该半导体晶片具有被中间层电介质覆盖的预定电路(未示出)。在铝(Al)焊盘11和整个半导体晶片20的表面上形成钝化(覆盖)膜12。在钝化膜12中的预定位置形成开口以露出铝(Al)焊盘11的上表面。然后，在露出的铝焊盘11和钝化膜12上形成聚酰亚胺膜(有机涂层)13。蚀刻聚酰亚胺膜13以在预定位置形成开口23，从而露出铝(Al)焊盘11的上表面。通过干蚀刻对铝(Al)焊盘11的露出表面进行预处理以去除自然氧化物层(未示出)。在干蚀刻过程中，聚酰亚胺膜13的表面区域被改变并产生转化层14。转化层14作为漏电层，且电阻水平下降到1.0×104Ω。
然后，依序溅射钛(Ti)膜15和铜(Cu)膜16以形成籽晶层25。形成抗蚀图案(未示出)以进行铜(Cu)电镀，从而形成铜互连31。去除抗蚀剂，并且去除铜膜16和钛膜15的多余部分。
然后，如图9B所示，通过使用例如N2、N2-H2、He、H2或者Ne等无氧气体的RF蚀刻而去除转化层14。在第四实施例中，从在铜(Cu)互连31之间延伸的较宽区域去除转化层14。从而，可以使用现有的微波(MW)灰化机而取代进行RF蚀刻。这种情况下，可以使用N2、N2-H2、He、H2、Ne和氧混合气体。
作为氧混合气体的实例，可以使用CF4/O2气体。这种情况下，进行两次灰化处理，每次处理都在功率为1000W、阶段温度为150℃、气压为0.6乇以及气流为4/196sccm的条件下进行30秒。从防止铜(Cu)互连31的表面氧化以及防止聚酰亚胺膜13的过量蚀刻与表面退化的角度考虑，优选采用无氧RF蚀刻以去除转化层14。
如上所述，在第一到第四实施例中的任何一个中，都可通过无氧RF蚀刻有效的去除聚酰亚胺膜表面区域中产生的转化层。
根据具体情况，可以使用现有的微波(MW)灰化机。为了保持聚酰亚胺膜表面状态良好并保证符合要求的装配特性，需要使用RF蚀刻。
有机涂层不局限于聚酰亚胺，也可使用酚醛树脂。效果相同，并可通过无氧干处理有效的去除转化层。
该专利申请基于并要求于2005年2月9日申请的日本专利申请号2005-033548的在先申请日期的权益，此处通过参考援引其全部内容。

Claims (20)

1.一种半导体器件，包括：
焊盘电极，设置于半导体晶片上的预定位置；
有机电介质膜，覆盖该半导体晶片且露出该焊盘电极的中心部分；
转化层，位于该有机电介质膜的表面区域；以及
导体，连接到该焊盘电极；
其中，设置转化层去除区域以将该导体与相邻的导体相隔离，并且在该转化层去除区域过蚀刻该有机电介质膜，过蚀刻深度为10nm到100nm。
2.如权利要求1所述的半导体器件，其中该导体是用于器件安装的突出电极，并且相邻突出电极间的间距为2μm到100μm。
3.如权利要求1所述的半导体器件，其中该导体是用于器件安装的突出电极，并且该突出电极的高度是5μm到120μm。
4.如权利要求1所述的半导体器件，其中该导体是再分布层的金属互连。
5.一种用于制造半导体器件的方法，包括以下步骤：
在该半导体器件上形成焊盘电极；
将有机电介质膜涂于该半导体器件的表面，以露出该焊盘电极的中心部分；
通过干蚀刻处理该焊盘电极的露出表面；
采用无氧干处理去除因用于表面处理的干蚀刻引起的、在该有机电介质膜中产生的转化层。
6.如权利要求5所述的方法，其中该无氧干处理是在无氧气体供给的条件下的射频(RF)等离子体蚀刻。
7.如权利要求6所述的方法，其中该RF等离子体蚀刻是以等于或低于400W的功率和等于或低于焊料熔点的温度条件下进行的。
8.如权利要求5所述的方法，还包括以下步骤：
在该无氧干处理之前对该转化层的表面进行轻度湿蚀刻；
其中，该无氧干处理是在无氧气体供给的条件下的干蚀刻或灰化。
9.如权利要求8所述的方法，还包括以下步骤：
在该焊盘电极上形成籽晶层；
其中，该轻度湿蚀刻使用蚀刻剂，以去除注入该转化层的该籽晶层的金属粒子。
10.如权利要求5所述的方法，其中该无氧气体包括N2、H2、Ne、He及其混合气体。
11.如权利要求5所述的方法，还包括以下步骤：
在该焊盘电极上形成突出电极；
其中，在形成该突出电极后去除该转化层。
12.如权利要求11所述的方法，还包括以下步骤：
对该突出电极进行回流处理；
其中，在该回流处理前去除该转化层。
13.如权利要求11所述的方法，还包括以下步骤：
对该突出电极进行回流处理；
其中，在该回流处理后去除该转化层。
14.如权利要求13所述的方法，还包括以下步骤：
在去除该转化层后，对该突出电极进行第二次回流处理。
15.如权利要求5所述方法，还包括以下步骤：
在该焊盘电极上形成突出电极；
其中，在形成该突出电极前去除该转化层。
16.如权利要求5所述的方法，还包括以下步骤：
在该焊盘电极上形成再分布金属互连；
其中，在形成该金属互连后去除该转化层。
17.如权利要求5所述的方法，还包括以下步骤：
在该无氧干处理之前对该转化层的表面进行轻度湿蚀刻；
其中，通过射频等离子体或微波等离子体去除该转化层。
18.一种用于制造半导体器件的方法，包括以下步骤：
在该半导体器件上形成焊盘电极；
将有机电介质膜涂于该半导体器件的表面，以露出该焊盘电极的中心部分；
通过干蚀刻处理该焊盘电极的露出表面；
采用氧混合气体去除因用于表面处理的干蚀刻引起的、在该有机电介质膜中产生的转化层；以及
在该焊盘电极上形成导体。
19.如权利要求18所述的方法，还包括以下步骤：
在去除该转化层后在该焊盘电极上形成突出电极；
其中，该氧混合气体是CHF3/O2。
20.如权利要求18所述的方法，还包括以下步骤：
在去除该转化层前在该焊盘电极上形成再分布金属互连；
其中，该氧混合气体是CF4/O2。
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5170915B2 (ja) * 2005-02-25 2013-03-27 株式会社テラミクロス 半導体装置の製造方法
US7553732B1 (en) * 2005-06-13 2009-06-30 Advanced Micro Devices, Inc. Integration scheme for constrained SEG growth on poly during raised S/D processing
US7572705B1 (en) 2005-09-21 2009-08-11 Advanced Micro Devices, Inc. Semiconductor device and method of manufacturing a semiconductor device
US20070085224A1 (en) * 2005-09-22 2007-04-19 Casio Computer Co., Ltd. Semiconductor device having strong adhesion between wiring and protective film, and manufacturing method therefor
US7323780B2 (en) * 2005-11-10 2008-01-29 International Business Machines Corporation Electrical interconnection structure formation
JP2007220959A (ja) * 2006-02-17 2007-08-30 Fujitsu Ltd 半導体装置及びその製造方法
US20070238283A1 (en) * 2006-04-05 2007-10-11 Taiwan Semiconductor Manufacturing Co., Ltd. Novel under-bump metallization for bond pad soldering
US8446008B2 (en) * 2006-12-25 2013-05-21 Rohm Co., Ltd. Semiconductor device bonding with stress relief connection pads
JP2012114148A (ja) * 2010-11-22 2012-06-14 Fujitsu Semiconductor Ltd 半導体装置の製造方法
CN102420148B (zh) * 2011-06-15 2013-12-04 上海华力微电子有限公司 一种基于聚酰亚胺基体的铝垫制备工艺
TWI490992B (zh) * 2011-12-09 2015-07-01 Chipmos Technologies Inc 半導體結構
US9368437B2 (en) 2011-12-31 2016-06-14 Intel Corporation High density package interconnects
WO2013101241A1 (en) * 2011-12-31 2013-07-04 Intel Corporation Organic thin film passivation of metal interconnections
US9257647B2 (en) * 2013-03-14 2016-02-09 Northrop Grumman Systems Corporation Phase change material switch and method of making the same
JP6698647B2 (ja) * 2015-05-29 2020-05-27 リンテック株式会社 半導体装置の製造方法
US10700270B2 (en) 2016-06-21 2020-06-30 Northrop Grumman Systems Corporation PCM switch and method of making the same
US11546010B2 (en) 2021-02-16 2023-01-03 Northrop Grumman Systems Corporation Hybrid high-speed and high-performance switch system

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4529860A (en) * 1982-08-02 1985-07-16 Motorola, Inc. Plasma etching of organic materials
US4572759A (en) * 1984-12-26 1986-02-25 Benzing Technology, Inc. Troide plasma reactor with magnetic enhancement
JPH0679570B2 (ja) * 1987-08-27 1994-10-12 松下電器産業株式会社 給湯装置
JP2698827B2 (ja) * 1993-11-05 1998-01-19 カシオ計算機株式会社 バンプ電極を備えた半導体装置の製造方法
US6087006A (en) * 1994-08-31 2000-07-11 Hitachi, Ltd. Surface-protecting film and resin-sealed semiconductor device having said film
CN1288592A (zh) * 1998-01-22 2001-03-21 时至准钟表股份有限公司 半导体装置的制造方法
US6277669B1 (en) * 1999-09-15 2001-08-21 Industrial Technology Research Institute Wafer level packaging method and packages formed
US6524963B1 (en) * 1999-10-20 2003-02-25 Chartered Semiconductor Manufacturing Ltd. Method to improve etching of organic-based, low dielectric constant materials
US6555908B1 (en) * 2000-02-10 2003-04-29 Epic Technologies, Inc. Compliant, solderable input/output bump structures
US6458683B1 (en) * 2001-03-30 2002-10-01 Taiwan Semiconductor Manufacturing Co., Ltd Method for forming aluminum bumps by CVD and wet etch
US6630406B2 (en) * 2001-05-14 2003-10-07 Axcelis Technologies Plasma ashing process
US6905968B2 (en) * 2001-12-12 2005-06-14 Applied Materials, Inc. Process for selectively etching dielectric layers
US6974659B2 (en) * 2002-01-16 2005-12-13 Taiwan Semiconductor Manufacturing Co., Ltd. Method of forming a solder ball using a thermally stable resinous protective layer
JP3871609B2 (ja) * 2002-05-27 2007-01-24 松下電器産業株式会社 半導体装置及びその製造方法

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102290379A (zh) * 2010-06-18 2011-12-21 台湾积体电路制造股份有限公司 半导体结构及半导体装置的制造方法
CN104617056B (zh) * 2010-06-18 2019-06-11 台湾积体电路制造股份有限公司 半导体结构
CN102290379B (zh) * 2010-06-18 2015-02-25 台湾积体电路制造股份有限公司 半导体结构及半导体装置的制造方法
CN104617056A (zh) * 2010-06-18 2015-05-13 台湾积体电路制造股份有限公司 半导体结构
CN102479923A (zh) * 2010-11-30 2012-05-30 中芯国际集成电路制造(北京)有限公司 相变存储器的制作方法
CN102479923B (zh) * 2010-11-30 2014-04-02 中芯国际集成电路制造(北京)有限公司 相变存储器的制作方法
CN103137469B (zh) * 2011-11-22 2015-08-19 上海华虹宏力半导体制造有限公司 一种非感光性聚酰亚胺钝化层的制作方法
CN103137469A (zh) * 2011-11-22 2013-06-05 上海华虹Nec电子有限公司 一种非感光性聚酰亚胺钝化层的制作方法
CN106211763A (zh) * 2014-03-25 2016-12-07 住友金属矿山株式会社 包覆焊料材料及其制造方法
CN106211763B (zh) * 2014-03-25 2019-08-27 住友金属矿山株式会社 包覆焊料材料及其制造方法
CN105826183A (zh) * 2015-01-06 2016-08-03 中芯国际集成电路制造(上海)有限公司 减少焊盘结构结晶缺陷的方法
CN105826183B (zh) * 2015-01-06 2019-10-25 中芯国际集成电路制造(上海)有限公司 减少焊盘结构结晶缺陷的方法
CN108962869A (zh) * 2017-05-23 2018-12-07 矽品精密工业股份有限公司 基板结构及其制法
CN108962869B (zh) * 2017-05-23 2022-07-05 矽品精密工业股份有限公司 基板结构及其制法

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