CN1667801A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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CN1667801A
CN1667801A CNA2004100974363A CN200410097436A CN1667801A CN 1667801 A CN1667801 A CN 1667801A CN A2004100974363 A CNA2004100974363 A CN A2004100974363A CN 200410097436 A CN200410097436 A CN 200410097436A CN 1667801 A CN1667801 A CN 1667801A
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sealant
type surface
forms
semiconductor chip
dielectric film
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CN1667801B (zh
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长崎健二
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Lapis Semiconductor Co Ltd
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Oki Electric Industry Co Ltd
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Abstract

本发明涉及一种半导体装置及其制造方法。在具有电路元件的晶圆状的半导体芯片(12’)的主表面(12a)上，形成面对电路元件的钝化膜(20’)，使得主表面中沿该主表面的端边的第一区域(30)露出。然后，形成绝缘膜22，使之沿该钝化膜的主表面(20a)和侧面(20b)延伸到半导体芯片的主表面上，并使第一区域中沿主表面的端边的第二区域(35)保留。而且，在第二区域上形成在形成的同时将绝缘膜覆盖的密封层。从而，能够抑制对封装件内部的水分侵入，还能通过按照设计值镀覆而形成的再布线层等使电气特性的可靠性得到改善。

Description

半导体装置及其制造方法
技术领域
本发明涉及具有封装结构的半导体装置及其制造方法。
背景技术
近年来，对安装于便携式设备等的电子设备的半导体装置的外形尺寸(或称为封装尺寸)的小型化和薄型化提出了越来越高的要求。伴随这种情况，以与半导体芯片外形尺寸大致相同的外形尺寸封装的半导体装置即CSP(Chip Size Package：芯片尺寸封装件)引起了人们的关注。
现在，CSP中，以晶圆状态完成外部端子形成工序后单片化地得到的WCSP(WaferLevel Chip Size Package：晶圆级芯片封装件)，以其能够降低制造成本而引人注目。
WCSP中，切割等产生的切断面原样地成为各封装件的侧面。因此，WCSP中，在衬底上的钝化膜上的绝缘膜(例如聚酰亚胺膜)也在侧面露出。然而，由于上述绝缘膜具有吸水性，水分通过绝缘膜侵入到封装件的内部，造成布线层等的导电性部件被腐蚀的问题。
因而，近年来提出了各种结构，用以抑制从这种具有吸水性的绝缘膜对封装件内部的水分侵入，并抑制封装件可靠性的降低。
作为这种结构，例如，提出了将晶圆上依次形成的钝化膜和聚酰亚胺膜等的绝缘膜的侧面在从封装件的侧面即切断面往里的内侧形成的结构(例如，参照专利文献1：特开2003-124392号公报)。
然而，基于构成半导体芯片的电路元件的形态等原因，覆盖该半导体芯片的钝化膜的表面有时会形成大的台阶差。
另外，如上述文献1的结构那样，将钝化膜的侧面在封装件的切断面往里的内侧形成时，钝化膜成为逆台面型形状，即倒的梯形形状。
可是，WCSP的制造工序中，一般地说，再布线层等的导电性材料层用镀覆方法(电解镀覆法或非电解镀覆法)形成。电镀电极，采用将依次形成钝化膜和聚酰亚胺膜的衬底上全面镀覆的UBM(UnderBarrier Metal：下阻挡层金属)层。这样，将UBM层作为电镀电极使用，能够在该UBM层上镀覆形成再布线层，并进而在再布线层上镀覆形成连接柱部。再有，UBM层除了作为电镀电极的功能以外，还能起到改善绝缘层和再布线层之间的接合性的功能以及防止扩散的功能。
另外，迄今为止的聚酰亚胺膜等的绝缘膜是只在钝化膜的主表面上形成的结构。因此，特别是在钝化膜为逆台面形状且将绝缘膜设置成使形成钝化膜的锐角的边缘部露出的场合，难以在该边缘部的表面以均匀的膜厚溅射镀覆UBM层。
用如此形成的不良UBM层作为电镀电极，会导致再布线层的膜厚不均或不能镀覆形成等问题的发生，并使完成的封装件的可靠性的降低。
发明内容
因而，本发明的主要目的是提供能够抑制水分侵入到封装件内部，并通过符合设计值地镀覆形成的再布线层等而具有高可靠性的电气特性的半导体装置及其制造方法。
为实现该目的，本发明的半导体装置的制造方法具有如下所述的结构上的特征。
也就是说，本发明的半导体装置的制造方法中，包含钝化膜形成工序、绝缘膜形成工序和密封层形成工序。
钝化膜形成工序中，在设有电路元件的半导体芯片的主表面上形成面向电路元件的钝化膜，使沿半导体芯片的主表面中该主表面端边的第一区域露出。绝缘膜形成工序中形成绝缘膜，使其沿钝化膜的主表面和侧面向半导体芯片的主表面上延伸，并使沿第一区域中主表面的端边的第二区域保留。在密封层形成工序中，形成在第二区域上形成的同时将绝缘膜覆盖的密封层。
依据这样的半导体装置的制造方法，能够使由衬底上的钝化膜形成的台阶差(高低差)通过覆盖钝化膜的绝缘膜得到缓和。而且，通过任意适当地设定绝缘膜的成膜条件，能够将与绝缘膜中钝化膜的边缘部对应的部分的形状设成没有角部的形状或钝角的形状。
结果，在后工序中，能够在绝缘膜上厚度均匀地成膜。
而且，依据这样的半导体装置的制造方法，能够通过密封层得到具有不使绝缘膜的侧面在外部露出的结构的半导体装置。因而，所得到的半导体装置，能够抑制从绝缘膜向封装件内部的水分侵入，形成封装件的耐湿性得到改善的结构。
因而，依据本发明的半导体装置及其制造方法，能够得到具有良好成膜准确性和耐湿性的、比传统装置的可靠性高的半导体装置。
附图说明
图1的(A)是表示本发明实施例的半导体装置的概略平面图，(B)是表示本发明实施例的半导体装置的概略剖面图。
图2的(A)～(D)是本发明实施例的半导体装置的制造工序图之一。
图3的(A)～(C)是本发明实施例的半导体装置的制造工序图之二。
图4的(A)和(B)是本发明实施例的半导体装置的制造工序图之三。
【符号说明】
10：半导体装置(WCSP)
12：半导体芯片
12’：切割前的半导体芯片
12a：半导体芯片的主表面
12b：半导体芯片的上表面的端边
14：电极垫
14a：电极垫的顶面
16：连接柱部
16a：连接柱部的顶面
18：布线层(再布线层)
20：钝化膜
20’：钝化膜(形成图案前)
20a：钝化膜的主表面
20b：钝化膜的侧面
22：绝缘膜
22’：绝缘膜(形成图案前)
22b：绝缘膜的侧面
30：第一区域
32：导电层(UBM层)
32’：导电层(UBM层)(形成图案前)
34：焊球
35：第二区域
40：密封层
40b：密封层的侧面
50：半导体晶圆
50a：半导体晶圆的主表面
52、54、58、60：掩模图案
121：芯片基体
140、141：开口
142：开口的内壁面
具体实施方式
以下，说明本发明的实施方式。再有，各图仅在能够理解本发明的程度上概略地表示各构成部分的形状、大小和配置关系，因此，本发明不受图中示例的限定。另外，为了容易使图示清晰，表示剖面斜线除一部分之外均作了省略。再有，以下说明的，仅仅是适用例而已，另外，例示的数值条件也并不构成任何限定。另外，各图中相同的构成部分均加注同一符号，并省略重复的说明。
参照图1至图4，就本发明实施例的半导体装置及其制造方法进行说明。图1(A)是概略表示该实施例的半导体装置10的平面图。再有，图1(A)中，只是详细表示用粗虚线P包围的区域的各构成要素，P区域以外的构成要素的图示省略。另外，为了方便起见，省略了连接柱部上的外部端子和密封层等的图示。图1(B)是概略表示图1(A)的半导体装置10中的各构成要素的连接和配置状况的剖面图，表示沿图1(A)的IB-IB虚线切断得到的切口。另外，图2至图4是表示用以说明本实施例的半导体装置的制造方法的剖面切口的示图。本实施例就WCSP结构的半导体装置及其制造方法进行说明。
如图1(A)所示，半导体装置10具有的半导体芯片12(参照图1(B))的主表面12a上，沿半导体芯片12的外周以预定间隔配置有电极垫14。电极垫14是与在半导体芯片12的表面区域形成的电路元件(未作图示)电气连接的电极面，例如由铝(Al)形成。由于这里的半导体芯片12的平面形状为四方形，所以将电极垫14沿四方形的各边排列。另外，电极垫14和与之对应的连接柱部16，通过布线层(或者，也称为再布线层)18电气连接。这些连接柱部16和布线层18，例如由铜(Cu)形成。
这里的钝化膜20不覆盖半导体芯片12的主表面12a中沿该主表面12a的端边(或称边线或棱线)12b的第一区域30(离端边12b的距离＝X)，因此其侧面20b不到达主表面的半导体芯片12的端边12b。
另外，在钝化膜20上形成的绝缘膜22，将钝化膜20的整个面覆盖，同时不将半导体芯片12的主表面12a中沿该主表面12a的端边12b的第二区域35(离端边12b的距离＝Y(其中，Y＜X))覆盖，因此，该侧面22b不到达主表面的半导体芯片12的端边12b。钝化膜20是用以保护设于面向电路元件的位置的电路元件的膜，例如由硅氧化膜(SiO2)或硅氮化膜(SiN)构成。另外，绝缘膜22是构成吸收热应力而缓冲的缓冲层的低硬度膜，例如是聚酰亚胺膜。
具体而言，如图1(B)所示，这里的半导体芯片12具有在表面区域形成电路元件(未图示)的芯片基体121和在该芯片基体121上形成的、与电路元件电气连接的布线122。布线122例如由铝材构成。再有，半导体芯片12并不限于在上述的芯片基体121上设布线122的结构，也可按照设计或规格等要求而采用任何适当的布线122不露出于表面的、只由芯片基体121构成的结构等。
在半导体芯片12的主表面12a上，使电极垫14的顶面14a的至少一部分露出，依次设置钝化膜20和绝缘膜22。也就是说，电极垫14的顶面14a，构成由钝化膜20和绝缘膜22形成的开口141的底面。
另外，钝化膜20的侧面20b，在从后述的密封层40的侧面40b往里的内侧(离密封层的侧面40b的距离＝X)形成，形成衬底上的台阶差(或称高低差)。另外，钝化膜20的主表面20a和侧面20b由绝缘膜22覆盖。再有，这里的钝化膜20的形状并不限于逆台面型，即倒梯形的形状，可以为任意合适的形状。
绝缘膜22沿钝化膜20的主表面20a和侧面20b，延伸到半导体芯片12的主表面12a上。而且，绝缘膜22的侧面22b也形成在从密封层40的侧面40b往里的内侧(离密封层的侧面40b的距离＝Y(其中，Y＜X))。
这里的绝缘膜22具有可抑制向半导体装置10内部的水分侵入的形状，同时使钝化膜20造成的台阶差缓和，构成高低差小的新的台阶差。该绝缘膜22的侧面22b以形成于从密封层40的侧面40b往里5μm以上的内侧为宜。从而，能够可靠抑制从外部向绝缘膜22的水分侵入
另外，形成作为UBM(Under Barrier Metal)层的导电层32，沿电极垫14的顶面14a和开口的内壁面142向绝缘膜22上延伸。该导电层32作为后述的电镀电极起作用。该UBM层例如由铜形成。
在UBM层32上形成再布线层18。然后，用于连接导电极垫14和安装基板的外部端子即焊球34，经由该再布线层18和连接柱部16个别地电气连接。通过该再布线层18，能够不依赖于电极垫14的位置地将焊球34配置在从半导体芯片12往上侧偏移的位置上。另外，在第一半导体芯片12的上侧，使连接柱部16的顶面16a露出地形成密封层40。
接着，参照图2至图4就该半导体装置10的制造方法进行说明。
首先，准备半导体晶圆50，其上配置多个将通过切割单片化的半导体芯片12’。再有，图中为了方便只图示了约3个单片化前的半导体芯片12’，这不构成任何限定。另外，在半导体晶圆50中相邻的切割前的半导体芯片12’之间，例如形成100μm左右的网格线区域(未图示)。
钝化膜形成工序中，在半导体晶圆50的主表面50a上例如以5nm的膜厚形成钝化膜即硅氧化膜20’。其后，在该硅氧化膜20’上，形成使电极垫14的顶面14a露出的开口140(图2(A))。
之后，在硅氧化膜20’和电极垫14上形成光刻胶(未图示)。接着，对该光刻胶进行曝光/显影，形成使沿半导体芯片12’的主表面12a的端边(或者边线或棱线)12b的第一区域30上的钝化膜20’露出的掩模图案52(参照图2(A))。
之后，用该掩模图案52作为掩模，将从掩模图案52露出的硅氧化膜20’蚀刻掉。
这样，就能形成使主表面12a中第一区域30露出的钝化膜20。也就是，成为钝化膜20的侧面20b不到达将要单片化的半导体芯片12’的主表面的端边12b的形状。蚀刻结束后，将掩模图案52除去。(图2(B))。这里，考虑掩模图案52的对合偏差等因素，适当的方法是将钝化膜20的侧面20b的位置确定在从半导体芯片12’的端边12b往里40μm的(即X＝40μm)内侧来形成。再有，这里的钝化膜20的形状并不以逆台面型为限定，例如，也可为台面型等的形状。
接着，在绝缘膜形成工序中，在半导体芯片12’的主表面12a、钝化膜20和电极垫14上，例如以5～30nm的范围内的膜厚形成绝缘膜即聚酰亚胺膜22’。这里的聚酰亚胺膜22’，可在半导体芯片的主表面12a，钝化膜20和电极垫14上旋涂上涂敷液即聚酰亚胺后，将聚酰亚胺烘烤而形成(参照图2(C))。
之后，在聚酰亚胺膜22’上形成光刻胶(未图示)。接着，对该光刻胶进行曝光/显影，形成使沿半导体芯片12’的主表面12a的端边12b的第二区域35和电极垫14的顶面14a上的聚酰亚胺膜22’露出的掩模图案54(图2(C))。
然后，用该掩模图案54作为掩模将从掩模图案54露出的聚酰亚胺膜22’蚀刻掉。
这样一来，能够形成使主表面12a中第二区域35和电极垫14的顶面14a露出的绝缘膜22。也就是说，成为绝缘膜22的侧面22b不到达将单片化的半导体芯片12’的主表面的端边12b的形状。同时，通过钝化膜20和绝缘膜22，形成使电极垫14的顶面14a露出的开口141(露出工序)。蚀刻结束后，除去掩模图案54(图2(D))。再有，这里的绝缘膜22，如旋涂法那样，以绝缘膜材料作为涂敷液将钝化膜20埋入而形成，从而钝化膜20的表面能够可靠地形成绝缘膜22，而且能够将绝缘膜22中与钝化膜20的边缘部对应的部分的形状形成为没有角部的形状或钝角的形状。结果，后工序中，能够在绝缘膜22上形成均匀膜厚的膜(详细后述)。这里，考虑掩模图案54的对合偏差等因素，适当的方法是将绝缘膜22的侧面22b的位置确定在从半导体芯片12’的端边12b往里5～20μm的(即Y＝5～20μm)内侧来形成。
接着，导电层形成工序中，在半导体芯片12’的主表面12a中第二区域35、钝化膜22及开口141的内壁面142上例如以5～10nm的范围内的膜厚形成构成UBM层的导电层32’。这里，作为导电层32’。例如，通过溅射形成铜构成的层(图3(A))。
接着，布线层形成工序中，在导电层32’上形成光刻胶(未图示)。接着，对该光刻胶进行曝光、显影，形成使布线层形成预定区域的导电层32’露出的掩模图案58(参照图3(A))。
之后，在从掩模图案58露出的导电层32’上，例如以5～10nm的范围内的膜厚形成铜构成的再布线层18(图3(B))。再布线层18的形成，能够以电解镀覆(或者也称为电镀)法或非电解镀覆法来形成。用电解镀覆法形成再布线层18时，例如，将半导体晶圆50和铂板浸入含有镀覆材料的电解质溶液，以晶圆50作为阴极、铂板作为阳极通入直流电流。通过这种方法，能够在阴极侧的电镀电极32’上镀覆上再布线层18。
这时，导电层32’的基底即聚酰亚胺膜22构成使钝化膜20产生的台阶差缓和的新的台阶差。从而，在这样的聚酰亚胺膜22上形成的导电层32’作为没有厚度不均的、高可靠性的电镀电极而起作用。
结果，能够按照设计值形成再布线层18，并能够抑制迄今存在的成膜不良的发生。
接着，在连接柱部形成工序中，在导电层32’和再布线层18上形成光刻胶(未图示)。接着，对该光刻胶进行曝光/显影，形成使连接柱部形成预定区域的再布线层18露出的掩模图案60(参照图3(B))。
之后，从掩模图案60露出的再布线层18上，镀覆形成铜构成的连接柱部16(图3(C))。这里，与形成再布线层18相同，也能够通过电解镀覆法或非电解镀覆法形成连接柱部16。
此时，导电层32’和再布线层18作为电镀电极起作用，但是如已说明的那样，这些膜层分别具有稳定的电气特性。
结果，能够按照设计值形成连接柱部16，并能够抑制迄今存在的成膜不良的发生。
之后，用再布线层18作为掩模，将从该再布线层18露出的导电层32’蚀刻掉，形成导电层32(图4(A))。
接着，密封层形成工序中，在半导体晶圆50的主表面50a上，当然也在各半导体芯片12’的第二区域35上，以将连接柱部16埋没的程度形成密封层40。这里，用环氧树脂等有机树脂作为密封材料，用自动成型(transfer mold)法形成。
其后，用研磨机研磨密封层40，使作为外部端子搭接面的连接柱部16的顶面16a露出。
之后，在露出的连接柱部16的顶面16a上，回熔(reflow)形成作为外部端子的焊球34。然后，用切割用的高速旋转刀片进行切割，将各半导体装置即WCSP(WaferLevel Chip Size Package)10按各个单片化(参照图1(B))。
这样切割出的WCSP10的侧面即切断面，由半导体芯片12的侧面12c和密封层的侧面40b构成，具有吸水性的聚酰亚胺膜22没有被露出。
从而，能可靠抑制从外部对绝缘膜22的水分侵入，并能够抑制封装件内部的布线层等的腐蚀。
如上所述，依据本实施例，能够通过绝缘膜使衬底上由钝化膜形成的台阶差得到缓和。
结果，能够实现绝缘膜上的导电层膜厚的均匀化，使该导电层作为具有稳定的电气特性的电镀电极起作用。
从而，能够在该绝缘膜上镀覆形成高可靠性的布线层和连接柱部。
而且，依据这样的结构，能够设置通过密封层不使绝缘膜的侧面向外部露出的结构。
从而，能够实现成膜的可靠性和耐湿性优良的、具有比传统装置可靠性高的半导体装置。
本发明不限于上述的实施例的组合。因而，能够在任意适当的阶段组合适当的条件来应用本发明。

Claims (10)

1.一种半导体装置的制造方法，其特征在于包括：
在设有电路元件的半导体芯片的主表面上形成面对所述电路元件的钝化膜，使所述主表面中沿该主表面的端边的第一区域露出的钝化膜形成工序；
沿该钝化膜的主表面和侧面延伸到所述半导体芯片的主表面上，且使所述第一区域中沿所述主表面的端边的第二区域保留来形成绝缘膜的绝缘膜形成工序；以及
在所述第二区域上形成在形成时将所述绝缘膜覆盖的密封层的密封层形成工序。
2.如权利要求1所述的半导体装置的制造方法，其特征在于：
所述绝缘膜形成工序中，用旋涂法形成所述绝缘膜。
3.如权利要求1或2所述的半导体装置的制造方法，其特征在于：
还包括所述密封层形成工序之前的如下工序，
在所述钝化膜和所述绝缘膜上形成开口，使所述半导体芯片的主表面上形成的电极垫的顶面露出的露出工序，
形成沿所述露出的电极垫的顶面和所述开口的内壁面延伸到所述绝缘膜上的导电层的导电层形成工序，以及
以所述导电层作为镀覆用电极，在所述导电层上镀覆而形成布线层的布线层形成工序；
在所述密封层形成工序中，进而用所述密封层将所述导电层和布线层密封。
4.如权利要求3所述的半导体装置的制造方法，其特征在于：
还包括所述密封层形成工序之前的如下工序，
以所述布线层作为镀覆用电极，在所述布线层上镀覆而形成连接柱部的连接柱部形成工序；
在所述密封层形成工序中，在所述连接柱部的侧面上形成所述密封层，形成到所述连接柱部的顶面被露出的高度。
5.如权利要求1至4中任一项所述的半导体装置的制造方法，其特征在于：
在所述密封层形成工序中形成密封层，使得在从垂直于该半导体芯片的主表面的方向观看所述半导体芯片时，所述密封层具有与所述半导体芯片的外形尺寸相同的外形尺寸。
6.如权利要求1至4中任一项所述的半导体装置的制造方法，其特征在于：
在所述绝缘膜形成工序中形成所述绝缘膜的侧面，使该侧面位于从所述密封层的侧面往里5μm以上的内侧。
7.一种半导体装置，其特征在于包括：
设有电路元件的半导体芯片；
在该半导体芯片的主表面上、面对所述电路元件的位置上形成的钝化膜；
沿该钝化膜的主表面和侧面延伸到所述半导体芯片的主表面上，且不覆盖所述主表面中沿该主表面的端边的区域的绝缘膜；以及
在所述区域上形成的同时覆盖所述绝缘膜的密封层。
8.如权利要求7所述的半导体装置，其特征在于：
设有在所述半导体芯片的主表面上形成的电极垫，它形成由所述钝化膜和所述绝缘膜形成的开口的底面，
沿所述电极垫的顶面和所述开口的内壁面延伸到所述绝缘层上的导电层，以及
在该导电层上形成的布线层；
所述密封层进而将所述导电层和布线层密封，并且从垂直于该半导体芯片的主表面的方向观看所述半导体芯片时，所述密封层具有与所述半导体芯片的外形尺寸相同的外形尺寸。
9.如权利要求8所述的半导体装置，其特征在于：
在所述布线层上形成连接柱部；
进而在所述连接柱部的侧面上形成所述密封层，形成到所述连接柱部的顶面被露出的高度。
10.如权利要求7至9中任一项所述的半导体装置，其特征在于：
所述绝缘膜的侧面形成于从所述密封层的侧面往里5μm以上的内侧的位置。
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