CN102176433B - 具有低介电性绝缘膜的半导体器件及其制造方法 - Google Patents

具有低介电性绝缘膜的半导体器件及其制造方法 Download PDF

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CN102176433B
CN102176433B CN201110083231XA CN201110083231A CN102176433B CN 102176433 B CN102176433 B CN 102176433B CN 201110083231X A CN201110083231X A CN 201110083231XA CN 201110083231 A CN201110083231 A CN 201110083231A CN 102176433 B CN102176433 B CN 102176433B
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low
dielectric film
wiring route
semiconductor device
laminar structure
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CN102176433A (zh
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水泽爱子
冈田修
若林猛
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Zhao Tan Jing Co ltd
Aoi Electronics Co Ltd
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Casio Computer Co Ltd
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Abstract

一种半导体器件，包括半导体衬底和设置于半导体衬底上除其外围部分之外的区域中的低介电性膜布线线路层压结构部分。每个层压结构部分具有低介电性膜和多个布线线路的层压结构。在层压结构部分的上侧上设置绝缘膜。在绝缘膜上设置用于电极的连接焊盘部分，其待电连接到层压结构部分的最上层布线线路的连接焊盘部分。在用于电极的连接焊盘部分上设置用于外部连接的凸块电极。在绝缘膜上以及半导体衬底的外围部分上设置密封膜。层压结构部分的侧表面被绝缘膜或密封膜覆盖。

Description

具有低介电性绝缘膜的半导体器件及其制造方法
本申请为分案申请，其原申请是2008年11月19日进入中国国家阶段、国际申请日为2006年12月11日的国际专利申请PCT/JP2006/325131，该原申请的中国国家申请号是200680054650.8，发明名称为“具有低介电性绝缘膜的半导体器件及其制造方法”。
技术领域
本发明涉及一种半导体器件和该器件的制造方法。
背景技术
作为待安装到以便携式电子器件等为代表的小尺寸电子器件上的导体器件，已知的有芯片尺寸封装(CSP)，每个芯片尺寸封装均具有基本等于半导体衬底尺寸的大小。在CSP中，也将在晶片状态下完成封装并通过划片分成个体半导体器件的CSP称为晶片级封装(WLP)。在日本专利申请特开公开文本No.2004-349461中公开了一种WLP的典型结构。在该现有文献所述的半导体器件中，从覆盖形成于半导体衬底上的连接焊盘(其中央部分除外)的绝缘膜上表面上的连接焊盘延伸出布线线路(wiring line)，在形成于延伸的布线线路末端上的连接焊盘部分的上表面上设置柱状电极，并形成密封膜以覆盖绝缘膜上表面上的柱状电极之间的布线线路。形成密封膜，使得密封膜的上表面和柱状电极的上表面位于一个平面上。在柱状电极的上表面上设置焊球。
在如上所述的这样的半导体器件当中，有一种这样的器件，在半导体衬底和绝缘膜之间设置层间绝缘膜布线线路层压结构部分，每个所述部分均包括层间绝缘膜和布线线路的层压结构。在这种器件中，当层间绝缘膜布线线路层压结构部分的布线线路之间的间隔随着半导体器件的小型化减小时，布线线路之间的电容增大，结果，通过布线线路传输的信号延迟增加。
为了改善这一点，作为层间绝缘膜的材料，对低介电性膜投入了很多关注，例如介电常数低于一般用作层间绝缘膜材料的二氧化硅的介电常数4.2到4.0的低k材料。低k材料的范例包括用碳(C)对二氧化硅(SiO2)掺杂而获得的SiOC以及进一步含有H的SiOCH。为了进一步降低介电常数，还在研究含有空气的多孔型低介电性膜。
然而，在以上包括低介电性膜的半导体器件中，尤其是由具有空心结构的多孔型低介电性膜代表的低介电性膜机械强度小且容易受湿气影响。结果，就存在低介电性膜容易从底层剥落的问题。
发明内容
本发明的目的是提供一种能够显著改善低介电性膜剥落问题的半导体器件以及该半导体器件的制造方法。
根据本发明一个方面的半导体器件包括：
半导体衬底；
设置于所述半导体衬底上除其外围部分之外的区域中的多个低介电性膜布线线路层压结构部分，每个所述低介电性膜布线线路层压结构部分由低介电性膜和包括具有连接焊盘部分的最上层布线线路的多个布线线路的层压结构构成；
设置于每个所述低介电性膜布线线路层压结构部分的上侧上的绝缘膜；
多个用于电极的连接焊盘部分，设置于所述绝缘膜上，以电连接到所述低介电性膜布线线路层压结构部分的所述最上层布线线路的所述连接焊盘部分；
设置于用于电极的所述连接焊盘部分上的用于外部连接的多个凸块电极；以及
设置于所述绝缘膜上以及所述半导体衬底的所述外围部分上的密封膜，
其中每个所述低介电性膜布线线路层压结构部分的侧表面被所述绝缘膜和所述密封膜之一覆盖。
此外，根据本发明另一方面的半导体器件制造方法包括：
制备半导体晶片，所述半导体晶片在其一个表面上具有低介电性膜布线线路层压结构部分的第一层和形成于所述低介电性膜布线线路层压结构部分上的绝缘膜，所述低介电性膜布线线路层压结构部分均通过层压低介电性膜和包括最上层布线线路的多个布线线路的第二层构成；
去除划片道区域和所述划片道的相对侧上的区域中的所述第一和第二层的部分以形成槽，所述槽将低介电性膜布线线路层压结构部分和所述绝缘膜彼此分开并暴露出所述低介电性膜布线线路层压结构部分的侧表面和所述绝缘膜的侧表面；
在所述绝缘膜上形成待连接到所述最上层布线线路的连接焊盘部分；
在所述连接焊盘部分上形成用于外部连接的凸块电极；以及
形成密封膜，所述密封膜覆盖用于外部连接的所述凸块电极之间的所述绝缘膜的上表面、所述低介电性膜布线线路层压结构部分的侧表面以及所述绝缘膜的侧表面。
根据本发明，为半导体衬底上除其外围部分之外的区域设置包括低介电性膜和布线线路的层压结构的低介电性膜布线线路层压结构部分，并且该低介电性膜布线线路层压结构部分的侧表面被密封膜(或绝缘膜)覆盖。因此，可以防止低介电性膜的剥落。
将在随后的说明书中阐述本发明的其他目的和优点，可以从说明书部分地明了这些目的和优点，或者可以通过实践本发明而了解。可以利用下文中特别指出的手段和组合来实现和获得本发明的目的和优点。
附图说明
附图被并入本说明书并构成其一部分，附图示出了本发明的实施例并与以上给出的一般性描述和以下给出的实施例详细描述一起解释本发明的原理。
图1是本发明第一实施例的半导体器件的截面图；
图2是制造图1所示半导体器件期间首先制备的组件的截面图；
图3是图2之后的步骤中的组件的截面图；
图4是图3之后的步骤中的组件的截面图；
图5是图4之后的步骤中的组件的截面图；
图6是图5之后的步骤中的组件的截面图；
图7是图6之后的步骤中的组件的截面图；
图8是图7之后的步骤中的组件的截面图；
图9是图8之后的步骤中的组件的截面图；
图10是图9之后的步骤中的组件的截面图；
图11是图10之后的步骤中的组件的截面图；
图12是本发明第二实施例的半导体器件的截面图；
图13是制造图12所示半导体器件期间的预定步骤中的组件的截面图；
图14是图13之后的步骤中的组件的截面图；
图15是图14之后的步骤中的组件的截面图；
图16是本发明第三实施例的半导体器件的截面图；以及
图17是根据本发明第四实施例的半导体器件的截面图。
具体实施方式
(第一实施例)
图1示出了本发明第一实施例的半导体器件的截面图。该半导体器件包括硅衬底(半导体衬底)1。在硅衬底1的上表面上，设置具有预定功能的集成电路，并且在上表面的外围部分中，多个或大量由铝基金属等制成的连接焊盘2电连接到集成电路，但图中仅示出了两个焊盘。
在硅衬底1和连接焊盘2的上表面上，设置低介电性膜/布线线路/层压结构部分3。层压结构部分3具有如下的结构：其中交替层压多个层，例如四层低介电性膜4和同样层数的由铝基金属等制成的布线线路5。低介电性膜4的材料范例包括氟化乙烯、氟化聚酰亚胺(polyimide fluoride)、聚烯烃、添加有填料的聚酰亚胺树脂、苯并环丁烯(BCB)和基于有机聚合物的低k材料。可以使用相对介电常数为1.5到3.9的材料，尤其是可以优选使用相对介电常数为2.5到3.9的材料。
在相邻层之间，对应于连接焊盘的布线线路5彼此电连接。最下层的布线线路5的一个端部经由最下层低介电性膜4中设置的开口6电连接到连接焊盘2。最上层的布线线路5的连接焊盘部分5a分别设置于最上层低介电性膜4的上表面外围部分上。
在最上层布线线路5和最上层低介电性膜4的上表面上设置由诸如二氧化硅或低介电性材料的无机材料制成的钝化膜7。在对应于最上层布线线路5的连接焊盘部分5a的部分中穿过钝化膜7形成开口8。在钝化膜7的上表面上设置由有机材料制成的保护膜9，该有机材料包含的主要成分为聚酰亚胺、环氧树脂、苯酚、双马来酰亚胺、丙烯、合成橡胶、聚苄氧化物(polybenzoxide)等。在对应于钝化膜7的开口8的部分中穿过保护膜9形成开口10。
在保护膜9的上表面上设置由铜等制成的金属衬层11。在每个金属衬层11的整个上表面上设置由铜制成的上层布线线路12。金属衬层11的端部经由钝化膜7和保护膜9的开口8、10电连接到最上层布线线路5的连接焊盘部分5a。在上层布线线路12的连接焊盘部分的上表面上，设置由铜制成的用于外部连接的凸块电极或柱状电极13。
在上层布线线路12和保护膜9的上表面以及硅衬底1的外围部分的上表面上，设置由诸如基于环氧树脂的树脂的有机材料制成的密封膜或密封层14，使得密封膜的上表面和柱状电极13的上表面位于一个平面上。在这种状态下，低介电性膜布线线路层压结构部分3、钝化膜7和保护膜9的侧表面完全被硅衬底1上表面上的密封膜14的一部分覆盖。在柱状电极13的上表面上设置焊球15。
如上所述，在该半导体器件中，硅衬底1上除外围部分的区域设置有均包括低介电性膜4和布线线路5的层压结构的低介电性膜布线线路层压结构部分3，且低介电性膜布线线路层压结构部分3、钝化膜7和保护膜9的侧表面被密封膜14覆盖。因此，低介电性膜布线线路层压结构部分3不容易从硅衬底1剥落。
接下来，将描述具有上述构造的半导体器件的制造方法的一个范例。首先，如图2所示，制备一个组件，其中，在具有晶片状态的硅衬底(以下简称半导体晶片21)上，设置连接焊盘2和低介电性膜布线线路层压结构部分3，每个低介电性膜布线线路层压结构部分3均分别包括四层低介电性膜4和布线线路5。在该组件中，在层压结构部分3上设置钝化膜7，经由钝化膜7中设置的开口8暴露最上层布线线路5的连接焊盘部分5a的中央。低介电性膜的材料范例包括氟化乙烯、氟化聚酰亚胺、聚烯烃、添加有填料的聚酰亚胺树脂、苯并环丁烯(BCB)和基于有机聚合物的低k材料。可以使用相对介电常数为1.5到3.9的材料，尤其是可以优选使用相对介电常数为2.5到3.9的材料。要指出的是，图2中用附图标记22表示的区域是对应于划片道(dicing street)的区域。
接下来，如图3所示，利用丝网印刷工艺、旋涂工艺等，在钝化膜7的上表面和经由钝化膜7的开口8暴露的最上层布线线路5的连接焊盘部分5a的上表面上形成由诸如聚酰亚胺基树脂的有机材料制成的保护膜9。
接下来，如图4所示，利用发射激光束的激光处理除去保护膜9、钝化膜7和四层低介电性膜4位于划片道22的区域中以及划片道相对侧区域中的部分，以形成格状槽23。于是，硅衬底1的上表面通过槽以格状(lattice)形式暴露出来。在钝化膜7位于连接焊盘部分5a上的部分中制造开口8，并在保护膜9位于这些开口上的部分中制造开口10。低介电性膜4是脆性的。因此，如果利用刀片在膜4中切割槽23，那么低介电性膜4的切割面将具有很多凹痕和裂痕。有鉴于此，建议对切割面施加激光束以制作槽23。在用激光束照射时，硅衬底1的上表面熔化，熔化的硅颗粒跃起并随后落到硅衬底1上。如图4所示，每个槽23将不可避免地具有不平坦的底表面。当槽23达到在大多数情况下形成于硅衬底1上的场效氧化膜(未示出)时，可以终止施加激光束。
在这种状态下，如上所述经由槽23暴露出半导体晶片21位于划片道22的区域中以及划片道相对侧上区域中的上表面。此外，通过槽23将层压在半导体晶片21上的四层低介电性膜4、钝化膜7和保护膜9的部分彼此分开。结果，在晶片21上形成了彼此独立的多个低介电性膜布线线路层压结构部分3。
作为一个范例，槽23的宽度为10到1000μm×2加上划片道(划片切割机)22的宽度。结果，在图1所示的完成的器件中，覆盖低介电性膜布线线路层压结构部分3、钝化膜7和保护膜9的侧表面的密封膜14的部分的宽度为10到1000μm。
接下来，如图5所示，在最上层布线线路5经钝化膜7和保护膜9的开口8、10暴露的连接焊盘部分5a的上表面上、在半导体晶片21经槽23暴露的上表面部分上以及在保护膜9的整个上表面上形成金属衬层11。在这种情况下，金属衬层11可以仅由通过无电镀形成的铜层形成、仅由通过溅射形成的铜层形成或由在通过溅射形成的钛等的薄膜层上通过溅射形成的铜层来形成。
接下来，在金属衬层11的上表面上形成抗电镀膜24，随后进行构图。结果，在抗电镀膜24对应于形成上层布线线路12的区域的部分中形成开口25。接下来，利用金属衬层11作为电镀电流路径完成铜的电解电镀，由此在抗电镀膜24的开口25中的金属衬层11的上表面上形成上层布线线路12。接下来，剥离抗电镀膜24。
接下来，如图6所示，在金属衬层11和上层布线线路12的上表面上通过沉积并随后构图来形成抗电镀膜26。于是，在这种情况下，在对应于上层布线线路12的连接焊盘部分的部分中(形成柱状电极13的区域)、在抗电镀膜26中形成开口27。接下来，利用金属衬层11作为电镀电流路径完成铜的电解电镀，由此在抗电镀膜26的开口27中、在上层布线线路12的连接焊盘部分的上表面上形成柱状电极13，每个柱状电极都具有50到150μm的高度。接下来，将抗电镀膜26全部剥离或去除。然后，利用上层布线线路12作为掩模蚀刻并去除金属衬层11的不必要部分。结果，如图7所示，仅留下上层布线线路12下方的金属衬层11。
接下来，如图8所示，通过丝网印刷工艺、旋涂工艺等，在上层布线线路12、柱状电极13和保护膜9的上表面上以及在经槽23暴露的半导体晶片21的上表面上完整地形成由诸如基于环氧树脂的树脂的有机材料制成的密封膜14，使得密封膜14的厚度大于柱状电极13的高度。因此，在这种状态下，柱状电极13的上表面被密封膜14的上部覆盖。保护膜9、钝化膜7和四层低介电性膜4的侧表面也完全被密封膜14覆盖。
接下来，适当研磨密封膜14的上表面的一部分以如图9所示暴露柱状电极13的上表面。此外，使柱状电极13的暴露上表面和密封膜14的上表面平坦化，使得这些上表面位于一个平面上。在对密封膜14的该上表面进行平坦化时，可以与密封膜14的上部一起将柱状电极13的上表面部分研磨几个到十个或更多微米。接下来，如图10所示，在柱状电极13的上表面上形成焊球15。接下来，如图11所示，沿着槽23中央的划片道22切割密封膜14和半导体晶片21。如上所述，由于槽23形成得比划片道22宽，因此获得了多个均具有如图1所示结构的半导体器件，其中，低介电性膜布线线路层压结构部分3的侧表面被密封膜14覆盖，且此外钝化膜7的侧表面和保护膜9的上表面与侧表面也被密封膜14覆盖。
在以上实施例中，半导体晶片21的上表面的暴露部分被示为类似槽23的底部，但可以用激光束部分地去除半导体晶片21的上表面以形成槽23，使得槽23的底部可以低于半导体晶片21的上表面。如果在半导体晶片21的上表面上形成诸如场效氧化膜的绝缘膜，那么该场效氧化膜的上表面或其膜厚度的中间部分可以是槽23的底部，且槽23的底部可以位于半导体晶片21的上表面上方。
(第二实施例)
图12示出了本发明第二实施例的半导体器件的截面图。该半导体器件与图1所示的半导体器件不同之处在于，钝化膜7的上表面和侧表面与低介电性膜布线线路层压结构部分3的侧表面被保护膜9覆盖，而保护膜9的侧表面被密封膜14覆盖。
作为制造该半导体器件的一个范例，制备图3所示的组件，然后如图13所示，利用发射激光束的激光处理，在划片道22的区域和划片道相对侧的区域中在钝化膜7和四层低介电性膜4中形成槽23。
在这种状态下，经槽23暴露划片道22中的半导体晶片21的上表面以及划片道相对侧上的区域。此外，沿着槽23将层压在半导体晶片21上且均由四层低介电性膜4和钝化膜7构成的单元彼此分开。结果，在半导体晶片21上形成了图13所示的多个低介电性膜布线线路层压结构部分3。
接下来，如图14所示，利用丝网印刷工艺、旋涂工艺等，在最上层布线线路5的连接焊盘部分5a经由钝化膜7的开口8暴露的上表面上、在钝化膜7的上表面上以及在半导体晶片21经由槽23暴露的部分的上表面上形成由诸如基于聚酰亚胺的树脂的有机材料制成的保护膜9。
接下来，如图15所示，通过发射激光束的激光处理或利用划片刀片的切割处理，在划片道22的区域中以及划片道相对侧上的区域中的保护膜9中形成稍窄于前述槽23的槽23a，并在保护膜9对应于钝化膜7的开口8的部分中形成开口10。由于后续的步骤类似于第一实施例的图5等图中的步骤，因此省略其描述。
(第三实施例)
图16示出了本发明第三实施例的半导体器件的截面图。第三实施例与第二实施例的不同之处在于，覆盖钝化膜7的上表面和侧表面以及低介电性膜4的侧表面的保护膜9延伸到与硅衬底1的侧表面相同的平面。为了获得这种结构，可以利用保护膜9完全填满第二实施例的图15所示的凹陷部分或槽23。
以上实施例均具有如下的结构：在保护膜9上形成金属衬层11，在该金属衬层上分别形成上层布线线路12，并在上层布线线路12的连接焊盘部分上形成柱状电极13。然而，本发明也可以应用于如下的结构：在保护膜9上直接形成连接到最上层布线线路5的连接焊盘部分5a的连接焊盘部分，并在连接焊盘部分上形成用于外部连接的诸如焊球15的凸块电极。
(第四实施例)
图17是根据本发明第四实施例的半导体器件的截面图。第四实施例在结构上类似于第一实施例。因此，将仅描述与第一实施例不同的特征，将不再描述与第一实施例共有的特征。第四实施例与第一实施例的不同之处在于，钝化膜7和保护膜9小于形成膜7和8二者的低介电性膜布线线路层压结构部分3。亦即，钝化膜7比层压结构部分3小且设置于部分3上，保护膜9比层压结构部分3小且设置于整个钝化膜7上以及部分3的外围边缘上。可以通过以下方法制造这种半导体器件。首先，如图2所示在部分3的整个表面上形成钝化膜7。利用光刻对钝化膜7进行构图。接下来，在钝化膜7上以及低介电性膜4上，即在低介电性膜布线线路层压结构部分3的最上层上形成保护膜9。然后，利用光刻技术对保护膜9进行构图。之后，向部分3施加激光束，制造槽23。在根据第四实施例的该方法中，用激光束仅处理低介电性膜布线线路层压结构部分3。钝化膜7或保护膜9都未被处理。因此可以为处理部分3，尤其是低介电性膜4设置最佳的激光束工艺条件。因此，可以以高精度处理低介电性膜4。
在上述实施例中，四个低介电性层4和四个布线线路5构成每个低介电性膜布线线路层压结构部分3。低介电性层的数量和布线线路的数量不限于四个。从上文可以认识到，该部分具有多个低介电性层和多个布线线路就足够了。
本领域的技术人员将容易想到更多的优点和改进。因此，在其更宽的方面上，本发明不限于这里所示和所述的特定细节和代表性实施例。因此，在不脱离如所附权利要求及其等价物所定义的总体发明构思的精神或范围的情况下可以作出各种修改。

Claims (11)

1.一种半导体器件，包括：
半导体衬底；
低介电性膜布线线路层压结构部分，该低介电性膜布线线路层压结构部分设置于所述半导体衬底的上表面上除其外围部分之外的区域中，并且该低介电性膜布线线路层压结构部分包括多个低介电性膜和多个布线线路的层压结构，所述多个布线线路包括具有多个连接焊盘部分的多个最上层布线线路；
设置于除所述低介电性膜布线线路层压结构部分的外围区域之外的所述低介电性膜布线线路层压结构部分的上表面上的绝缘层；
多个用于电极的连接焊盘部分，设置于所述绝缘层的上表面上，以电连接到所述低介电性膜布线线路层压结构部分的所述最上层布线线路的所述连接焊盘部分；
设置于用于电极的所述连接焊盘部分的上表面上的、用于外部连接的多个凸块电极；以及
设置于所述绝缘层的上表面和侧表面、所述低介电性膜布线线路层压结构部分的侧表面和外围区域、所述半导体衬底的所述外围部分以及所述凸块电极的侧表面上的密封膜。
2.根据权利要求1所述的半导体器件，其中所述绝缘层由钝化膜和保护膜构成，所述钝化膜设置在所述低介电性膜布线线路层压结构部分的上表面上，所述保护膜设置在所述钝化膜的上表面上。
3.根据权利要求2所述的半导体器件，其中所述钝化膜由无机材料制成。
4.根据权利要求2所述的半导体器件，其中所述钝化膜包括二氧化硅膜或低介电性膜。
5.根据权利要求2所述的半导体器件，其中所述保护膜由有机材料制成。
6.根据权利要求1所述的半导体器件，其中具有用于电极的所述连接焊盘部分的多个上层布线线路形成在所述绝缘层的上表面上。
7.根据权利要求1所述的半导体器件，其中用于外部连接的所述凸块电极是柱状的。
8.根据权利要求1到7中的任一项所述的半导体器件，其中在用于外部连接的所述凸块电极的上表面上设置多个焊球。
9.根据权利要求1到7中的任一项所述的半导体器件，其中所述低介电性膜含有氟化乙烯、氟化聚酰亚胺、聚烯烃、添加有填料的聚酰亚胺树脂、苯并环丁烯(BCB)和基于有机聚合物的低k材料中的至少一种。
10.根据权利要求1到7中的任一项所述的半导体器件，其中所述低介电性膜具有1.5到3.9的相对介电常数。
11.根据权利要求1到7中的任一项所述的半导体器件，其中所述低介电性膜具有2.5到3.9的相对介电常数。
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