TWI490992B - 半導體結構 - Google Patents

半導體結構 Download PDF

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Publication number
TWI490992B
TWI490992B TW100145468A TW100145468A TWI490992B TW I490992 B TWI490992 B TW I490992B TW 100145468 A TW100145468 A TW 100145468A TW 100145468 A TW100145468 A TW 100145468A TW I490992 B TWI490992 B TW I490992B
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Taiwan
Prior art keywords
semiconductor structure
bumps
bump
substrate
pads
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TW100145468A
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English (en)
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TW201324716A (zh
Inventor
Geng Shin Shen
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Chipmos Technologies Inc
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Application filed by Chipmos Technologies Inc filed Critical Chipmos Technologies Inc
Priority to TW100145468A priority Critical patent/TWI490992B/zh
Priority to CN2012100876384A priority patent/CN103165550A/zh
Priority to US13/671,202 priority patent/US8786082B2/en
Publication of TW201324716A publication Critical patent/TW201324716A/zh
Application granted granted Critical
Publication of TWI490992B publication Critical patent/TWI490992B/zh

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    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
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  • Engineering & Computer Science (AREA)
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

半導體結構
本發明為一半導體結構，特別是指一種使凸塊間距小於凸塊寬度的一半導體結構。
隨著半導體封裝技術發展，以往採用打線作為電性連接的方式，現已逐漸由凸塊取代，藉由透過電鍍、銲膏轉印、蒸鍍與銲球直接黏著等技術設置於晶片上的凸塊，達成晶片與基板電路之電性連接。在各式的凸塊相關封裝技術中，基於成本及封裝尺寸之考量，近年更以覆晶封裝(Flip Chip in Package，FCiP)為其主流。
簡言之，覆晶技術係將晶片倒置，使晶片上之凸塊可直接與基材上之電路電性連接。為提高各個封裝上的電路密集度，在晶片的主動面上需儘可能的增加凸塊接點數量，進而需縮小凸塊間距(bump pitch)及凸塊寬度(bump width)。然而，上述凸塊間距及凸塊寬度之減少幅度有限，且較小的凸塊間距亦會使得凸塊寬度縮小，利用探針檢測時，較小的凸塊需搭配較高的操作精度，以增加檢測時間、成本及難度。
詳言之，請參考第1A及1B圖所示習知半導體結構之上視圖及剖面圖。半導體結構1包含一基材10、複數個連接墊12、一保護層14、複數個底層金屬層16及複數個凸塊18，複數個連接墊12依序相鄰設置於基板10上，且該些連接墊12藉由保護層14所定義的複數開口142與底層金屬層16及凸塊18電性相連。由圖可 知，一般在線路設計上，各個凸塊間距W1須大於凸塊寬度W2，藉以避免凸塊接觸短路。換言之，在設計凸塊大小時，凸塊寬度W2便會受到凸塊間距W1的限制。而在現今欲降低整體尺寸的發展趨勢下，降低凸塊間距會使得測試時遭受到一些技術上的瓶頸，諸如探針定位有其精度的限度，寬度不足的凸塊亦會提高封裝的困難和增加凸塊剝落的機率等等。
有鑑於此，提供一種可改善上述缺失，封裝尺寸小、易於檢測凸塊電性又具有高電路密集度的半導體結構，乃為此業界亟待解決的問題。
本發明的一目的為在半導體結構中，提供凸塊寬度不受凸塊間距所囿限，且利於探針進行測試又便於封裝的凸塊。
為達上述目的，本發明提供一半導體結構，其包含一基板、至少二襯墊、一鈍化層、至少二凸塊底層金屬層及至少二凸塊。襯墊係沿一第一方向相鄰設置於基板上，鈍化層覆蓋於基板及各襯墊之一周圍上表面以分別界定一開口，各開口於一第二方向各具有一開口投影，開口投影係各自相鄰設置而不重疊，其中，第一方向與第二方向垂直。凸塊底層金屬層則設置於各個開口上，並分別與該些襯墊電性相連，而凸塊則分別設置於各凸塊底層金屬層上。
為了讓上述的目的、技術特徵和優點能夠更為本領域之人士所知悉並應用，下文係以本發明之數個較佳實施例以及附圖進行詳細的說明。
以下將透過實施方式來解釋本發明內容，本發明係關於一種半導體結構。需說明者，在下述實施例以及附圖中，關於實施方式之說明僅為闡釋本發明之目的，而非用以直接限制本發明，同時，以下實施例及圖式中，與本發明非直接相關之元件均已省略而未繪示；且圖式中各元件間之尺寸關係僅為求容易瞭解，非用以限制實際比例及實際大小。
請先參考第2A至2C圖，本發明之第一實施例係為一半導體結構2，其包含一基板20、數個襯墊22、一鈍化層24、數個凸塊底層金屬層26及數個凸塊28。
如第2A圖所示，在半導體結構2中可定義一第一方向X及一第二方向Y，且第一方向X垂直於第二方向Y。在本實施例中，各襯墊22係為沿第二方向Y成型之長條狀襯墊並順沿第一方向X等距設置於基板20上，但不以此為限。
鈍化層24覆蓋於基板20及各襯墊22之一周圍上表面，以於各襯墊22上分別界定一開口242，各開口242於一第二方向Y上各具有一開口投影(圖未示出)，其中，任二相鄰開口之開口投影係各自相鄰設置而不重疊。凸塊底層金屬層26則設置於各個開口242上，並與該些襯墊22電性相連。且凸塊28則分別設置於各凸塊底層金屬層26上。詳細而言，凸塊28可依所採用之不同材料性質，而藉由印刷、點膠、電鍍等之方式形成於各凸塊底層金屬層26上。基於上述內容及相關圖面，熟知此項技術領域者當可輕易了解，本發明之凸塊可依據不同的設計，形成上視形狀為梯形 或是不規則形狀之凸塊，並在第二方向Y中各自具有一凸塊投影，使得相鄰凸塊之凸塊投影邊緣處亦可局部重疊，並非需如本實施例所述，限制本發明之相鄰凸塊之凸塊投影在第二方向Y上不重疊。
在本實施例中，基板20可為一晶片、一晶圓、一印刷電路板、一陶瓷基板或一薄膜等；凸塊底層金屬層26採用之材料係為鈦、銅、釩、鎢鈦或其合金；凸塊28之材料可為金、銀、銅、鎳、上述合金、導電高分子材料或其他等效金屬；而鈍化層24之材料則可為二氧化矽(SiO2)或氮化矽(SiN)。
須說明的是，上述的「各開口於第二方向Y上各具有一開口投影」，係指任二鈍化層所界定的相鄰兩開口，在第二方向上投影可形成二投影線段，此等投影線段雖相鄰但並不重疊。且前述所稱「相鄰凸塊」與「相鄰開口」中的「相鄰」實質上係指設置於及形成於「相鄰襯墊」上的凸塊及開口。
請再次參考的第2B圖，其係沿第2A圖AA線段的剖面示意圖。從圖中可知悉，各凸塊28可以增加的/設計的寬度較一般習知凸塊寬，至少可以沿著圖面中的第一方向X增加凸塊28的寬度。在某些實施例中，在同樣線距的襯墊上，更可相較於一般習知凸塊，將凸塊表面面積增加約兩倍左右。
接著，請接續參考第2C圖，其係沿第2A圖BB線段的剖面示意圖。從圖中可知本發明之凸塊28之形狀並非必須沿開口242之中心左右寬度對稱，在可容許的情況下，凸塊28可於一側適度地增加其寬度，以增加封裝(如內引腳接合製程)及檢測(Probeing)的 穩定度，亦即如第2C圖所示，凸塊28之一側向外延伸較長。
綜上所述，本發明之第一實施例的配置如第2B圖所示，二相鄰凸塊定義一凸塊間距W1(相鄰凸塊之平行第二方向Y之一側邊的間距)，且凸塊間距W1實質上小於凸塊寬度W2，是故本發明之凸塊較一般習知的凸塊具有較大的電性連接的表面積，易於進行晶片及凸塊間之電性檢測，又可符合縮小封裝體積並提高電路密集度之發展趨勢。
第3A至3C圖為本發明之第二實施例之半導體結構3相關示意圖。與第二實施例相似地，半導體結構3亦包含一基板30、數個襯墊32、一鈍化層34、數個凸塊底層金屬層36及數個凸塊38。
此實施例與第一實施例的主要差異為，鈍化層34為一保護層341和一絕緣層342所構成。本實施例中，保護層341覆蓋基板30並覆蓋各襯墊32之一周圍上表面，以於各襯墊32上分別界定一襯墊開口3412。接著，絕緣層342覆蓋在保護層341上及局部覆蓋於各襯墊開口3412上，以分別界定開口3422。其中，各襯墊開口3412於第二方向Y各具有一襯墊開口投影(圖未示出)，該些襯墊開口投影係相互重疊。於本發明中，絕緣層可選用具有彈性的材料，除了可提供絕緣功能以外，更可吸收凸塊接合時承受的應力，以及避免凸塊發生底切效應。
同樣地，請接續參考第3C圖，其係沿第3A圖BB線段的剖面示意圖。本實施例之凸塊38與習知凸塊相較下，具有較寬闊之表面，且更可沿著圖面中的第一方向X進一步增加寬度，提高檢測便利性。在某些實施例中，在同樣線距的襯墊上，更可相較於一 般習知凸塊，將凸塊表面面積增加約兩倍左右。
由於本實施例之其餘元件配置、元件間的關係及材料採用係與第一實施例相似，故於此便不再次贅述。
如上述第二實施例的配置而言，凸塊間距W1同樣地實質上小於凸塊寬度W2，是故本發明之凸塊較一般習知的凸塊具有較大的電性連接的表面積，易於進行晶片及凸塊間之電性檢測，又可符合縮小封裝體積並提高電路密集度之發展趨勢。
除了前述的兩種實施態樣，半導體結構亦可採用不同的排列方式，藉由不同的開口位置，解決習知凸塊之問題，以達到本發明之目的。請參考第4圖及第5圖，為本發明之第三實施例及第四實施例之相關示意圖。半導體結構4同樣具有基板(圖未標示出)、數個襯墊42、鈍化層44、數個凸塊底層金屬層(圖未示出)及數個凸塊48；而半導體結構5亦同樣具有基板(圖未標示出)、數個襯墊52，鈍化層54，數個凸塊底層金屬層(圖未示出)及凸塊58。於此二實施例中，任二相鄰襯墊42(或襯墊52)上之開口442(或開口542)，於第二方向Y係相鄰設置而不重疊，故此二實施例亦可達到與上述實施例相似的效果及相同的目的。
需說明的是，上述實施例所配合說明之半導體結構局部上視圖，僅係用以例示半導體結構之局部配置設計，故本發明並不限制其餘未顯示的部分需具有相同/對稱的配置。使用者可在不悖於本發明的概念下，將本發明應用在不同的設計之中。綜言之，半導體結構可全部或局部地採用本發明之概念。
綜上所述，本發明藉由將開口錯位設置於襯墊上，使凸塊之寬度不會受凸塊間距所囿限，進而達到使提高探針測試的精準度及提高封裝良率之目的。
上述之實施例僅用來例舉本發明之實施態樣，以及闡釋本發明之技術特徵，並非用來限制本發明之保護範疇。任何熟悉此技術者可輕易完成之改變或均等性之安排均屬於本發明所主張之範圍，本發明之權利保護範圍應以申請專利範圍為準。
1‧‧‧半導體結構
10‧‧‧基材
12‧‧‧連接墊
14‧‧‧保護層
142‧‧‧開口
16‧‧‧底層金屬層
18‧‧‧凸塊
2‧‧‧半導體結構
20‧‧‧基板
22‧‧‧襯墊
24‧‧‧鈍化層
242‧‧‧開口
26‧‧‧凸塊底層金屬層
28‧‧‧凸塊
3‧‧‧半導體結構
30‧‧‧基板
32‧‧‧襯墊
34‧‧‧鈍化層
341‧‧‧保護層
3412‧‧‧襯墊開口
342‧‧‧絕緣層
3422‧‧‧開口
36‧‧‧凸塊底層金屬層
38‧‧‧凸塊
4‧‧‧半導體結構
42‧‧‧襯墊
44‧‧‧鈍化層
442‧‧‧開口
48‧‧‧凸塊
5‧‧‧半導體結構
52‧‧‧襯墊
54‧‧‧鈍化層
542‧‧‧開口
58‧‧‧凸塊
X‧‧‧第一方向
Y‧‧‧第二方向
W1‧‧‧凸塊間距
W2‧‧‧凸塊寬度
第1A圖為習知半導體結構之局部上視示意圖；第1B圖為第1A圖之習知半導體結構剖面示意圖；第2A圖為本發明之第一實施例之半導體結構局部上視示意圖；第2B圖為第2A圖沿AA線段之剖面示意圖；第2C圖為第2A圖沿BB線段之剖面示意圖；第3A圖為本發明之第二實施例之半導體結構局部上視示意圖；第3B圖為第3A圖沿AA線段之剖面示意圖；第3C圖為第3A圖沿BB線段之剖面示意圖；第4圖為本發明之第三實施例之半導體結構局部上視示意圖；以及第5圖為本發明之第四實施例之半導體結構局部上視示意圖。
2‧‧‧半導體結構
20‧‧‧基板
22‧‧‧襯墊
24‧‧‧鈍化層
242‧‧‧開口
28‧‧‧凸塊

Claims (13)

  1. 一種半導體結構，包含：一基板；至少二襯墊，沿一第一方向相鄰設置於該基板上；一鈍化層，覆蓋該基板並覆蓋各該襯墊之一周圍上表面以分別界定至少一開口，各該開口於一第二方向各界定出一開口投影，其中任二相鄰該開口所界定之該開口投影係彼此不重疊，且該第一方向與該第二方向垂直；以及至少二凸塊底層金屬層，分別設置於各該開口上；至少二凸塊，分別設置於各該凸塊底層金屬層上。
  2. 如請求項1所述之半導體結構，該鈍化層具有一保護層，覆蓋該基板並覆蓋各該襯墊之一周圍上表面以分別界定至少一襯墊開口，各該襯墊開口於該第二方向各具有一襯墊開口投影，該些襯墊開口投影係相互重疊。
  3. 如請求項2所述之半導體結構，該鈍化層更具有一絕緣層，覆蓋在該保護層上及局部覆蓋於各該襯墊開口上，以分別界定該至少一開口。
  4. 如請求項1所述之半導體結構，其中該至少二凸塊之材料為金、銀、銅、鎳或其合金。
  5. 如請求項1所述之半導體結構，其中相鄰之各該凸塊於該第二方向之各自具有一凸塊投影，且該些凸塊投影係局部重疊。
  6. 如請求項1所述之半導體結構，其中該至少二凸塊底層金屬層之材料係為鈦、銅、釩、鎢鈦或其合金。
  7. 如請求項1所述之半導體結構，其中該至少二凸塊之材料係 為一導電高分子材料。
  8. 如請求項7所述之半導體結構，其中該至少二凸塊係以印刷或點膠之方式設置於各該凸塊底層金屬層上。
  9. 如請求項1所述之半導體結構，其中該基板係為一晶片、一晶圓、一印刷電路板、一陶瓷基板或一薄膜。
  10. 如請求項1所述之半導體結構，其中該鈍化層之材料為二氧化矽(SiO2)或氮化矽(SiN)。
  11. 如請求項1所述之半導體結構，其中各該襯墊係為沿該第二方向成型之一長條狀。
  12. 如請求項1所述之半導體結構，其中各該凸塊係利用電鍍設置各該凸塊底層金屬層上。
  13. 如請求項1至3任一所述之半導體結構，該至少二凸塊定義一凸塊間距，且該凸塊間距小於各該凸塊之一凸塊寬度。
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