CN102290379B - 半导体结构及半导体装置的制造方法 - Google Patents

半导体结构及半导体装置的制造方法 Download PDF

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Publication number
CN102290379B
CN102290379B CN201010551927.6A CN201010551927A CN102290379B CN 102290379 B CN102290379 B CN 102290379B CN 201010551927 A CN201010551927 A CN 201010551927A CN 102290379 B CN102290379 B CN 102290379B
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plasma process
layer
semiconductor device
plasma
base material
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CN102290379A (zh
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卢祯发
刘重希
余振华
陈威宇
陈正庭
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供具有聚合物层的半导体装置及其制造方法。用于聚合物表面的两步骤等离子体处理包含一第一等离子体工艺用以使聚合物层表面粗糙化并释放出使结构松散一产生的松散结构污染物，及一第二等离子体工艺用以使聚合物层光滑或较不粗糙。可在第一等离子体工艺及第二等离子体工艺之间使用一蚀刻工艺以移除由第一等离子体工艺所释放的污染物。在一实施例中，聚合物层的由原子力显微镜及表面积差异比率系数所量测得到的粗糙度介于约1％及约8％，且/或该聚合物层的钛表面污染物小于1％、氟表面污染物小于约1％、锡表面污染物小于约1.5％、及铅表面污染物小于约0.4％。本发明可避免及/或减少来自例如胶带工艺的污染物。

Description

半导体结构及半导体装置的制造方法
技术领域
本发明涉及半导体装置，且特别涉及一种表面经等离子体处理以减少或避免污染的半导体装置。
背景技术
自集成电路(IC)问世以来，由于各种电子元件(例如晶体管、二极管、电阻、电容等)的集积度持续改良，半导体工业持续快速成长。主要而言，集积度的改良来自持续缩减元件的最小尺寸，使更多元件能被整合至单位面积中。
近年来，已可见到半导体封装的许多变化冲击了整个半导体产业。表面粘着技术(surface-mount technology，SMT)及球栅阵列(ball grid array，BGA)封装通常为高产能封装各种IC元件的重要步骤，同时亦使印刷电路板上接垫节距减小。传统IC封装结构基本上是以纯金细线连接裸片上的金属垫与分布于塑模树脂封装上的电极。另一方面，某些芯片级封装(CSP)及球栅阵列(BGA)封装依靠焊料凸块来提供裸片上的接触点与基材(例如封装基材、印刷电路板、其他裸片/晶片等)上的接触点之间的电性连接。其他芯片级封装(CSP)及球栅阵列(BGA)封装则是将焊球或凸块置于导电柱体上，依靠焊接来达到结构整合。在上述情况下，通常会以聚合物材料来覆盖焊球或凸块周边的基材，以保护基材表面。底部填充材料通常亦设置于IC及其底下的基材之间(例如封装基材)，以提供机械强度并保护IC免于受到环境污染物污染。
在某些装置中，故意形成粗糙的聚合物表面，因而创造出珊瑚状(coral-like)的表面。此粗糙表面相信可使聚合物材料及底部填充材料之间的接合更为紧密，减少聚合物材料及底部填充材料之间的脱层。然而，经发现，此粗糙表面亦包含工艺中额外的污染物。例如，此粗糙表面似乎会使在晶背端薄化工艺中施予胶带所造成的胶带残余物增加。
发明内容
为克服现有技术中的缺陷，本发明提供一种半导体结构，包括：一基材，具有一接触垫形成于其上；一聚合物层位于该基材上，该聚合物层的由原子力显微镜及表面积差异比率(SADP)系数量测得到的表面粗糙度介于约1％至8％之间，且该聚合物层具有一开口暴露至少一部分的该导电垫；以及一凸块下金属结构，延伸贯穿该开口并与该导电垫电性连接。
本发明亦提供另一种半导体结构，包括：一基材，具有一导电垫形成于其上；以及一聚合物层位于该基材上，该聚合物层经图案化以暴露至少一部分的该导电垫，该聚合物层的钛表面污染物小于约1％、氟表面污染物小于约1％、锡表面污染物小于约1.5％、及铅表面污染物小于约0.4％。
本发明更提供一种半导体装置的制造方法，包括：形成一基材；形成一接触垫于该基材上；形成一保护层于该接触垫上，以暴露至少一部分的该接触垫；形成一凸块下金属结构与该接触垫电性连接；形成一导电凸块于该凸块下金属结构上；于该保护层的暴露表面上进行一第一等离子体工艺，该第一等离子体工艺使该保护层的一表面粗糙化；于进行该第一等离子体工艺后，进行一或多次工艺步骤；以及于该保护层的暴露表面上进行一第二等离子体工艺，该第二等离子体工艺减少该保护层的粗糙度。
本发明的工艺可使表面实质上无杂质，及提供较光滑的表面，且更避免及/或减少来自例如胶带工艺的污染物。
为让本发明的上述和其他目的、特征、和优点能更明显易懂，下文特举出优选实施例，并配合附图，作详细说明如下。
附图说明
图1～7显示依照本发明一实施例的方法制造半导体装置的中间阶段。
图8包含使用一步骤等离子体工艺及两步骤等离子体工艺所形成的表面的图像。
图9显示为使用一步骤等离子体工艺及两步骤等离子体工艺所形成的表面的粗糙度的比较图示。
图10显示为使用一步骤等离子体工艺及两步骤等离子体工艺的样本上所发现的污染物的比较表格。
其中，附图标记说明如下：
102～基材                    104～电路
108～层间介电层              110～接触点
112～金属间介电层            114～接触点
116～保护层                  118～导电垫
120～第一钝化层              210～第二钝化层
310～凸块下金属籽晶层        312～图案化掩模
410～导电柱体                412～导电盖层
414～焊料                    516～污染物
900～虚线                    1002～表格
1004～表格
具体实施方式
本发明接下来将会提供许多不同的实施例以实施本发明中不同的特征。然而，这些实施例并非用于限定本发明。以下所讨论的特定实施例仅用于举例本发明实施例的制造及使用，但不限定本发明的范畴。
在此所述的实施例是关于用于聚合物表面的两步骤等离子体处理，提供无污染物的表面供半导体装置使用。如以下所讨论，本发明实施例揭示使用一第一等离子体处理工艺自基材表面以使聚合物层表面粗糙化并使金属污染物结构松散以利后续蚀刻制成移除污染物，及使用第二等离子体处理工艺使表面较为光滑，其中基材可为裸片、晶片、印刷电路板、封装基材等。可相信的是，在此所述的工艺可使表面实质上无杂质，及提供较光滑的表面，且更避免及/或减少来自例如胶带工艺的污染物。在本发明所举例的各种图示及实施例中，相似参考标号代表相似元件。
图1-图7显示依照本发明一实施例的方法制造半导体装置的各种中间阶段。首先参见图1，其显示本发明一实施例的一部分的基材102，并可视需要形成电路104于其上。基材102可包含，例如，块材硅、掺杂或非掺杂的基材、或半导体有源层覆于绝缘层上(SOI)的基材。通常，半导体覆于绝缘层上(SOI)的基材包含例如硅的半导体材料层形成于绝缘层上。此绝缘层可例如为深埋氧化层(BOX)或氧化硅层。提供于基材上的绝缘层通常为硅或玻璃基材。亦可使用其他基材，例如多层或梯度基材。
各种特定应用的电路104可视需要形成于基材102上。在一实施例中，电路104包含形成于基材102上的一或多层介电层及其上的电子装置。可于介电层之间形成金属层以传递电子装置间的电子信号。亦可于一或多层的介电层中形成电子装置。
例如，电路104可包含各种N型金属氧化物半导体(NMOS)及/或P型金属氧化物半导体(PMOS)装置，例如晶体管、电容、电阻、二极管、光二极管、熔丝等，彼此相互连接以进行一或多种功能。这些功能可包含存储器结构、处理器结构、传感器、扩大器、配电器(power distribution)、输入/输出线路等。本领域技术人员可知的是，上述例子仅用以举例说明，以更加详尽解释各种实施例中的应用，但非通过上述方式限制本发明。于特定应用中亦可使用其他电路。
图1亦显示层间介电(inter-layer dielectric，ILD)层108。层间介电层108可由低介电常数材料形成，例如硅磷酸玻璃(phophosilicate glass，PSG)、硼硅磷酸玻璃(boronphosphosilicate glass，BPSG)、氟硅玻璃(FSG)、SiOxCy、旋涂式玻璃(spin-on glass)、旋涂式聚合物(spin-on polmers)、碳硅材料、前述的化合物、前述的复合材料或前述的组合等，并可由任何公知方法制成，例如旋转涂布(spinning)、化学气相沉积(CVD)、等离子体增强式化学气相沉积(plasma-enhanced CVD，PECVD)。值得注意的是，层间介电层108可包含多个介电层。
接触点，例如接触点110，形成贯穿层间介电层108，以与电路104电性接触。接触点110可由例如下述方法形成，使用光学光刻技术沉积光致抗蚀剂材料于层间介电层108上并作图案化，以暴露层间介电层的欲成为接触点的部分；进行蚀刻工艺(例如各向异性干蚀刻工艺)以在层间介电层中108形成开口，此开口可内衬有扩散阻障层及/或粘着层(未显示)；及填入导电材料于开口中。在一实施例中，扩散阻障层包含一或多层的氮化钽、钽、氮化钛、钛、钨钴合金(CoW)、或其类似物，且导电材料包含铜、钨、铝、银及前述的组合等，因而形成如图1所示的接触点110。
于层间介电层108上形成一或多层金属间介电层(inter-metallic dielectriclayer，IMD)112及对应的金属层。通常，一或多层金属间介电层112及对应的金属层用于此电路彼此间的相互连接，并提供至外部的电性连接。金属间介电层112可由低介电常数介电层形成，例如由等离子体增强式化学气相沉积、高密度等离子体化学气相沉积(HDPCVD)等方法所形成的氟硅玻璃，且包含中间蚀刻停止层。接触点114设置于最上端的金属间介电层中，以提供至外部的电性连接。
值得注意的是，可于两相邻介电层(例如层间介电层108及金属间介电层112)之间设置一或多层的蚀刻停止层(未显示)。一般来说，蚀刻停止层提供在形成通孔及/或接触点时，用以停止蚀刻的机制。蚀刻停止层由蚀刻选择性与相邻膜层(例如其下的半导体基材102、其上的层间介电层102及其上的金属间介电层112)不同的介电材料形成。在一实施例中，蚀刻停止层可由SiN、SiCN、SiCO、CN形成，其可由化学气相沉积(CVD)或等离子体增强式化学气相沉积(PECVD)等方法沉积形成。
保护层116可由介电材料(例如氮化硅、等离子体增强氧化物(plasma-enhanced oxide，PEOX)、等离子体增强氮化硅(plasma-enhancedSiN，PE-SiN)、未掺杂的硅玻璃(USG)、等离子体增强硅玻璃(PE-USG)等)形成于金属间介电层112的最上端表面上并作图案化，以在接触点114上方形成开口，并保护底下膜层免于受到各种环境污染物污染。随后，形成导电垫118于保护层116上并作图案化。导电垫118提供凸块下金属结构上(例如可形成外部连接的铜柱结构)的电性连接。导电垫118可由任何合适导电材料形成，例如铜、钨、铝、银、前述的组合或其类似物。
如图1所示，一或多层钝化层(passivation layer)，例如第一钝化层120，形成于导电垫118上并作图案化。第一钝化层120可为例如氮化硅、未掺杂的硅玻璃、等离子体增强硅玻璃、等离子体增强氮化硅、前述的组合及/或其类似物等介电材料，并可由例如化学气相沉积、物理气相沉积或其类似方法形成。在一实施例中，钝化层120包含氮化硅及等离子体增强硅玻璃的多层结构。
本领域技术人员可知的是，在此所示的单一膜层的导电垫及钝化层仅是用于举例。因此，在其他实施例中亦可包含任意层数的导电层及/或钝化层。此外，值得注意的是，一或多层的导电层可作为重分布层(RDL)，以提供所欲的节距(pitch)或球/凸块布局。
如上讨论的结构可使用任何合适工艺形成，故在此不多作赘述。如本领域技术人员可知的是，以上说明仅提供本发明实施例中的元件的概略描述，且亦可有其他众多元件存在。例如，可存在有其他电路、衬层、阻障层、凸块下金属结构(UBM)及其类似物。以上仅提供在此所讨论的实施例的内容，但非用以限制本发明的揭示内容或权利要求的保护范围至上述特定实施例中。
值得注意的是，在此所述的实施例中的基材102，在本发明一实施例中，为一部分的集成电路芯片。在其他实施例中，基材102可为转接板(interposer)(具有或无有源及/或无源电子元件形成于其上)、封装基材、层压基板、高密度内连线等。在其他实施例中，可具有或不具有各种如上所述的膜层，及可具有其他额外膜层。
图2显示于第一钝化层120上形成第二钝化层210并将其图案化，以暴露至少一部分的导电垫118。第二钝化层120可为由任何合适工艺(例如光刻涂布工艺)形成的聚合物，例如聚酰亚胺、聚苯恶唑(polybenzoxazole)或其类似物。
图3显示于第二钝化层210表面上沉积凸块下金属籽晶层(UBM seedlayer)310。凸块下金属籽晶层310为导电材料薄层，其帮助在随后工艺中形成较厚的膜层。在一实施例中，凸块下金属籽晶层310可使用例如化学气相沉积或物理气相沉积形成一或多层的薄导电层，例如铜、钛、钽、氮化钛、氮化钽、前述的组合或其类似物。例如，在一实施例中，可由物理气相沉积工艺沉积钛层以形成阻障层，并由物理气相沉积工艺沉积铜层于钛层上。钛层可避免或减少铜扩散至其底下的膜层中。亦可使用其他材料、厚度及工艺。
随后，如图3所示，依照本发明一实施例于凸块下金属籽晶层310上形成图案化掩模并将其图案化。图案化掩模312定义了于随后工艺中形成的导电柱体(将于以下详述)的横向边界。图案化掩模312可为图案化光致抗蚀剂掩模、硬掩模、前述的组合或其类似物。
图4显示依照本发明一实施例形成导电柱体410。导电柱体410可由任何合适材料形成，包含铜、镍、铂、铝、前述的组合或其类似物，并可通过任何种类的合适技术形成，包含物理气相沉积、化学气相沉积、电化学沉积(electrical chemical deposition，ECD)、分子束外延(molecular beam epitaxy，MBE)、原子层沉积、电镀等。值得注意的是，在某些实施例中，例如沉积(例如物理气相沉积及化学气相沉积)顺应性的膜层于晶片的整个表面上，需进行蚀刻及平坦化工艺(例如化学机械研磨)以自图案化掩模312表面移除多余的导电材料。
值得注意的是，在此所述的薄层导电柱体仅用以举例。在其他实施例中，导电柱体410可更厚，例如厚度约20μm至50μm。导电柱体410可为具有任何足以满足应用需求的厚度。导电柱体410可具有任意形状。
图4亦显示盖层412可视需要形成于导电柱体410上。如以下的详细讨论，焊料将形成于导电柱体416上。在回焊工艺(soldering process)期间，自然地形成介金属化合物(inter-metallic compound，IMC)(未显示)于焊料与其底下表面的交界处。可发现到某些材料，相较于其他材料，可形成更坚固且更耐用的介金属化合物层。如此，优选需形成盖层，例如导电盖层412，以提供性质更佳的介金属化合物层。在一实施例中，导电柱体410由铜形成，导电盖层412优选为由镍形成，或亦可由其他材料形成，例如铂、金、银或前述的组合。导电盖层412可由任何合适技术形成，例如物理气相沉积、化学气相沉积、电化学沉积(electrical chemical deposition，ECD)、分子束外延(molecular beam epitaxy，MBE)、原子层沉积、电镀等技术。
此外，图4亦显示形成焊料414。在一实施例中，焊料414包含锡铅合金(SnPb)、高铅材料(例如Sn95Pb5)、锡基焊料(Sn-based solder)、无铅焊料或其他合适导电材料。
随后，如图5所示，移除图案化掩模312(参见图4)。在一实施例中，图案化掩模312由光致抗蚀剂材料形成，可使用例如由乳酸乙酯、苯甲醚(anisole)、乙酸异戊酯(methyl butyl acetate)、乙酸戊酯(amyl acetate)、甲酚树脂(cresol novolac resin)、重氮感光化合物(diazo photoactivecompound，称为SPR9)所组成的混合物的化学溶液予以移除，或由其他剥除工艺移除。可进行对第一凸块下金属的蚀刻工艺以自第二钝化层210表面移除部分的凸块下金属籽晶层310。在一实施例中，可将含钛层及铜层的凸块下金属籽晶层310湿浸至由磷酸及过氧化氢组成的化学溶液(称为DPP)及1％的氢氟酸中以作移除，或使用其他清洁工艺。
如图5所示，就算在上述清洁工艺之后，污染物516仍可能残存在第二钝化层210表面。为了移除这些污染物，可进行一或多次的等离子体处理。在一实施例中，进行第一等离子体处理以稍微地粗糙化第二钝化层210表面，因而释放松散(loosen)出污染物516。随后进行第二等离子体工艺以减少(但不完全消除)第二钝化层210的粗糙度。
在一实施例中，第一等离子体工艺包含使用氮气(N2)等离子体工艺，其条件为约100sccm至约1000sccm的氮气流速、约16Pa至约100Pa的压力、约500Watts至约2000Watts的微波功率、及约250Watts至约500Watts的射频功率。氮气等离子体处理可进行约10秒至约90秒，以足够使第二钝化层210足够粗糙并释放出污染物516。
在另一实施例中，第一等离子体工艺包含使用四氟化碳/氧气(CF4/O2)等离子体处理，其条件为约50sccm至约200sccm的四氟化碳流速、约50sccm至约200sccm的氧气流速、约16Pa至约100Pa的压力、约500Watts至约2000Watts的微波功率、及约100Watts至约400Watts的射频功率。四氟化碳/氧气等离子体处理可进行约10秒至约90秒，以足够使第二钝化层210足够粗糙并释放松散出污染物516。
随后，可进行对第二凸块下金属的蚀刻工艺。在经第一等离子体处理释放松散松散污染物之后，可使用第二凸块下金属的蚀刻工艺来移除释放出来的污染物。在一实施例中，第二凸块下金属的蚀刻工艺可包含使用湿浸至1％的氢氟酸中或其他清洁工艺，以蚀刻包含钛层及铜层的第二凸块下金属层。可相信的是，当凸块下金属籽晶层310包含钛层及铜层时，污染物绝大部分是钛污染物。因此，湿浸至1％的氢氟酸中主要是用以蚀刻钛污染物。如有发现其他污染物，亦可使用其他种类的蚀刻剂，例如用以移除铜污染物的DPP溶液。
图6显示第二钝化层210的粗糙表面及在第一等离子体处理及第二凸块下金属蚀刻工艺后的污染物516(参见图5)的移除。在此阶段中，亦可进行氧气等离子体处理以移除任何由等离子体处理与保护层材料210(例如聚合物)反应形成的副产物。图6亦显示回焊工艺。
图7显示依照本发明一实施例的第二等离子体处理。如前述，可发现于随后工艺(例如晶背端薄化工艺)中施予胶带或其他粘着剂至此粗糙表面(例如其他系统所使用者)，通常造成胶带残留物残存在保护层210的粗糙表面上，其可能造成第二钝化层210及底部填充材料之间的脱层。在焊料414上的胶带残留物亦可能造成冷焊(cold joint)。在这些情况下，优选需进行第二等离子体处理以使第二钝化层210表面较为光滑，或使第二钝化层210表面较不粗糙。较光滑的表面可残留较少的胶带残余物。
在一实施例中，第二等离子体工艺包含使用氮气等离子体工艺，其条件为约100sccm至约1000sccm的氮气流速、约16Pa至约100Pa的压力、约500Watts至约2000Watts的微波功率及约50Watts至约250Watts的射频功率。氮气等离子体处理可进行约10秒至约90秒。
在另一实施例中，第二等离子体处理包含使用氩气/氧气(Ar/O2)等离子体处理，其条件为约50sccm至约200sccm的氩气流速、约50sccm至约200sccm的氧气流速、约16Pa至约100Pa的压力、约50001Watts至约2000Watts的微波功率及约50Watts至约250Watts的射频功率。氩气/氧气等离子体处理可进行约10秒至约90秒。
图8显示由上述讨论的实施例所得到的结果。图8A-1至图8D-1显示经上述两步骤等离子体处理后的聚合物表面由100K扫瞄式电子显微镜(Scanning Electron Micriscopy，SEM)得到的图像。图8A-1至图8D-1的表面粗糙度经量测得到各自为2.84％、2.92％、2.2％、3.9％，其由原子力显微镜(Atomic Force Microscopy，AFM)以表面积差异比率系数(index of surfacearea difference percentage，index of SADP)量测得到。通常，表面积差异比率(SADP)为用以量测三维表面的粗糙度的等式，其为将三维面积及二维面积之间的差除以二维面积后乘上100，易言之，即为(((3D面积-2D面积)/2D面积)*100)。
相较之下，图8A-2至图8D-2显示仅进行一次粗糙化等离子体处理的聚合物表面的100K SEM图像。该些表面由SAPD所测得的表面粗糙度各自为13.9％、22.5％、12.3％及9.41％，。
图9显示第二钝化层210在经两步骤等离子体工艺及一步骤等离子体工艺后的表面粗糙度的差异比较。特别是虚线900左边的样本为使用如前述的两步骤等离子体处理后的第二钝化层210的表面粗糙度。如图9所示，两步骤等离子体工艺可得到约1％至约8％的表面粗糙度，然而，一步骤等离子体工艺得到大于8％的表面粗糙度。
图10为两个表格，其显示经两步骤等离子体处理及一步骤等离子体处理后的第二钝化层210的表面成分鉴定。表格1004显示保护层210表面在经一步骤等离子体处理后的所发现的钛、氟、锡、铅的含量，及表格1002显示保护层210表面在经两步骤等离子体处理后所发现的钛、氟、锡、铅的含量，上述含量由X光电子能谱(X-ray Photoelectron Spectroscopy，XPS)测得。在图10中可见，两步骤等离子体处理显著地减少了上述元素的含量。
可相信的是，两步骤等离子体工艺所造成的表面粗糙度可使凸块下金属籽晶层残余物被有效移除，然亦得到一表面粗糙度可避免或减少例如胶带残余物的粘着污染物。
虽然本发明已以数个优选实施例公开如上，然其并非用以限定本发明，任何所属技术领域中的技术人员，在不脱离本发明的精神和范围内，当可作任意的更动与润饰，因此本发明的保护范围当视随附的权利要求所界定的保护范围为准。此外，本领域技术人员将可依照本发明所揭示的现有或未来所发展的特定程序、机器、制造、物质的组合、功能、方法或步骤达成相同的功能或相同的结果。因此本发明的保护范围包含这些程序、机器、制造、物质的组合、功能、方法或步骤。此外，每个权利要求建构成一独立的实施例，且各种权利要求及实施例的组合皆介于本发明的范围内。

Claims (9)

1.一种半导体装置的制造方法，包括：
形成一基材；
形成一接触垫于该基材上；
形成一聚合物保护层于该接触垫上，以暴露至少一部分的该接触垫；
形成一凸块下金属结构与该接触垫电性连接；
形成一导电凸块于该凸块下金属结构上；
于该聚合物保护层的暴露表面上进行一第一等离子体工艺，该第一等离子体工艺使该保护层的一表面粗糙化；
于进行该第一等离子体工艺后，进行一或多次工艺步骤；以及
于该聚合物保护层的暴露表面上进行一第二等离子体工艺，该第二等离子体工艺减少该保护层的粗糙度。
2.如权利要求1所述的半导体装置的制造方法，其中该聚合物保护层为聚酰亚胺或聚苯恶唑。
3.如权利要求1所述的半导体装置的制造方法，其中所述一或多次工艺包含一蚀刻工艺，以移除由该第一等离子体工艺松散释放的污染物。
4.如权利要求1所述的半导体装置的制造方法，其中该第一等离子体工艺包含氮气等离子体处理或四氟化碳/氧气等离子体处理。
5.如权利要求1所述的半导体装置的制造方法，其中该第二等离子体工艺包含氮气等离子体处理或氩气/氧气等离子体处理。
6.一种半导体结构，该半导体结构为采用权利要求1-5中任一所述的制造方法制造，该半导体结构包括：
一基材，具有一接触垫形成于其上；
该聚合物层位于该基材上，该聚合物层的由原子力显微镜以表面积差异比率系数所测得的表面粗糙度介于1％至8％之间，且该聚合物层具有一开口暴露至少一部分的导电垫，其中该聚合物层的钛表面污染物小于约1％、氟表面污染物小于约1％、锡表面污染物小于约1.5％、及铅表面污染物小于约0.4％；以及
一凸块下金属结构，延伸贯穿该开口并与该导电垫电性连接。
7.如权利要求6所述的半导体结构，其中该聚合物层包含聚酰亚胺。
8.如权利要求6所述的半导体结构，其中该聚合物层包含聚苯恶唑。
9.如权利要求6所述的半导体结构，还包含一导电凸块，其与该凸块下金属结构电性连接，其中该凸块下金属结构包含一钛层及一铜层。
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