TWI541964B - 半導體基板之製法 - Google Patents

半導體基板之製法 Download PDF

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Publication number
TWI541964B
TWI541964B TW099140299A TW99140299A TWI541964B TW I541964 B TWI541964 B TW I541964B TW 099140299 A TW099140299 A TW 099140299A TW 99140299 A TW99140299 A TW 99140299A TW I541964 B TWI541964 B TW I541964B
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Taiwan
Prior art keywords
layer
opening
insulating protective
protective layer
metal layer
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TW099140299A
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English (en)
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TW201222747A (en
Inventor
簡豐隆
陳宜興
郭夔孝
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矽品精密工業股份有限公司
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Priority to TW099140299A priority Critical patent/TWI541964B/zh
Priority to US12/987,571 priority patent/US20120126397A1/en
Publication of TW201222747A publication Critical patent/TW201222747A/zh
Application granted granted Critical
Publication of TWI541964B publication Critical patent/TWI541964B/zh

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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K1/00—Soldering, e.g. brazing, or unsoldering
    • B23K1/0008—Soldering, e.g. brazing, or unsoldering specially adapted for particular articles or work
    • B23K1/0016—Brazing of electronic components
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K3/00—Tools, devices, or special appurtenances for soldering, e.g. brazing, or unsoldering, not specially adapted for particular methods
    • B23K3/06—Solder feeding devices; Solder melting pans
    • B23K3/0607—Solder feeding devices
    • B23K3/0623—Solder feeding devices for shaped solder piece feeding, e.g. preforms, bumps, balls, pellets, droplets
    • B—PERFORMING OPERATIONS; TRANSPORTING
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    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K3/00—Tools, devices, or special appurtenances for soldering, e.g. brazing, or unsoldering, not specially adapted for particular methods
    • B23K3/08—Auxiliary devices therefor
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Description

半導體基板之製法
本發明係有關一種半導體基板及其製法，尤指一種避免銲球發生破裂之半導體基板及其製法。
隨著電子產業的蓬勃發展，電子產品亦逐漸邁入多功能、高性能的研發方向。目前半導體晶片之設計係包括有打線式(wire bonding)及覆晶式(flip chip)等，以將晶片接置於封裝基板上，且於該晶片及封裝基板之間設置金線或導電凸塊，使該晶片電性連接至該封裝基板上。
而為達多功能、高作動功率、使用壽命長，晶片之電性穩定度係相當重要。可參考第6,107,180或US 6,111,321號美國專利，或請參閱第1圖，係為習知半導體元件之剖面示意圖。
如第1圖所示，習知半導體元件1包括：具有電性接觸墊100之晶圓(Wafer)10、設於該晶圓10上且外露該電性接觸墊100之絕緣保護層11、設於該外露之電性接觸墊100上之底凸塊金屬層(Under Bump Metal,UBM)12、以及設於該UBM層12上之銲球16。
惟，由於該晶圓10與該UBM層12之熱膨脹係數(Coefficient of Thermal Expansion,CTE)不匹配，故當該半導體元件1進行溫度測試時，容易導致該UBM層12剝離，使該銲球16發生脫落或破裂(crack)等問題，以致於當後續進行覆晶(flip chip)製程時，該電性接觸墊100無法有效連接至封裝基板上，進而無法有效產生電性連接，導致產品之良率降低。
請再參閱第2A至2B圖，係為另一習知半導體元件1’之製法之剖面示意圖。如第2A圖所示，先於一具有電性接觸墊100’之晶圓10’上形成阻層15，且利用曝光顯影之方式使該阻層15形成開孔150，以外露出該電性接觸墊100’。接著，以刷塗(printing)方式形成銲料(solder paste)160於該開孔150中之電性接觸墊100’上。最後，如第2B圖所示，移除該阻層15，再經回銲(reflow)製程，使該銲料160形成銲球16’。
惟，由於該銲料160係以刷塗方式形成之，因而不易於該開孔150中填充完全，以致於當經回銲製程後，該銲球16’容易產生空孔(void)現象，且易因電子遷移(electro migration,EM)而導致該銲球16’產生局部熔融(local melting)，使當後續進行覆晶(flip chip)製程時，該電性接觸墊100’無法有效連接至封裝基板上，進而無法有效產生電性連接，因而產品之良率降低。
因此，如何避免上述習知技術之種種問題，實為當前所要解決的目標。
為克服習知技術之種種缺失，本發明係提供一種半導體基板，係包括：基板，其表面上具有電性接觸墊；第一絕緣保護層，設於該基板與電性接觸墊上，該第一絕緣保護層具有第一開孔，以令該電性接觸墊外露於該第一開孔中；金屬層，係設於該第一開孔中之電性接觸墊上，且延伸至該第一絕緣保護層之部分表面上；第二絕緣保護層，係設於該第一絕緣保護層及金屬層上，該第二絕緣保護層具有第二開孔，以令該金屬層外露於該第二開孔中，且該第二絕緣保護層覆蓋位於該第一絕緣保護層上之金屬層；以及銲球，係設於該第二開孔中之金屬層上。
前述之半導體基板中，該金屬層係為底凸塊金屬層(Under Bump Metal)，且形成該底凸塊金屬層之材質如鈦/銅/鎳、或鈦/鎳釩/銅。
前述之半導體基板中，形成該銲球之材質係為錫。
前述之半導體基板中，該銲球具有銅材。
本發明復揭露一種半導體基板之製法，係包括：提供一表面上具有電性接觸墊及覆蓋該電性接觸墊之第一絕緣保護層之基板，其中，該第一絕緣保護層具有第一開孔，以令該電性接觸墊外露於該第一開孔中；於該第一開孔中及電性接觸墊上形成金屬層，且該金屬層延伸至該第一絕緣保護層之部分表面上；於該第一絕緣保護層及金屬層上形成第二絕緣保護層，該第二絕緣保護層具有第二開孔，以令該金屬層外露於該第二開孔中，且該第二絕緣保護層覆蓋位於該第一絕緣保護層上之金屬層；以及形成具有銅材之銲球於該第二開孔中之金屬層上。
前述之製法中，該銲球之製程，係包括：形成銅層於該第二絕緣保護層上及該第二開孔中之金屬層上；形成阻層於該銅層上，且該阻層具有第三開孔，以外露出該金屬層上之銅層；形成銲料於該第三開孔中及該第三開孔內之銅層上；移除該阻層及其下之銅層；以及融合該銲料及其下之銅層，以形成該具有銅材之銲球。
前述之製法中，係可以電鍍形成該銲料。
前述之半導體基板及其製法中，該基板係可為晶圓。
由上可知，本發明之半導體基板及其製法，係藉由該第二絕緣保護層覆蓋於該金屬層之周圍上，相較於習知技術，當本發明之半導體基板進行溫度測試時，可避免該銲球發生脫落或破裂等問題。
再者，藉由電鍍方式形成該銲料，可使該銲料完全填充於該開孔中，相較於習知技術，本發明可避免該銲球產生空孔現象，且可避免該銲球因局部熔融導致電性連接不良之情形。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”、“一”及“下”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
請參閱第3A至3H圖，係揭示本發明半導體基板2之製法。
如第3A圖所示，提供一表面上具有電性接觸墊200及覆蓋該電性接觸墊200之第一絕緣保護層21之基板20，其中，該第一絕緣保護層21具有第一開孔210，以令該電性接觸墊200外露於該第一開孔210中。於本實施例中，該基板20係可為覆晶式之晶圓。
如第3B圖所示，形成金屬層22於該第一開孔210中之孔壁上及電性接觸墊200上，且該金屬層22延伸至該第一絕緣保護層21之部分表面上。
於本實施例中，該金屬層22係為底凸塊金屬層(Under Bump Metal,UBM)，且形成該底凸塊金屬層之材質係例如：鈦/銅/鎳、或鈦/鎳釩/銅。再者，可藉由濺鍍(sputter)或鍍覆(plating)配合曝光顯影之方式，進行圖案化製程，以形成該金屬層22。
如第3C圖所示，形成第二絕緣保護層23於該第一絕緣保護層21及金屬層22上，該第二絕緣保護層23具有第二開孔230，以令該金屬層22外露於該第二開孔230中，且該第二絕緣保護層23覆蓋位於該第一絕緣保護層21上之金屬層22。
如第3D圖所示，以濺鍍(sputter)方式，形成銅層24於該第二絕緣保護層23上及該第二開孔230中之金屬層22上。
如第3E圖所示，形成阻層25於該銅層24上，且該阻層25係可為光阻，故藉由曝光顯影之方式，使該阻層25形成圖案化之第三開孔250，以外露出該金屬層22上之銅層24。如圖所示，前述之第一開孔210、第二開孔230及第三開孔250係互相對應設置。
如第3F圖所示，以電鍍方式形成銲料(solder paste)260於該第三開孔250中、第二開孔230中及銅層24上。於本實施例中，形成該銲料260之材質係為錫。
如第3G圖所示，移除該光阻層25，再蝕刻移除該光阻層25下之銅層24，以保留該銲料260下之銅層24。
如第3H圖所示，經回銲(reflow)製程，使該銲料260形成銲球26，同時該銲料260下之銅層24會熔入該銲球26中，以形成具有銅材之銲球26於該第二開孔230中之金屬層22上。於後續製程中，該銲球26以覆晶(flip chip)方式電性連接至封裝基板上。
本發明藉由該第二絕緣保護層23覆蓋於該金屬層22上，使該第二絕緣保護層23可防止該金屬層22剝離，故當半導體基板2進行溫度測試時，該銲球26不會發生脫落或破裂(crack)等問題。因此，當後續進行覆晶製程時，該電性接觸墊200可有效電性連接至封裝基板上，俾提升產品之良率。
再者，藉由電鍍方式形成該銲料260，可使該銲料260完全填充於該第三開孔250及第二開孔230中，當經回銲製程後，再藉由銅層24熔入該銲球26中，不僅可避免該銲球26產生空孔(void)現象，且可避免該銲球26因局部熔融導致電性連接不良之情形。因此，當後續進行覆晶製程時，該電性接觸墊200可有效電性連接至封裝基板上，俾提升產品之良率。
本發明復提供一種半導體基板2，係包括：表面上具有電性接觸墊200之基板20、設於該基板20上且外露該電性接觸墊200之第一絕緣保護層21、設於該電性接觸墊200上之金屬層22、設於該第一絕緣保護層21及金屬層22上之第二絕緣保護層23、以及設於該金屬層22上之具有銅材之銲球26。
所述之基板20係可為晶圓。
所述之第一絕緣保護層21具有第一開孔210，以令該電性接觸墊200外露於該第一開孔210中。
所述之金屬層22係設於該第一開孔210中之電性接觸墊200上，且延伸至該第一絕緣保護層21之部分表面上。再者，該金屬層22係為底凸塊金屬層(UBM)，且形成該UBM之材質係可為鈦/銅/鎳、或鈦/鎳釩/銅。
所述之第二絕緣保護層23具有第二開孔230，以令該金屬層22外露於該第二開孔230中，且該第二絕緣保護層23覆蓋位於該第一絕緣保護層21上之金屬層22。
所述之具有銅材之銲球26係設於該第二開孔230中之金屬層22上，且形成該銲球26之材質係為錫。
綜上所述，本發明之半導體基板及其製法，藉由該第二絕緣保護層覆蓋於該金屬層之周圍上，以當半導體基板進行溫度測試時，該銲球不會發生脫落或破裂等問題。
再者，藉由電鍍方式形成銲料，可使該銲料完全填充於該開孔中，當經回銲製程後，不僅可避免該銲球產生空孔現象，且可避免該銲球因局部熔融導致電性連接不良之情形。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
1、1’．．．半導體元件
10、10’．．．晶圓
100、100’、200．．．電性接觸墊
11．．．絕緣保護層
12．．．底凸塊金屬層
15、25．．．阻層
150．．．開孔
16、16’、26．．．銲球
160、260．．．銲料
2．．．半導體基板
20．．．基板
21．．．第一絕緣保護層
210．．．第一開孔
22．．．金屬層
23．．．第二絕緣保護層
230．．．第二開孔
24．．．銅層
250．．．第三開孔
第1圖係為習知半導體元件之局部剖面示意圖；
第2A至2B圖係為另一習知半導體元件之製法之剖面示意圖；以及
第3A至3H圖係為本發明半導體基板之製法之剖面示意圖。
2．．．半導體基板
20．．．基板
200．．．電性接觸墊
21．．．第一絕緣保護層
210．．．第一開孔
22．．．金屬層
23．．．第二絕緣保護層
230．．．第二開孔
26．．．銲球

Claims (3)

  1. 一種半導體基板之製法，係包括：提供一表面上具有電性接觸墊及覆蓋該電性接觸墊之第一絕緣保護層之基板，其中，該第一絕緣保護層具有第一開孔，以令該電性接觸墊外露於該第一開孔中；於該第一開孔中及電性接觸墊上形成金屬層，且該金屬層延伸至該第一絕緣保護層之部分表面上；於該第一絕緣保護層及金屬層上形成第二絕緣保護層，該第二絕緣保護層具有第二開孔，以令該金屬層外露於該第二開孔中，且該第二絕緣保護層覆蓋位於該第一絕緣保護層上之金屬層；形成銅層於該第二絕緣保護層上及該第二開孔中之金屬層上；形成阻層於該銅層上，且該阻層具有第三開孔以外露出該金屬層上之該銅層；形成錫銲料於該第三開孔中及該第三開孔內之該銅層上；移除該阻層及該阻層下之該銅層；以及融合該錫銲料及該錫銲料下之該銅層，以形成由錫銅銲料共同熔融為一體所構成之銲球，且該錫銅銲料之銅係熔入該銲球中。
  2. 如申請專利範圍第1項所述之半導體基板之製法，其中，該基板係為晶圓。
  3. 如申請專利範圍第1項所述之半導體基板之製法，其中，係電鍍形成該銲料。
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