JP4724192B2 - 電子部品の製造方法 - Google Patents

電子部品の製造方法 Download PDF

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Publication number
JP4724192B2
JP4724192B2 JP2008047950A JP2008047950A JP4724192B2 JP 4724192 B2 JP4724192 B2 JP 4724192B2 JP 2008047950 A JP2008047950 A JP 2008047950A JP 2008047950 A JP2008047950 A JP 2008047950A JP 4724192 B2 JP4724192 B2 JP 4724192B2
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Japan
Prior art keywords
film
metal
solder
manufacturing
electronic component
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Expired - Fee Related
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JP2008047950A
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JP2009206334A (ja
Inventor
匡 飯島
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Toshiba Corp
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Toshiba Corp
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Priority to JP2008047950A priority Critical patent/JP4724192B2/ja
Priority to TW098103292A priority patent/TWI429790B/zh
Priority to US12/369,794 priority patent/US20090218230A1/en
Publication of JP2009206334A publication Critical patent/JP2009206334A/ja
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Publication of JP4724192B2 publication Critical patent/JP4724192B2/ja
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    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457Solder materials or compositions; Methods of application thereof
    • H05K3/3473Plating of solder
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C18/00Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
    • C23C18/54Contact plating, i.e. electroless electrochemical plating
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    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
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Description

本発明は、半田バンプからなる接続端子を備えた電子部品の製造方法に関する。
従来から、半導体チップ上に形成された半田バンプにより半導体チップとBGA基板等のインターポーザ基板とをフリップチップ接続する技術が知られている。半田バンプには、これまでSn−Pb等のPb系半田が用いられてきたが、近年は、環境保全の観点からPbを含まない無鉛半田(例えば、Sn−Cu、Sn−Ag−Cu等)に置き換わりつつある。
かかる無鉛半田からなるバンプの形成方法として、半田の構成元素のCuからなる層を基板上にスパッタリングなどにより下地金属(UBM:under bump metal)層として形成し、その上に電解めっきによりSn半田またはSn−Ag半田を堆積し、その後、半田をリフローする際に、UBM層のCuを半田内に溶解させ、それぞれSn−CuまたはSn−Ag−Cu半田を形成する方法が提案されている(例えば、特許文献1参照。)。この方法は、半田の第2または第3の元素であるCuをUBM層から取り込むことで、めっきを行う元素数を減らし、めっき工程の簡素化を図ろうとするものである。すなわち、めっき工程は、めっき元素数が多くなるほど、めっき液の化学的性質の維持や組成の精密な制御が複雑となる。めっきする元素数を減らすことによって、このような複雑な管理、制御を単純化できると考えられる。
ところで、この方法においては、Sn半田またはSn−Ag半田をめっき後、バンプ形成部分以外のUBM層を除去する必要がある。このUBM層の除去には、ウエットエッチング、ドライエッチング等が用いられるが、生産性や経済性の観点からは処理速度の速いウエットエッチングが適している。しかしながら、ウエットエッチングを用いた場合、エッチングが等方的に進行するため、めっき層下のUBM層(Cu層)に比較的大きなアンダーカットを生じる。その結果、半田バンプの最終組成が変化し、融点の変化や機械的強度の低下により、実装の歩留まり低下を招くおそれがあった。また、近年、半田バンプは狭ピッチ化(例えば、50μm以下)が進んでいるが、この場合、アンダーカットの半田組成に与える影響は特に大きい。さらに、アンダーカット量が多くなると半田リフロー後のバンプ径が小さくなってその制御が難しく、かつ下地との密着性が低下して剥がれが生じやすくなってしまう。このため、狭ピッチの半田バンプの形成には、ウエットエッチングを用いた上記方法を適用できず、生産性や経済性の向上が図れないという問題があった。
特開2005−294827号公報
本発明の目的は、半田バンプの構成元素を含むUMB層をウエットエッチング法により除去する際のアンダーカットの発生を防止することができる電子部品の製造方法を提供することにある。
本発明の一態様によれば、基板上に半田バンプを形成する電子部品の製造方法であって、前記基板上に第1の金属からなる膜を形成する工程(A)と、置換めっきにより、前記第1の金属からなる膜を部分的に、前記第1の金属よりの金属である第2の金属を含む膜に変換する工程(B)と、前記第2の金属を含む膜上に、第3の金属からなる膜を形成する工程(C)と、前記第3の金属からなる膜をマスクとして前記第2の金属を含む膜以外の第1の金属からなる膜をウエットエッチングにより除去する工程(D)とを具備することを特徴とする電子部品の製造方法が提供される。
本発明の一態様による電子部品の製造方法によれば、半田バンプの構成元素を含むUMB層をウエットエッチング法により除去する際のアンダーカットの発生を防止することができる。
以下、本発明の実施の形態について説明する。なお、以下では本発明の実施の形態を図面に基づいて説明するが、それらの図面は図解のために提供されるものであり、本発明はそれらの図面に限定されるものではない。
(第1の実施の形態)
第1の実施の形態について説明する。図1(a)〜(g)は本実施形態に係る電子部品の製造方法の工程を示す断面図である。本実施の形態では、電子部品にSn−Ag−Cu三元系無鉛半田またはSn−Ag二元系無鉛半田からなるバンプを形成する場合を説明する。
まず、図1(a)に示すように、図示しない電極パッドおよびパッシベーション膜が設けられた半導体チップ等の電子部品の基板11上に、UBM層12として、例えば5000オングストローム厚のTi膜13、および例えば1μm厚のCu膜14を、無電解めっき、蒸着、スパッタリング等により順に成膜する。なお、UBM層12の第1層は、Tiの他、Ta、W、Cr、V、Zr、Ni、これらの合金または化合物などで構成してもよく、また、これらの膜を複数積層する積層構造としてもよい。
次に、図1(b)に示すように、スピンコート技術を用いてCu膜14上に例えば70μm厚のレジスト膜15を積層した後、リソグラフィ技術を用いてバンプを形成する箇所にのみレジスト膜15に、例えばその外接円の直径が100μmからなる八角形状の開口15aを形成する。
次に、図1(c)に示すように、UBM層12(Cu層14)に通電するとともに開口15a内にAgめっき液を供給して、電解めっきにより、開口15aの底部に露出するCu膜14上に、Cuより貴の金属であるAgからなる膜16を形成する。この際、UBM層12への通電に先立って、CuとAgの電位差を利用して、Cuの少なくとも一部をAgに置換する置換めっきを行い、Cu膜14の開口15aの底部に露出する部分を選択的にCu−Ag(もしくはAg)からなる膜14aに変換させる。その後、通電を開始して、例えば1μm厚のAg膜16を形成する。
なお、CuのAgへの置換の割合や、形成するAg膜16の厚さは、最終的に形成しようとする半田バンプの組成により適宜定められる。したがって、場合により、Ag膜16を形成せず、置換めっきのみ行うことも可能である、この場合、Cu−Ag(もしくはAg)膜14aの直上に、後述するSn膜17が形成される。また、Cuの一部をAgに置換させた場合、その後に熱処理することによって、合金化もしくは化合物化してもよい。合金化もしくは化合物化することによって、後述するCuウエットエッチングの際のエッチング選択性をより高められる利点を有する。
次に、図1(d)に示すように、UBM層12に通電するとともに開口15a内にSnめっき液を供給して、電解めっきにより、開口15aの底部に露出するAg膜16上、またはCu−Ag(もしくはAg)膜14a上に、例えば50μm厚のSn膜17を形成する。このSn膜17の厚さも、最終的に形成しようとする半田バンプの組成により適宜定められる。なお、Sn膜17は、電解めっきによらず、蒸着、スパッタリング、無電解めっき、その他の一般に知られる方法により形成してもよい。
次に、図1(e)に示すように、レジスト膜15をレジスト剥離液等の薬液を用いて剥離した後、Sn膜17、または、Sn膜17およびAg膜16をマスクとしてCu膜14をウエットエッチングにより除去する。この際、エッチング液として、アンモニアと過酸化水素水、硫酸と過酸化水素水、燐酸と過酸化水素水等の、Cuは溶解するが少なくともAgは溶解しないかもしくは溶解し難いエッチング液を使用する。具体的には、Cu用エッチング液として市販されている三菱ガス化学社製のWLC−C(商品名)等が好適に使用される。このようなエッチング液を用いることにより、Cu膜14のみが選択的に除去され、ウエットエッチングにともなうSn膜17およびAg膜16下のアンダーカットの発生を抑制乃至防止することができる。
すなわち、図2は、Cu膜14にCu−Ag(もしくはAg)膜14aを設けることなくAg膜16およびSn膜17を形成した以外は、本実施の形態と同様にして成膜した後、Cu膜14にウエットエッチング処理した場合の例を示したもので、Cu膜14のSn膜17およびAg膜16下に明らかにアンダーカット18が発生していることがわかる。本実施の形態においては、Cu膜14の開口15aの底部に露出する部分を選択的にCu−Ag(もしくはAg)からなる膜14aに変換し、かつCuは溶解するが少なくともAgは溶解しないかもしくは溶解し難いエッチング液を使用しているので、Cu膜14のみを選択的に除去することができ、Sn膜17およびAg膜16下のアンダーカットの発生を抑制乃至防止することができる。
次に、図1(f)に示すように、UBM層12の第1層のTi膜13を、Sn膜17、Ag膜16およびCu−Ag(もしくはAg)膜14aをマスクとしてウエットエッチングにより除去する。エッチング液としては、Sn膜17、Ag膜16およびCu−Ag(もしくはAg)膜14aを溶解しないものが好ましく、例えば0.5〜1質量%程度に希釈した希フッ酸、KOHと過酸化水素水、Ti用エッチング液として市販されている三菱ガス化学社製のWLC−T(商品名)等が好適に使用される。Ti膜13はCu−Ag(もしくはAg)膜14aが形成されたCu膜14と異なり全体が同質であるため、Cu−Ag(もしくはAg)膜14a下にアンダーカット18が発生する。しかしながら、その量は、例えばCu−Ag(もしくはAg)膜14aの端部からウエットエッチング後のTi膜13の端部までの距離が例えば0.1μm程度と非常に小さく、また、半田バンプの最終組成に影響することもないので、実用上問題となることはない。
その後、図1(g)に示すように、通常の半田リフロー処理を行う。この処理によりSn膜17とAg膜16とCu−Ag(もしくはAg)膜14aが共晶化して合金化し、Sn、AgおよびCuの各元素の成分比に応じたSn−Ag−Cu三元系またはSn−Ag二元系の半田バンプ19が形成される。なお、リフロー処理工程はTi膜13を除去する前に行ってもよい。この場合、Sn−Ag−Cu三元系またはSn−Ag二元系の半田バンプ19がTi膜13をウエットエッチングする際のマスクとして使用される。
本実施の形態では、UBM層12として形成したCu膜14の半田バンプ形成部分を、Cu−Ag(もしくはAg)膜14aに変換させているので、半田バンプ形成部分以外のCu膜14をウエットエッチング法により除去する際に、その除去すべきCu膜14のみを選択的に除去することができ、アンダーカットの発生を抑制乃至防止することができる。これにより、半田バンプの最終組成を精密に制御することが可能になり、融点の変化や機械的強度、密着性の低下による実装の歩留まり低下を防止することができる。また、狭ピッチの半田バンプであってもその最終組成、寸法を精密に制御することができるため、Cu膜のエッチングにウエットエッチングを適用することが可能になり、狭ピッチの半田バンプを含む電子部品の生産性の向上および製造コストの低減を図ることができる。
(その他の実施の形態)
上記第1の実施の形態では、Sn−Ag−Cu三元系無鉛半田またはSn−Ag二元系無鉛半田からなるバンプを形成する場合について説明したが、このような組成以外の半田からなるバンプを形成する場合も、材料や工程を適宜選択することによって広く適用可能であることはいうまでもない。
例えば、第1の実施の形態において、Ag膜16に代えてAu膜を形成した場合には、Sn−Au−Cu三元系無鉛半田またはSn−Au二元系無鉛半田からなるバンプを形成することができる。Cu膜14に代えてBi膜を形成した場合には、Sn−Ag−Bi三元系無鉛半田またはSn−Ag二元系無鉛半田からなるバンプを形成することができる。この場合、さらに、Ag膜16に代えてAu膜を形成すると、Sn−Au−Bi三元系無鉛半田またはSn−Au二元系無鉛半田からなるバンプを形成することができる。Cu膜14に代えてAg膜を形成し、Ag膜16に代えてAu膜を形成した場合には、Sn−Au−Ag三元系無鉛半田またはSn−Au二元系無鉛半田からなるバンプを形成することができる。
また、Sn膜17上またはSn膜17下に1層もしくはそれ以上の他の金属からなる膜をさらに成膜することも可能であり、これにより四元系以上の半田(例えば、Sn−Ag−In−Bi等)からなるバンプの形成が可能となる。
さらに、上記第1の実施の形態では、Cu膜14を部分的にCu−Ag(もしくはAg)膜14aに変換する工程は、置換めっき法により行っているが、Cu−Ag(もしくはAg)膜14a、つまりAgを含む膜に変換できれば特にそのような方法に限定されるものではない。置換めっき法を使用した場合には、置換する金属に対し、置換される金属(Cu、Bi等)が電気化学的に卑である必要があるが、他の方法を適用した場合には、そのような制限はなくなり、金属種の選択の自由度を増大させることができる。
本発明は、以上説明した実施の形態の記載内容に限定されるものではなく、構造や材質、各部材の配置等は、本発明の要旨を逸脱しない範囲で適宜変更可能である。
第1の実施の形態に係る電子部品の製造方法の工程を示す断面図である。 第1の実施の形態との対比としてアンダーカットが発生した例を示す断面図である。
符号の説明
11…基板、12…UBM層、13…Ti膜、14…Cu膜、14a…Cu−Ag(もしくはAg)膜14a、15…レジスト膜、15a…開口、16…Ag膜、17…Sn膜、18…アンダーカット、19…半田バンプ。

Claims (4)

  1. 基板上に半田バンプを形成する電子部品の製造方法であって、
    前記基板上に第1の金属からなる膜を形成する工程(A)と、
    置換めっきにより、前記第1の金属からなる膜を部分的に、前記第1の金属よりの金属である第2の金属を含む膜に変換する工程(B)と、
    前記第2の金属を含む膜上に、第3の金属からなる膜を形成する工程(C)と、
    前記第3の金属からなる膜をマスクとして前記第2の金属を含む膜以外の第1の金属からなる膜をウエットエッチングにより除去する工程(D)と
    を具備することを特徴とする電子部品の製造方法。
  2. 前記第1の金属は、Cu、Ag及びBiから選ばれる1種であり、前記第2の金属は、AgまたはAuであることを特徴とする請求項1記載の電子部品の製造方法。
  3. 前記工程(D)の後、前記第3の金属からなる膜及び前記第2の金属を含む膜にリフロー処理を施すことを特徴とする請求項1または2記載の電子部品の製造方法。
  4. 前記工程(B)の後、前記工程(C)に先立って、前記第2の金属を含む膜に熱処理を施して、前記第2の金属を含む膜内の第1の金属と第2の金属を合金化または化合物化することを特徴とする請求項1乃至3のいずれか1項記載の電子部品の製造方法。
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Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2405469B1 (en) * 2010-07-05 2016-09-21 ATOTECH Deutschland GmbH Method to form solder alloy deposits on substrates
TWI541964B (zh) * 2010-11-23 2016-07-11 矽品精密工業股份有限公司 半導體基板之製法
US8298930B2 (en) 2010-12-03 2012-10-30 International Business Machines Corporation Undercut-repair of barrier layer metallurgy for solder bumps and methods thereof
JP5659821B2 (ja) * 2011-01-26 2015-01-28 三菱マテリアル株式会社 Sn合金バンプの製造方法
TWI430377B (zh) * 2011-08-09 2014-03-11 Univ Nat Chiao Tung 用於減緩介金屬化合物成長之方法
US9142520B2 (en) 2011-08-30 2015-09-22 Ati Technologies Ulc Methods of fabricating semiconductor chip solder structures
CN103579149B (zh) * 2012-08-01 2016-08-03 颀邦科技股份有限公司 半导体结构及其制造工艺
KR102258660B1 (ko) 2013-09-17 2021-06-02 삼성전자주식회사 구리를 함유하는 금속의 식각에 사용되는 액체 조성물 및 이를 이용한 반도체 장치의 제조 방법
KR101778498B1 (ko) 2014-10-10 2017-09-13 이시하라 케미칼 가부시키가이샤 합금 범프의 제조방법
JP6571446B2 (ja) * 2015-08-11 2019-09-04 ローム株式会社 半導体装置

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5256597A (en) * 1992-09-04 1993-10-26 International Business Machines Corporation Self-aligned conducting etch stop for interconnect patterning
KR100219806B1 (ko) * 1997-05-27 1999-09-01 윤종용 반도체장치의 플립 칩 실장형 솔더 범프의 제조방법, 이에 따라 제조되는 솔더범프 및 그 분석방법
US5937320A (en) * 1998-04-08 1999-08-10 International Business Machines Corporation Barrier layers for electroplated SnPb eutectic solder joints
JP4237325B2 (ja) * 1999-03-11 2009-03-11 株式会社東芝 半導体素子およびその製造方法
US6638847B1 (en) * 2000-04-19 2003-10-28 Advanced Interconnect Technology Ltd. Method of forming lead-free bump interconnections
US7547623B2 (en) * 2002-06-25 2009-06-16 Unitive International Limited Methods of forming lead free solder bumps
JP2004207685A (ja) * 2002-12-23 2004-07-22 Samsung Electronics Co Ltd 無鉛ソルダバンプの製造方法
US7427557B2 (en) * 2004-03-10 2008-09-23 Unitive International Limited Methods of forming bumps using barrier layers as etch masks
US7410833B2 (en) * 2004-03-31 2008-08-12 International Business Machines Corporation Interconnections for flip-chip using lead-free solders and having reaction barrier layers
JP4843229B2 (ja) * 2005-02-23 2011-12-21 株式会社東芝 半導体装置の製造方法
US7713859B2 (en) * 2005-08-15 2010-05-11 Enthone Inc. Tin-silver solder bumping in electronics manufacture
US7456090B2 (en) * 2006-12-29 2008-11-25 Taiwan Semiconductor Manufacturing Co., Ltd. Method to reduce UBM undercut

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