TWI579937B - 基板結構及其製法暨導電結構 - Google Patents

基板結構及其製法暨導電結構 Download PDF

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TWI579937B
TWI579937B TW104117740A TW104117740A TWI579937B TW I579937 B TWI579937 B TW I579937B TW 104117740 A TW104117740 A TW 104117740A TW 104117740 A TW104117740 A TW 104117740A TW I579937 B TWI579937 B TW I579937B
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conductive
layer
insulating layer
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pillar
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TW201643973A (zh
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林欣達
蔣靜雯
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矽品精密工業股份有限公司
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Priority to CN201510321455.8A priority patent/CN106298710B/zh
Priority to US14/981,549 priority patent/US9899344B2/en
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Description

基板結構及其製法暨導電結構
本發明係有關一種基板結構，尤指一種具導電凸塊之基板結構。
傳統覆晶式(flip chip)半導體封裝技術主要係於晶片之電性接觸墊上形成銲料凸塊(solder bump)，再透過該銲料凸塊直接與封裝基板電性連接，相較於打線(wire bonding)方式而言，覆晶技術的電路路徑較短，具有較佳的電性品質，同時因可設計為晶背裸露形式，亦可提高晶片散熱性。
如第1圖所示之覆晶技術之局部示意圖，係於晶片10之絕緣層11(由第一絕緣層11a與第二絕緣層11b所組成)上形成外露電性接觸墊100之開孔，再於該絕緣層11上與該開孔中形成黏附層12、潤濕層13與保護層14，並於該電性接觸墊100上方形成銲料凸塊16，最後蝕刻移除未被該銲料凸塊16所覆蓋之黏附層12、潤濕層13與保護層14，以於該銲料凸塊16底下定義出凸塊底下金屬層(Under Bump Metallurgy，簡稱UBM)15，使該銲料凸塊16牢固 接於該電性接觸墊100上。
上述中，該黏附層12之材質係為鈦(Ti)、鉻(Cr)或鈦鎢(TiW)，以提供該電性接觸墊100與該潤濕層13間有較強之黏著性。該潤濕層13之材質係為鎳(Ni)或銅(Cu)，其與銲錫之潤濕程度較高，故於回銲該銲料凸塊16時，該銲料凸塊16可完全附著且呈球狀。該保護層14之材質係為如金、銅等之低電阻金屬，其可保護該銲料凸塊16及降低電阻值。
惟，隨者晶片10之微小化的發展，各該電性接觸墊100之間的距離愈小，致使習知覆晶製程無法配合，導致相鄰兩銲料凸塊16容易橋接，故需有更新更進步的封裝技術以供更微小的晶片10之使用。
因此，如何克服上述習知技術之橋接問題，實已成目前亟欲解決的課題。
鑑於上述習知技術之缺失，本發明係提供一種基板結構，係包括：基板本體，係具有複數電性接觸墊；絕緣層，係形成於該基板本體上，並令該些電性接觸墊顯露於該絕緣層；至少一導電通孔，係形成於該絕緣層中並電性連接該電性接觸墊；線路層，係具有複數線路並係形成於該絕緣層中及該導電通孔上，其中，該線路層之各線路之寬度大於該導電通孔之寬度；以及導電柱，係形成於該絕緣層上並設於該線路層上，其中，該導電柱之寬度大於或等於該線路層之寬度，且該導電通孔、線路層及導電柱係為一 體成形者。
本發明復提供一種基板結構之製法，係包括：提供具有複數電性接觸墊之基板本體；形成絕緣層於該基板本體上；於該絕緣層中形成貫穿其中之複數通孔，以令各該電性接觸墊外露於各該通孔；形成未貫穿該絕緣層之複數溝槽，且該些溝槽連通該些通孔；以及形成導電材於該些通孔與該些溝槽中及該絕緣層上，以於該些通孔中形成電性連接該電性接觸墊之導電通孔，且於該些溝槽中形成電性連接該導電通孔之線路層，並於該絕緣層上形成電性連接該線路層之導電柱，使該導電通孔、線路層及導電柱係為一體成形者。
前述之製法中，形成該導電材之方法係為電鍍、化鍍、濺鍍、蒸鍍或無電鍍。
前述之基板結構及其製法中，形成該基板本體之材質係為矽、陶瓷或有機材質。
本發明亦提供一種導電結構，係與一絕緣層結合，該導電結構係包括：導電通孔，係形成於該絕緣層中；線路層，係形成於該絕緣層中並設於該導電通孔上，其中，該線路層之寬度大於該導電通孔之寬度；以及導電柱，係形成於該絕緣層上並設於該線路層上，其中，該導電柱之寬度大於或等於該線路層之寬度，且該導電通孔、線路層及導電柱係為一體成形者。
前述之基板結構及其製法暨導電結構中，該導電材(或該導電通孔、線路層及導電柱之材質)係為銅材或金 材。
前述之基板結構及其製法暨導電結構中，該導電柱之寬度係小於20微米。
另外，前述之基板結構及其製法暨導電結構中，復包括形成於該導電柱上之導電元件。
由上可知，本發明之基板結構及其製法暨導電結構中，主要藉由導電材一次形成於該些通孔與該些溝槽中，使該導電通孔、線路層及導電柱係為一體成形者，以供超微小晶片或細間距(fine pitch)之電性接觸墊進行覆晶電性連接。
10‧‧‧晶片
100,200‧‧‧電性接觸墊
11,21‧‧‧絕緣層
11a‧‧‧第一絕緣層
11b‧‧‧第二絕緣層
12‧‧‧黏附層
13‧‧‧潤濕層
14‧‧‧保護層
15‧‧‧凸塊底下金屬層
16‧‧‧銲料凸塊
2‧‧‧基板結構
2’‧‧‧導電結構
20‧‧‧基板本體
21a‧‧‧第一子層
21b‧‧‧第二子層
210‧‧‧氮化矽層
211‧‧‧氧化層
22‧‧‧導電通孔
220‧‧‧通孔
23‧‧‧線路層
230‧‧‧溝槽
24‧‧‧阻障層
25‧‧‧阻層
250‧‧‧開口
26‧‧‧導電柱
27‧‧‧導電材
28‧‧‧導電元件
d,r,w‧‧‧寬度
第1圖係為習知具有銲料凸塊的基板結構之剖視圖；以及 第2A至2H圖係為本發明之基板結構之製法之剖視示意圖。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功 效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”、“第一”、“第二”及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
第2A至2H圖係為本發明之基板結構2之製法之剖視示意圖。
如第2A圖所示，提供一具有複數電性接觸墊200之基板本體20。於本實施例中，形成該基板本體20之材質係為矽，但於其它實施例中，形成該基板本體20之材質可為陶瓷或有機材質。
如第2B圖所示，形成一絕緣層21於該基板本體20上，且該絕緣層21係分為接觸該基板本體20之第一子層21a與形成於該第一子層21a上之第二子層21b。
於本實施例中，該第一子層21a與該第二子層21b均由氮化矽層210與氧化層211所組成。
如第2C圖所示，形成貫穿該第一與第二子層21a,21b之複數通孔220，以令各該電性接觸墊200外露於各該通孔220。於本實施例中，藉由蝕刻方式形成該些通孔220。
如第2D圖所示，形成複數溝槽230於該絕緣層21之第二子層21b上，且該些溝槽230連通該些通孔220。於本實施例中，藉由蝕刻方式形成該些溝槽230。
如第2E圖所示，形成阻障層24於該第二子層21b、 溝槽230之壁面、通孔220之壁面及電性接觸墊200上，再形成一阻層25於該阻障層24上，且該阻層25形成有複數開口250，以令單一開口250暴露複數該通孔220及其周圍之表面。
於本實施例中，形成該阻障層24之材質係為氮化鉭(TaN)或氮化鈦(TiN)，且該阻層25係為乾膜(dry film)。
如第2F圖所示，形成導電材27於該些通孔220、該些溝槽230、及該開口250中，以於該些通孔220中形成電性連接該電性接觸墊200之導電通孔22，且於該些溝槽230中形成電性連接該導電通孔22之線路層23，並於該些開口250中形成凸出該些溝槽230及電性連接該線路層23之導電柱26，使該導電通孔22、線路層23及導電柱26為一體成形，其中，單一該導電柱26覆蓋複數該導電通孔22。
於本實施例中，該導電材27係為銅材或金材，且形成該導電材27之方法係為電鍍、化鍍、濺鍍、蒸鍍或無電鍍。
如第2G圖所示，移除該阻層25及其下之阻障層24。於本實施例中，該導電柱26之寬度w係小於20微米。
如第2H圖所示，形成導電元件28於該導電柱26上。於本實施例中，該導電元件28係含有銲錫材料。
本發明復提供一種基板結構2，係包括：一基板本體20、一形成於該基板本體20上之絕緣層21以及與該絕緣層21結合之導電結構2’。
所述之基板本體20係具有複數電性接觸墊200，且形 成該基板本體20之材質係為矽、陶瓷或有機材質。
所述之導電結構2’係至少包括：至少一導電通孔22、一線路層23以及一導電柱26。
所述之導電通孔22係形成於該絕緣層21中並電性連接該電性接觸墊200。
所述之線路層23係形成於該絕緣層21中並設於該導電通孔22上以電性連接該導電通孔22，其中，該線路層23之寬度d大於該導電通孔22之寬度r。
所述之導電柱26係形成於該絕緣層21上並設於該線路層23上且覆蓋至少一該導電通孔22，其中，該導電柱26之寬度w大於或等於該線路層23之寬度d，且該導電通孔22、線路層23及導電柱26係為一體成形者。
於一實施例中，該導電材27(或該導電通孔22、線路層23及導電柱26之材質)係為銅材或金材。
於一實施例中，該導電柱26之寬度w係小於20微米。
於一實施例中，該基板結構2(或該導電結構2’)復包括形成於該導電柱26上之導電元件28。
綜上所述，本發明之基板結構及其製法暨導電結構，係藉由導電材27一次形成於該些通孔220與該些溝槽230中及該絕緣層21上，使該導電通孔22、線路層23及導電柱26係為一體成形者，以令該導電柱26之寬度w係小於20微米，俾供超微小晶片或細間距之電性接觸墊進行覆晶電性連接。
上述實施例係用以例示性說明本發明之原理及其功 效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
2‧‧‧基板結構
20‧‧‧基板本體
200‧‧‧電性接觸墊
21‧‧‧絕緣層
22‧‧‧導電通孔
23‧‧‧線路層
26‧‧‧導電柱
27‧‧‧導電材
d,r,w‧‧‧寬度

Claims (15)

  1. 一種基板結構，係包括：基板本體，係具有複數電性接觸墊；絕緣層，係形成於該基板本體上，並令該些電性接觸墊顯露於該絕緣層；複數導電通孔，係形成於該絕緣層中並電性連接該電性接觸墊；線路層，係具有複數線路並係形成於該絕緣層中及該導電通孔上，其中，該線路層之各線路之寬度大於該導電通孔之寬度；以及導電柱，係形成於該絕緣層上並設於該線路層上，其中，該導電柱之寬度大於或等於該線路層之寬度，且該導電通孔、線路層及導電柱係為一體成形者。
  2. 如申請專利範圍第1項所述之基板結構，其中，形成該基板本體之材質係為矽、陶瓷或有機材質。
  3. 如申請專利範圍第1項所述之基板結構，其中，該導電通孔、線路層及導電柱之材質係為銅材或金材。
  4. 如申請專利範圍第1項所述之基板結構，其中，該導電柱之寬度係小於20微米。
  5. 如申請專利範圍第1項所述之基板結構，復包括形成於該導電柱上之導電元件。
  6. 一種基板結構之製法，係包括：提供具有複數電性接觸墊之基板本體；形成絕緣層於該基板本體上； 於該絕緣層中形成貫穿其中之複數通孔，以令各該電性接觸墊外露於各該通孔；形成未貫穿該絕緣層之複數溝槽，且該些溝槽連通該些通孔；以及形成導電材於該些通孔與該些溝槽中及該絕緣層上，以於該些通孔中形成電性連接該電性接觸墊之導電通孔，且於該些溝槽中形成電性連接該導電通孔之線路層，並於該絕緣層上形成電性連接該線路層之導電柱，使該導電通孔、線路層及導電柱係為一體成形者。
  7. 如申請專利範圍第6項所述之基板結構之製法，其中，形成該基板本體之材質係為矽、陶瓷或有機材質。
  8. 如申請專利範圍第6項所述之基板結構之製法，其中，該導電材係為銅材或金材。
  9. 如申請專利範圍第6項所述之基板結構之製法，其中，形成該導電材之方法係為電鍍、化鍍、濺鍍、蒸鍍或無電鍍。
  10. 如申請專利範圍第6項所述之基板結構之製法，其中，該導電柱之寬度係小於20微米。
  11. 如申請專利範圍第6項所述之基板結構之製法，復包括形成導電元件於該導電柱上。
  12. 一種導電結構，係與一絕緣層結合，該導電結構係包括：導電通孔，係形成於該絕緣層中； 線路層，係形成於該絕緣層中並設於該導電通孔上，其中，該線路層之寬度大於該導電通孔之寬度；以及導電柱，係形成於該絕緣層上並設於該線路層上，其中，該導電柱之寬度大於或等於該線路層之寬度，且該導電通孔、線路層及導電柱係為一體成形者。
  13. 如申請專利範圍第12項所述之導電結構，其中，該導電通孔、線路層及導電柱之材質係為銅材或金材。
  14. 如申請專利範圍第12項所述之導電結構，其中，該導電柱之寬度係小於20微米。
  15. 如申請專利範圍第12項所述之導電結構，復包括形成於該導電柱上之導電元件。
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