200924583 丨twf.doc/p 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種線路板（circujt board )，且特別 疋有關於一種具有導電凸塊（c〇nductiVe bump)的線路板 以及此導電凸塊的製造方法。 【先前技術】200924583 丨twf.doc/p IX. Description of the Invention: [Technical Field] The present invention relates to a circuit board (circujt board), and particularly to a circuit having a conductive bump (c〇nductiVe bump) A board and a method of manufacturing the conductive bump. [Prior Art]
現今許夕豕電用品以及電子裝置（electr〇nic apparatus)都需要配備電阻、電容、電感、晶片（chip) 與晶片封裝體（chip package)等電子元件，而這些電子元 件必須要與線路板組裝才能運作。 圖1疋習知線路板的剖面示意圖。請參閱圖i，線路 板卿通常具有-銅線路層11〇、一防焊層12〇以及多個 焊料塊130,其中銅線路層11〇包括多個焊塾ιΐ2 (圖i ^會示—個焊塾112與—個焊料塊130)與多條走線(trace) 層120覆蓋銅線路層110，並具有局部暴露這 些知墊112的開口 H1。 別配130的材質通常是谭錫’而這些焊料塊130 ' ^己，於运些開口 m内’並連接這些焊整112。這也取 免130能連接上述電子元件，進而使電子元件與 板100組褒。如此，這些電子元件得以運作。… 然知的祕板⑽卻具有細存在的^ 塊130受到其材質特性的加工性影響，例如力 ϋ塊130的内聚力與表面張力等物理特性，扣 斗塾1的表面，即凝固後的焊料塊测 200924583 5twf.doc/p 局部接觸焊墊112的表面（如圖1中，虛線圍繞的地方）。 這會造成焊料塊130與焊墊112之間的接觸面積有限，以 致於二者之間的附著力不足，導致焊料塊13〇容易自焊塾 112脫洛’進而降低線路板1〇〇的產品彳g賴度（reiiability )。 【發明内容】 本發明提供一種導電凸塊的製造方法，以增加線路板 與電子元件之間的附著力。 本發明提供一種線路板，其導電凸塊與電子元件之間 具有較大的附著力。 本發明提供一種導電凸塊的製造方法。首先，提供一 線路基板，其包括一絕緣層、一線路層以及一第一防鍍層， 其中線路層與第一防鍍層配置於絕緣層上。線路層包括至 少一接墊，而第一防鍍層暴露接墊。接著，形成一第二防 鍍層，其中第二防鍍層覆蓋第一防鍍層與線路層，且第二 防鍍層具有至少一暴露接墊的開口。接著，形成一導電凸 塊於此開口内，其中導電凸塊連接接墊。 在本發明之一實施例中，上述形成導電凸塊的方法包 括電鍍法或填入導電膠。 在本發明之—實施例中，上述導電凸塊的製造方法更 2 ’移除第一防錢層與第二防鏡層。接著，形成-保護 ^層’其巾賴材料層全面性地覆蓋線路層、絕緣層以 料Ϊ電凸塊。接著，移除位於導電凸塊上方的部分保護材 霞:、1以形成—圖案化紐層，其巾圖案化賴層完全暴 V電凸塊的一頂面，且此頂面與保護層的表面實質上 200924583 < w (w»jtwf.doc/p 切齊。Nowadays, the electrical appliances and electronic devices (electr〇nic apparatus) need to be equipped with electronic components such as resistors, capacitors, inductors, chips and chip packages. These electronic components must be assembled with the circuit board. To be able to operate. Figure 1 is a schematic cross-sectional view of a conventional circuit board. Referring to FIG. 1, the circuit board usually has a copper circuit layer 11A, a solder mask layer 12A, and a plurality of solder bumps 130, wherein the copper circuit layer 11 includes a plurality of solder pads ιΐ2 (Fig. The solder bumps 112 and the solder bumps 130 and the plurality of trace layers 120 cover the copper wiring layer 110 and have openings H1 that partially expose the pads 112. The material of the 130 is usually Tanxi' and these solder bumps 130' are inside the openings m and are connected to the soldering 112. This also allows 130 to connect the above electronic components, thereby causing the electronic components to be assembled with the board 100. As such, these electronic components operate. However, the secret board (10) has a fine presence. The block 130 is affected by the workability of its material properties, such as the physical properties such as the cohesion and surface tension of the force block 130, and the surface of the buckle 1 is the solidified solder. Block test 200924583 5twf.doc / p The surface of the local contact pad 112 (as shown in Figure 1, surrounded by a dotted line). This causes the contact area between the solder bumps 130 and the pads 112 to be limited, so that the adhesion between the solder bumps is insufficient, resulting in the solder bumps 13 being easily detached from the solder bumps 112, thereby reducing the product of the wiring board 1〇〇. g reiability. SUMMARY OF THE INVENTION The present invention provides a method of manufacturing a conductive bump to increase the adhesion between the wiring board and the electronic component. The present invention provides a wiring board having a large adhesion between a conductive bump and an electronic component. The present invention provides a method of manufacturing a conductive bump. First, a circuit substrate is provided, comprising an insulating layer, a wiring layer and a first plating resist, wherein the wiring layer and the first plating resist are disposed on the insulating layer. The circuit layer includes at least one pad and the first plating layer exposes the pads. Next, a second plating resist is formed, wherein the second plating resist covers the first plating resist and the wiring layer, and the second plating resist has at least one opening that exposes the pads. Next, a conductive bump is formed in the opening, wherein the conductive bump is connected to the pad. In an embodiment of the invention, the above method of forming the conductive bumps comprises electroplating or filling with a conductive paste. In an embodiment of the invention, the method of fabricating the conductive bumps further removes the first anti-money layer and the second anti-mirror layer. Next, a layer of the protective layer is formed, and the layer of the material of the towel is integrally covered with the wiring layer and the insulating layer to form the electric bump. Then, a part of the protective material located above the conductive bump is removed: 1 to form a patterned layer, and the towel patterning layer completely ruptures a top surface of the V-electrode bump, and the top surface and the protective layer are The surface is essentially 200924583 < w (w»jtwf.doc/p.
在本發明之-實施例中，上述導電凸塊更具有— 電凸塊的頂©之邊緣的側面’而保護層覆蓋此側面。 在本發明之-實施例中，上述移除位於導電凸塊 複部分保護材料層的方法包括對保護材料層進行研磨製 林發歡—實施射，上職護層為-防焊層。 5 纟本發明之-實關巾，上述導電凸塊的製造方法在 彬成保護層之後’更包括對導電凸塊進行一表面處理製程。 在本發明之一實施例中，上述表面處理製程包括形成 少一抗氧化層，而抗氧化層位於導電凸塊的頂面上。 蘇本發明另提供一種線路板，其包括一絕緣層、—線路 ^、一保護層以及至少一導電凸塊。線路層配置於絕緣層 ，並包括至少一接墊。保護層覆蓋線路層與絕緣層，其 、保護層具有至少一開口。導電凸塊配置於此開口内，並 ^ 、接接墊，其中導電凸塊具有一頂面。此頂面與保護層的 表面實質上切齊’而保護層的開口完全暴露頂面。 在本發明之一實施例中’上述導電凸塊更具有—連接 項面之邊緣的側面，而保護層更覆蓋側面。 在本發明之一實施例中，上述保護層為一防焊層。 ^ 在本發明之一實施例中，上述線路板更包括至少一抗 氣化層，而抗氡化層位於導電凸塊的頂面上。 本發明利用二層防鍍層（即第一防鍍層與第二防鍍 層）來製造導電凸塊，且所製成的導電凸塊，其頂面可從 200924583 ' …-」twf.d〇c/p 保濩層完全暴露出來。如此，導電凸塊的頂面能與焊料塊 充刀接觸’以致於電子元件不易與線路板脫離，進而增加 線路板的產品信賴度。 為讓本發明之上述特徵和優點能更明顯易懂，下文特 舉些實施例，並配合所附圖式，作詳細說明如下。 【實施方式】 圖2A至圖2G是本發明一實施例之導電凸塊的製造 f) 方法之流程的剖面示意圖。必須事先說明的是，圖2A至 圖所揭露的導電凸塊的製造方法僅供用來作為舉例說 明’以使本發明所屬技術領域中具有通常知識者能具體實 施而為之。因此，在此強調，本發明的範疇並不僅限定圖 2A至圖2G所揭露的導電凸塊的製造方法’而且還包括其 他未繪示的實施例。 請參閱圖2A，首先，提供一線路基板200，線路基板 2〇〇包括一絕緣層210、一線路層220a以及一第一防鍍層 230a，其中線路層220a與第一防鍍層230a配置於絕緣層 ^ 210上。線路層220a包括至少一接墊222以及多條走線 224，而第一防鍍層230a暴露接墊222與這些走線224。 另外，第一防鍍層230a可以是乾膜（dry film)或是由其 他適當材料所製成。 圖2A至圖2H雖然僅繪示一個接墊222,但在其他未 繪示的實施例中，線路層220a亦可以包括多個接墊222， 故圖2A至圖2H所示的接墊222之數目並非用來限定本發 明。 200924583 _ — . _ itwf.doc/p 在本實施例中，線路基板200更可以包括一線路層 220b以及至少一導電盲孔結構（conductive via structure ) 240，其中線路層220a能藉由導電盲孔結構240而電性連 接線路層220b。 由此可知，線路基板200本質上可算是一種線路板， 其例如是單面線路板（single side circuit board )、雙面線 路板（double side circuit board )或是多層線路板 (multi-layer circuit board)。雖然圖2A所示的線路基板 200可算是一種多層線路板，然而圖2A所示的線路基板 200僅是舉例說明，並非限定本發明。 請參閱圖2B，接著，形成一第二防鍍層230b，其中 第二防鑛層230b覆蓋第一防鏡層230a與線路層220a，且 第二防鏡層230b與第一防鑛層230a的材質可以相同。第 二防鍍層230b具有至少一暴露接墊222的開口 H2，而開 口 H2可以局部暴露接墊222的表面222a，如圖2B所示。 當然，端視產品不同的設計與需求，開口 H2亦可以完全 暴露出接墊222。此外，形成第二防鍍層23〇b的方法可以 是微影與蝕刻製程或是其他適當的方法。 请參閱圖2C，之後，形成一導電凸塊25〇於開口 H2 内其中‘電凸塊250連接接塾222。如此，導電凸塊250 能電性連接對應的接墊222。在本實施例中，形成導電凸 塊250的方法包括紐法或填人導轉。關於此電鍛法， 可以直接對線路層220a進行電錄，以在接墊222的表面 222a上沉積導電材料’而導電膠可以是銅κ膏、銀膠 200924583 6twf.doc/p 或其他能直接填入開口 H2内的導電材料。 如此，導電凸塊250得以形成。另外，導電凸塊250 具有一頂面252a以及一側面252b，其中頂面252a的邊緣 連接側面252b。 請參閱圖2C與圖2D ’之後，移除第一防鍍層230a 與第二防鍍層230b ’以使線路層220a裸露出來。此外， 第一防鐘層230a與第二防鍍層230b可以採用化學藥劑來 移除。 請參閱圖2E，接著，形成一保護材料層26〇，其中保 護材料層260全面性地覆蓋線路層220a、絕緣層210以及 導電凸塊250,即導電凸塊250的頂面252a與接墊222皆 被保護材料層260所覆蓋。保護材料層260可以藉由塗佈 液態的絕緣材料而形成，而保護材料層260的材質可以是 防焊材料，例如防焊漆或防焊乾膜。 請參閱2E與圖2F，接著，移除位於導電凸塊25〇上 方的部分保護材料層260，以形成一圖案化保護層26〇,。 圖案化保護層260’會完全暴露出導電凸塊250的頂面 252a。詳細而言，圖案化保護層26〇,覆蓋線路層22〇a與絕 緣層210,並具有至少一開口 H3。導電凸塊25〇位於開口 H3内，且開口 H3完全暴露導電凸塊25()的頂面252a。 圖案化保護層260,可以是一種防焊層（s〇ldermask)。 另外，在圖案化保護層260,形成之後，基本上一種包括絕 緣層210、線路層220a、圖案化保護層260,以及導電凸塊 25〇的線路板300已製造完成。 10 200924583In an embodiment of the invention, the conductive bumps further have a side ” of the edge of the top of the electrical bump and the protective layer covers the side. In an embodiment of the invention, the method of removing the layer of the protective portion of the conductive bump includes removing the layer of protective material from the forest to the surface, and the upper layer is a solder mask. In the case of the present invention, the method for manufacturing the conductive bumps is followed by a surface treatment process for the conductive bumps. In one embodiment of the invention, the surface treatment process includes forming a lesser anti-oxidation layer on the top surface of the conductive bump. The invention further provides a wiring board comprising an insulating layer, a wiring, a protective layer and at least one conductive bump. The circuit layer is disposed on the insulating layer and includes at least one pad. The protective layer covers the circuit layer and the insulating layer, and the protective layer has at least one opening. The conductive bump is disposed in the opening, and is connected to the pad, wherein the conductive bump has a top surface. This top surface is substantially in line with the surface of the protective layer' and the opening of the protective layer completely exposes the top surface. In one embodiment of the invention, the conductive bumps described above have a side that connects the edges of the face, and the protective layer covers the sides. In an embodiment of the invention, the protective layer is a solder resist layer. In an embodiment of the invention, the circuit board further includes at least one anti-gasification layer, and the anti-deuteration layer is located on a top surface of the conductive bump. The invention utilizes a two-layer anti-plating layer (ie, a first anti-plating layer and a second anti-plating layer) to manufacture conductive bumps, and the conductive bumps are formed, and the top surface thereof can be from 200924583 '...-" twf.d〇c/ p The protective layer is completely exposed. Thus, the top surface of the conductive bump can be in contact with the solder bump so that the electronic component is not easily detached from the wiring board, thereby increasing the reliability of the circuit board. The above described features and advantages of the present invention will be more apparent from the following description. [Embodiment] Figs. 2A to 2G are schematic cross-sectional views showing the flow of a method of manufacturing a conductive bump according to an embodiment of the present invention. It must be noted in advance that the method of fabricating the conductive bumps disclosed in Figures 2A to Figure 1 is for illustrative purposes only, and may be embodied by those of ordinary skill in the art to which the invention pertains. Accordingly, it is emphasized herein that the scope of the present invention is not limited to the method of manufacturing the conductive bumps disclosed in Figures 2A through 2G, but also includes other embodiments not shown. Referring to FIG. 2A, first, a circuit substrate 200 is provided. The circuit substrate 2 includes an insulating layer 210, a wiring layer 220a, and a first plating resist 230a. The wiring layer 220a and the first plating resist 230a are disposed on the insulating layer. ^ 210 on. The circuit layer 220a includes at least one pad 222 and a plurality of traces 224, and the first plating resist 230a exposes the pads 222 and the traces 224. Alternatively, the first plating resist 230a may be a dry film or may be made of other suitable materials. 2A to 2H, although only one pad 222 is shown, in other embodiments not shown, the circuit layer 220a may also include a plurality of pads 222, so that the pads 222 shown in FIGS. 2A to 2H The number is not intended to limit the invention. In this embodiment, the circuit substrate 200 further includes a circuit layer 220b and at least one conductive via structure 240, wherein the circuit layer 220a can pass through the conductive blind hole. The structure 240 is electrically connected to the wiring layer 220b. It can be seen that the circuit substrate 200 can be regarded as a circuit board in nature, for example, a single side circuit board, a double side circuit board or a multi-layer circuit board. ). Although the circuit substrate 200 shown in FIG. 2A can be regarded as a multilayer wiring board, the circuit substrate 200 shown in FIG. 2A is merely illustrative and does not limit the present invention. Referring to FIG. 2B, a second anti-plating layer 230b is formed, wherein the second anti-mine layer 230b covers the first anti-mirror layer 230a and the circuit layer 220a, and the second anti-mirror layer 230b and the material of the first anti-mine layer 230a. Can be the same. The second plating resist 230b has at least one opening H2 exposing the pads 222, and the opening H2 can partially expose the surface 222a of the pads 222, as shown in Fig. 2B. Of course, depending on the design and requirements of the product, the opening H2 can also completely expose the pad 222. Further, the method of forming the second plating resist 23b may be a lithography and etching process or other suitable method. Referring to FIG. 2C, a conductive bump 25 is formed in the opening H2, wherein the electric bump 250 is connected to the interface 222. As such, the conductive bumps 250 can be electrically connected to the corresponding pads 222. In the present embodiment, the method of forming the conductive bumps 250 includes a new method or a filling guide. With regard to this electric forging method, the circuit layer 220a can be directly electrically recorded to deposit a conductive material on the surface 222a of the pad 222. The conductive paste can be copper κ cream, silver paste 200924583 6twf.doc/p or other directly The conductive material in the opening H2 is filled. As such, the conductive bumps 250 are formed. In addition, the conductive bump 250 has a top surface 252a and a side surface 252b, wherein the edge of the top surface 252a connects to the side surface 252b. Referring to FIG. 2C and FIG. 2D', the first plating resist 230a and the second plating resist 230b' are removed to expose the wiring layer 220a. Further, the first weather guard layer 230a and the second plating resist 230b may be removed using a chemical. Referring to FIG. 2E, a protective material layer 26 is formed, wherein the protective material layer 260 comprehensively covers the circuit layer 220a, the insulating layer 210, and the conductive bumps 250, that is, the top surface 252a and the pads 222 of the conductive bumps 250. Both are covered by a layer of protective material 260. The protective material layer 260 may be formed by coating a liquid insulating material, and the material of the protective material layer 260 may be a solder resist material such as a solder resist or a solder resist dry film. Referring to 2E and FIG. 2F, a portion of the protective material layer 260 located above the conductive bumps 25A is removed to form a patterned protective layer 26A. The patterned protective layer 260' will completely expose the top surface 252a of the conductive bumps 250. In detail, the patterned protective layer 26 is covered to cover the wiring layer 22a and the insulating layer 210, and has at least one opening H3. The conductive bump 25 is located within the opening H3, and the opening H3 completely exposes the top surface 252a of the conductive bump 25(). The patterned protective layer 260 can be a solder mask. In addition, after the patterned protective layer 260 is formed, substantially one of the wiring boards 300 including the insulating layer 210, the wiring layer 220a, the patterned protective layer 260, and the conductive bumps 25A has been completed. 10 200924583
Stwf.doc/p 移除位於導電凸塊250上方的部分保護材料層260的 方法有很多種’其中之一是對保護材料層260進行研磨製 程。如此’頂面252a會與圖案化保護層260,的表面262 貝質上切齊。此外’在本實施例中，圖案化保護層26〇，更 可以覆盍導電凸塊250的側面252b。Stwf.doc/p There are many ways to remove a portion of the protective material layer 260 over the conductive bumps 250, one of which is to grind the protective material layer 260. Thus, the top surface 252a will be flush with the surface 262 of the patterned protective layer 260. Further, in the present embodiment, the patterned protective layer 26 is further covered by the side surface 252b of the conductive bump 250.
C o 請參閱圖2G，在形成圖案化保護層26〇，之後，更可 以對^ ¾凸塊25〇進行一表面處理製程。透過此表面處理 製轾，‘電凸塊250的頂面252a能防止氧化，進而提高導 電凸塊250在電性連接方面的品質。在本實施例中，上述 表面處理製程可以包括形成一抗氧化層270於頂面252a C氧化層270是鎳金層、化學錫層、有機護銅 ^，疋由，、他適當的抗氧化材料所形成。 的是本實施例的線路板3GG可以應用在-3白〇〇 ^以二階以3上的封裝。也就是說，線路板 package) 二或疋用來組裝晶片封裝體（chip a上：辻且太？容、電感等電子元件的線路板。 造導電凸塊，而所製成的導雪 吸锻層木衣 全暴露出來。當導電心^，龙’/、頂面可從保護層完 焊料塊二二：料=τ ’以增加導靖 離，且線路板财得《增^件不易與線路板脫 雖然本發明已以實施 本發明，任何所屬版… '其並非用以限定 所屬技姻域中具有通常知識者，在不脫離 11 200924583 itwf.doc/p 本發明之精神和範圍内，當可作些許之更動與潤飾，因此 本發明之保護範圍當視後附之申請專利範圍所界定者為 準。 【圖式簡單說明】 圖1是習知線路板的剖面示意圖。 圖2A至圖2G是本發明一實施例之導電凸塊的製造 方法之流程的剖面示意圖。 【主要元件符號說明】 l i 100、300 :線路板 110 :銅線路層 112 :焊墊 114、224 :走線 120 :防焊層 130 :焊料塊 200 .線路基板 210 :絕緣層 〇 220a、220b :線路層 222 :接墊 222a、262 :表面 230a :第一防鍍層 230b:第二防鍍層 240 :導電盲孔結構 250 :導電凸塊 252a :頂面 12 itwf.doc/p 200924583 252b :側面 260 .保護材料層 260’ ：圖案化保護層 270 :抗氧化層 m、H2、H3 :開口C o Referring to Fig. 2G, after the patterned protective layer 26 is formed, a surface treatment process can be performed on the bumps 25A. Through the surface treatment, the top surface 252a of the electric bump 250 can prevent oxidation, thereby improving the quality of the conductive bump 250 in terms of electrical connection. In this embodiment, the surface treatment process may include forming an oxidation resistant layer 270 on the top surface 252a. The oxide layer 270 is a nickel gold layer, a chemical tin layer, an organic copper layer, and an appropriate oxidation resistant material. Formed. The circuit board 3GG of the present embodiment can be applied to a package of -3 white 〇〇^ in second order to 3. That is to say, the circuit board package) or 疋 is used to assemble the chip package (chip a: 太 and too, capacitance, inductance and other electronic components of the circuit board. Create conductive bumps, and the resulting snow guide forging The layer of wood clothing is fully exposed. When the conductive core ^, the dragon '/, the top surface can be completed from the protective layer of the solder block 22: material = τ ' to increase the guidance, and the circuit board is profitable. The present invention has been implemented in accordance with the present invention, and is not intended to limit the scope of the present invention, and does not depart from the spirit and scope of the present invention. The scope of protection of the present invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a schematic cross-sectional view of a conventional circuit board. Figure 2A to Figure 2G Is a schematic cross-sectional view showing the flow of a method for manufacturing a conductive bump according to an embodiment of the present invention. [Description of main component symbols] li 100, 300: circuit board 110: copper wiring layer 112: pads 114, 224: trace 120: Solder layer 130: solder bump 200. line base 210: insulating layer 〇 220a, 220b: circuit layer 222: pads 222a, 262: surface 230a: first plating layer 230b: second plating layer 240: conductive blind hole structure 250: conductive bump 252a: top surface 12 itwf. Doc/p 200924583 252b: side 260. Protective material layer 260': patterned protective layer 270: oxidation resistant layer m, H2, H3: opening