TWI599006B - 凸塊底層金屬化層結構及其形成方法和重佈金屬化層結構 - Google Patents

凸塊底層金屬化層結構及其形成方法和重佈金屬化層結構 Download PDF

Info

Publication number
TWI599006B
TWI599006B TW103127648A TW103127648A TWI599006B TW I599006 B TWI599006 B TW I599006B TW 103127648 A TW103127648 A TW 103127648A TW 103127648 A TW103127648 A TW 103127648A TW I599006 B TWI599006 B TW I599006B
Authority
TW
Taiwan
Prior art keywords
layer
redistribution
hole
metal
protective layer
Prior art date
Application number
TW103127648A
Other languages
English (en)
Other versions
TW201532218A (zh
Inventor
李智飛
張復誠
鄭志成
陳信吉
黃遠國
Original Assignee
台灣積體電路製造股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 台灣積體電路製造股份有限公司 filed Critical 台灣積體電路製造股份有限公司
Publication of TW201532218A publication Critical patent/TW201532218A/zh
Application granted granted Critical
Publication of TWI599006B publication Critical patent/TWI599006B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/64—Manufacture or treatment of solid state devices other than semiconductor devices, or of parts thereof, not peculiar to a single device provided for in groups H01L31/00 - H10K99/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/677—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
    • H01L21/67784—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations using air tracks
    • H01L21/67787—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations using air tracks with angular orientation of the workpieces
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3192—Multilayer coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H01L2224/02311—Additive methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H01L2224/02313—Subtractive methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H01L2224/02315—Self-assembly processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H01L2224/02331—Multilayer structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0235—Shape of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0236—Shape of the insulating layers therebetween
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02372—Disposition of the redistribution layers connecting to a via connection in the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02381—Side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0239—Material of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/036—Manufacturing methods by patterning a pre-deposited material
    • H01L2224/0361—Physical or chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/036—Manufacturing methods by patterning a pre-deposited material
    • H01L2224/03618—Manufacturing methods by patterning a pre-deposited material with selective exposure, development and removal of a photosensitive material, e.g. of a photosensitive conductive resin
    • H01L2224/0362—Photolithography
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/039—Methods of manufacturing bonding areas involving a specific sequence of method steps
    • H01L2224/0391—Forming a passivation layer after forming the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05005—Structure
    • H01L2224/05008—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05024—Disposition the internal layer being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05184—Tungsten [W] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05569—Disposition the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30101—Resistance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30105—Capacitance

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

凸塊底層金屬化層結構及其形成方法和重佈金屬化層結構
本發明是關於一凸塊，且特別是關於一凸塊底層金屬化層。
半導體工業在過去幾十年來最重要的趨勢是持續努力地改善元件性能，也因此需要不斷縮小半導體元件的特徵尺寸。在現今的半導體元件中，特徵尺寸通常已在深次微米的範圍。由於特徵尺寸的減小，次微米金屬內連線變得越來越重要。在理想情況下，一個金屬層應被均勻地沉積，且應以相同的金屬密度填滿金屬線的輪廓。然而，對於次微米金屬內連線的大小，經常會遇到的是不良的沉積金屬層階梯覆蓋率。此外，當為了解決RC延遲的問題而增加次微米金屬內連線的厚度時，階梯覆蓋率差的問題只會變得更嚴重。
根據一些實施例，本揭露提供了一個重佈金屬化的結構。重佈金屬化結構包括一個絕緣保護層，重佈通孔以及一個導電重佈層。重佈通孔暴露了一個設置在基板上的 底層金屬化層結構的方法。在基板上的金屬接合墊上形成一個第一保護層。在第一保護層中形成一個重佈通孔以暴露出金屬接合墊，且重佈通孔具有一圓形或相鄰邊之間的角度大於90°的一多邊形。在重佈通孔中和在第一保護層上形成第一金屬層。圖案化第一金屬層以形成重佈層。在重佈層上形成第二保護層。在第二保護層中形成末端通孔以暴露出一部分的重佈層。在末端通孔中和第二保護層上形成第二金屬層。將第二金屬層圖案化以形成凸塊底層金屬層。
100‧‧‧重佈通孔
110‧‧‧第一金屬層
110a‧‧‧重佈金屬層
120‧‧‧接縫處
125‧‧‧腐蝕區域
130‧‧‧金屬接合墊
140‧‧‧第一保護層
150‧‧‧第二保護層
200‧‧‧重佈通孔
210‧‧‧第一金屬層
230‧‧‧金屬接合墊
240‧‧‧第一保護層
250‧‧‧第二保護層
310~380‧‧‧步驟
400‧‧‧基板
410‧‧‧金屬接合墊
420‧‧‧第一保護層
425‧‧‧重佈通孔
430‧‧‧導電重佈層
440‧‧‧第二保護層
445‧‧‧末端通孔
450‧‧‧凸塊底層金屬層
本揭露的態樣在閱讀下述的詳細描述時結合附圖可以較佳理解。需要強調的是，根據業界標準實務，各種特徵並非按比例繪製。實際上，為了清楚討論起見，各種特徵的尺寸可任意放大或縮小。
第1A圖是一個金屬層沉積在傳統重佈通孔的俯視圖，其中已被金屬層部分地填充。
第1B圖是一個掃描式電子顯微鏡圖，其顯示在傳統重佈通孔中沉積金屬層後的剖視圖。
第2A圖是一個金屬層沉積在重佈通孔的俯視圖，根據本揭露的一些實施例，其中已被金屬層部分地填充。
第2B圖是一個掃描式電子顯微鏡圖，其顯示從頂部看具有八角形的重佈通孔中沉積金屬層後的剖視圖。
第3圖是，根據本揭露的一些實施例，形成凸塊底層金屬化層結構的流程圖。
第4A-4D圖是，根據本揭露的一些實施例，一個形成凸塊底層金屬化層結構的製程的剖視圖。
本揭露提供了許多不同的實施例，或例子，用於實施各種實施例不同的特徵。各特定實施例中的組成及配置將會在以下作描述以簡化本發明。這些為實施例並非用於限定本發明。舉例而言，一第一特徵形成於一第二特徵“上方”、“之上”、“之下”或“上”可包含實施例中的該第一特徵與第二特徵直接接觸，或也可包含該第一特徵與第二特徵之間更有其他額外特徵使該第一特徵與第二特徵無直接接觸。此外，在本說明書的各種例子中可能會出現重複的元件符號以便簡化描述。重複的元件符號是為了以便簡化描述，這不代表在各個實施例及/或圖示之間有何特定的關連。
另外，空間相對位置的術語，例如“在...之下”、“下方”、“向下”、“上方”、“向上”等，在此可被用於簡化說明以描述如圖所示的一個元件或部件與另外的元件或部件的關係。這些空間上相對的術語意在涵蓋除圖中所示方位以外的使用或操作器件的不同方位。該元件可以另行定位(旋轉90度或處於其他方位)並且在此使用的空間相對位置的描述詞可以同樣相應地解釋。
如上所述，由於現今半導體元件中的次微米金屬內連線變得越來越重要，RC延遲的問題可能會變得更重要。因此，增加次微米金屬內連線的厚度可能是解決日益嚴重 的RC延遲問題的一個方法。然而，當為了解決RC延遲的問題而增加次微米金屬內連線的厚度時，沉積的金屬層階梯覆蓋率差的問題只會變得更嚴重。凸塊底層金屬化層也會遇到上述的兩難問題。
現今的覆晶技術，用於重新定位積體電路(IC)的I/O接合墊的重佈金屬層具有更低的成本，更高密度，更大的靈活度和更高的性能等優點。然而，由於設計規則的限制，在覆蓋接合墊的保護層中的重佈通孔所佔的面積和相鄰重佈通孔的間距不能再增加了。因此，增加重佈金屬線的厚度以減少後續形成的重佈金屬層的RC延遲是唯一的選擇，且重佈通孔的縱橫比也因此提高了。
然而，當重佈金屬線的厚度和重佈通孔的直徑比例增加到至少1.4時，針孔故障是由沉積的金屬層階梯覆蓋率差所造成的。第1A圖是一個金屬層沉積在傳統重佈通孔的俯視圖，其中已被金屬層部分地填充。根據設計規則，傳統的重佈通孔100從頂部看具有正方形的形狀。重佈通孔100在第一保護層中形成(第1A圖中未示出)且覆蓋金屬接合墊(第1A圖中未示出)之後，開始於重佈通孔100中沉積一個第一金屬層110且覆蓋第一保護層。
在第1A圖中，重佈通孔100已被部分地填充，且可以看出，接縫處120幾乎是沿著重佈通孔100相鄰邊之間的對角線形成的。這是因為重佈通孔100邊的中央的金屬沉積速率比較快，且重佈通孔100角落的金屬沉積速率比較慢。除了上述的不均勻金屬沉積速率，重佈通孔100 相鄰邊之間的角度θ 1是小於或等於90°。重佈通孔100相鄰邊之間的角度越小會使其更容易在沉積於重佈通孔100中的第一金屬層110的上方部分產生接縫處120和產生外伸(在第1A圖中未示出)。這些接縫處120和外伸會造成之後形成的重佈金屬層產生針孔故障，因為之後用於圖案化第一金屬層110以形成重佈金屬層，圖案化覆蓋重佈金屬層的第二保護層，和圖案化形成於第二保護層中的末端通孔中的第二金屬層所用的酸蝕刻液將會透過這些接縫處120流入且腐蝕第一金屬層110。
此外，在第一金屬層110沉積於重佈通孔100的過程中，如果沉積於重佈通孔100中的第一金屬層110上方部分的外伸問題很嚴重的話，甚至可能會在位於重佈通孔100中的金屬層110形成空洞。空洞可能會累積酸蝕刻液使得腐蝕的問題更為嚴重且增加了重佈金屬層的RC延遲。
第1B圖是一個掃描式電子顯微鏡圖，其顯示在傳統重佈通孔中沉積金屬層後的剖視圖。第1B圖所示的掃描式電子顯微鏡圖係沿第1A圖之線段BB’的剖面。在第1B圖中，第一保護層140是沉積在一個金屬接合墊130上。在第一保護層140中形成一個重佈通孔100以暴露出金屬接合墊130。之後沉積一個第一金屬層110以填滿重佈通孔100並覆蓋第一保護層140。圖案化第一金屬層110以形成重佈金屬層110a之後，隨後沉積一個第二保護層150於重佈金屬層110a上。在第1B圖所示的掃描式電子顯微鏡圖中，可以清楚地看出一個沿著接縫處120所形成的嚴重U- 形腐蝕區域125。因此，IC晶片的產率嚴重降低。
有鑑於此，如何同時解決RC延遲的問題和針孔故障已成為一個棘手的問題。然而，後來終於發現，如果增大重佈通孔100相鄰邊之間的角度θ 1，可以解決針孔故障的問題，且可以同時保持小的RC延遲。
第2A圖是一個金屬層沉積在重佈通孔的俯視圖，根據本揭露的一些實施例，其中已被金屬層部分地填充。在第2A圖中，一個第一金屬層210是沉積在形成於覆蓋金屬接合墊的第一保護層(在第2A圖未示出)中的重佈通孔200中。重佈通孔200已被第一金屬層210部分地填充。在第2A圖中的重佈通孔200從頂部看具有八角形的形狀。因此，具有八角形形狀的重佈通孔200相鄰邊之間的角度θ 2(135°)比在第1A圖中具有方形形狀的重佈通孔100相鄰邊之間的角度θ 1(90°)更大。可以看出重佈通孔200相鄰邊之間沒有形成接縫處。
第2B圖是一個掃描式電子顯微鏡圖，其顯示在從頂部看具有八角形的重佈通孔中沉積金屬層後的剖視圖。第2B圖所示的掃描式電子顯微鏡圖係沿第2A圖之線段BB’的剖面。在第2B圖中，一個重佈通孔200是形成於覆蓋金屬接合墊230的第一保護層240中。以一個第一金屬層210填滿重佈通孔200並以一個第二保護層250覆蓋第一金屬層210。可以看出在第2B圖中沒有形成接縫處，因此在第2B圖觀察不到腐蝕。
有鑑於此，因理解到當金屬層沉積於通孔中時，由 於通孔的角落有更多的空間，在通孔中的角落的金屬沉積速率可隨著相鄰邊之間的角度θ增加時增加。因此，可減少在通孔邊的中央和通孔的角落之間差別的金屬沉積速率以得到比較均勻的金屬沉積速率，且也可以降低外伸的問題。更均勻的金屬沉積速率可避免通孔相鄰邊之間形成接縫處的和避免形成外伸，從而後續形成的金屬插塞可避免針孔故障。因此，增加相鄰邊之間的角度θ是一個解決通孔針孔故障問題的有效方法。
根據一些實施例，通孔相鄰邊之間的角度θ大於90°以解決針孔故障的問題。根據一些其它實施例，通孔相鄰邊之間的角度θ至少108°以解決針孔故障的問題。根據一些其它實施例，通孔相鄰邊之間的角度θ至少135°以解決針孔故障的問題。或者在一些實施例中，通孔可以是圓形的形狀以便每一個通孔具有均勻的金屬沉積速率。
根據一些實施例，一個形成凸塊底層金屬化層結構的方法如下提供。第3圖是，根據本揭露的一些實施例，形成凸塊底層金屬化層結構的流程圖。第4A-4D圖是，根據本揭露的一些實施例，一個形成凸塊底層金屬化層結構的製程的剖視圖。後續請同時參考第3圖和第4A-4D圖。
在第3圖和第4A圖的步驟310中，第一保護層420是在基板400上的金屬接合墊410上形成的。基板400具有一些半導體元件(在第4A圖中未示出)和一些已在其上形成的金屬內連線結構(在第4A圖中未示出)。金屬接合墊410可以由一個金屬形成，例如鋁或銅，或是金屬合金， 例如AlCu或AlCuSi。形成金屬接合墊的方法可透過進行沉積處理隨後圖案化處理。沉積處理可為化學氣相沉積，物理氣相沉積或電鍍。圖案化處理可以是微影和蝕刻的組合。
第一保護層420可以由氮化矽，未摻雜的矽酸鹽玻璃，聚醯亞胺，或其任意組合所製成的。例如，根據一些實施例，第一保護層420可以是一個氮化矽層。根據一些其它實施例，第一保護層420也可是下氮化矽層和上聚醯亞胺層。可以透過化學氣相沉積，旋轉塗佈，或其組合來形成第一保護層420。
在第3圖和第4A圖中的步驟320中，金屬接合墊410是透過在第一保護層420中形成一個重佈通孔425暴露出的。可以透過進行微影處理隨後使用蝕刻處理形成重佈通孔425。從頂部看，重佈通孔425具有圓形的形狀或相鄰邊之間具有角度大於90°的多邊形形狀，例如至少108°或至少135°。根據一些實施例，重佈通孔425的直徑或寬度為約1微米至約4微米。
在第3圖和第4B圖的步驟330中，第一金屬層是沉積於重佈通孔425中和在第一保護層420上。第一金屬層可以由一個複合金屬層形成，以滿足附著，障壁，導體和保護的需求。根據一些實施例，第一金屬層可以由一個底部金屬層和一個頂部金屬層所形成。例如，底部金屬層可以是鋁，鎳，釩，銅，鈦，或鎳釩，頂部金屬層可以是鎳，釩，銅，鎳釩，鉻，或鎢。第一金屬層的沉積方法可 以是物理氣相沉積，化學氣相沉積，或電鍍。
根據一些其它實施例，當第一金屬層的厚度跟重佈通孔425的直徑(或寬度)之比為至少約1.4時，例如從約1.4至約2.5，重佈通孔425相鄰邊之間的角度最好大於90°，例如至少108°或至少135°，以避免形成接縫處和外伸。例如，當重佈通孔425的直徑或寬度為約2微米，只要第一金屬層的厚度為大於或等於2.8微米將會形成接縫處和外伸而導致針孔故障。
隨後在步驟340和第4B圖中，隨後將金屬層圖案化以形成導電重佈層430。圖案化方法可以是微影和蝕刻的組合。蝕刻處理所使用的蝕刻液可能含有酸，且如果在重佈通孔425中的導電重佈層430中形成接縫處的話，可能會產生針孔故障。
在第3圖和第4C圖的步驟350中，第二保護層440是形成在導電重佈層430和第一保護層420上。第二保護層440可以由例如氮化矽，聚醯亞胺，或其任意組合所製成的。可以透過化學氣相沉積，旋轉塗佈，或其組合來形成第二保護層440。
在第3圖和第4C圖的步驟360中，在第二保護層440中形成末端通孔445以暴露部分的導電重佈層430。形成末端通孔445的方法可以是透過進行微影處理隨後使用蝕刻處理的組合。蝕刻處理所用的蝕刻液可含有另一個酸。同樣地，如果位於重佈通孔425中的導電重佈層430中有形成接縫處的話，酸可能會導致針孔故障。
在第3圖和第4D圖的步驟370中，第二金屬層是形成於末端通孔445中和在第二保護層440上。第二金屬層可以由一個複合金屬層形成。根據一些實施例，第二金屬層可包含底部附著層，擴散障壁層，銲料可附著層和可選擇性包含一個氧化障壁層。根據一些其他實施例，第二金屬層可以是Cr/CrCu/Cu，Ti/NiV，Ti/Cu，Ti/W/Au，或Ni/Au的複合金屬層。
在第3圖和第4D圖中的步驟380，一個凸塊底層金屬層450是由圖案化第二金屬層所形成的。第二金屬層的圖案化處理方法可以是微影和蝕刻的組合。蝕刻處理所使用的蝕刻液可能含有酸，且如果位於重佈通孔425中的導電重佈層430中形成接縫處的話，可能會產生針孔故障。
因此，雖然因設計規則的限制，每個重佈通孔所佔據的面積和重佈通孔相鄰之間的間距都不能再增加了。RC延遲和針孔故障的問題仍能透過增加重佈層的高度和改變重佈通孔的形狀來解決，例如從正方形改變至圓形或具有重佈通孔相鄰邊之間的角度超過90°的多邊形。
根據一些實施例，提供了一個重佈金屬化層的結構。重佈金屬化層結構包括一個絕緣保護層，其絕緣保護層具有重佈通孔以及一個導電重佈層填充於重佈通孔中且設置在保護層上。重佈通孔暴露了一個設置在基板上的金屬接合墊且從頂部看具有圓形或多邊形的形狀，且該多邊形相鄰邊之間的角度大於90°。
根據一些其它實施例，提供了一個凸塊底層金屬化 層的結構。凸塊底層金屬化層結構包括一個在基板上的金屬接合墊，一個設置在金屬接合墊上的第一保護層且具有一個暴露出金屬接合墊的重佈通孔，一個設置在重佈通孔中和在第一保護層上的重佈層，一個設置在重佈層上的第二保護層且具有一個暴露出一部分的重佈層的末端通孔，和一個設置在末端通孔中和在第二保護層上的凸塊底層金屬層。從頂部看，重佈通孔上方具有一個圓形的形狀或相鄰邊之間的角度大於90°的多邊形。
根據一些其它實施例，提供了一個形成凸塊底層金屬化層結構的方法。該方法包括以下步驟。在設置在基板上的金屬接合墊上形成一個第一保護層。在第一保護層中形成一個重佈通孔以暴露出金屬接合墊，且重佈通孔具有圓形的形狀或相鄰邊之間的角度大於90°的多邊形。在重佈通孔中和在第一保護層上形成第一金屬層。圖案化第一金屬層以形成重佈層。在重佈層上形成第二保護層。在第二保護層中形成末端通孔以暴露出一部分的重佈層。在末端通孔中和第二保護層上形成第二金屬層。將第二金屬層圖案化以形成凸塊底層金屬層。
雖然本發明已以數個較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作任意之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
200‧‧‧重佈通孔
210‧‧‧第一金屬層

Claims (6)

  1. 一重佈金屬化層結構，包含：一絕緣保護層，具有一重佈通孔，其中該重佈通孔暴露一設置在一基板上的金屬接合墊，該重佈通孔從頂部看具有一多邊形的形狀，且該多邊形相鄰邊之間的角度大於90°；以及一導電重佈層，填充於該重佈通孔中且設置於該保護層上，其中該導電重佈層的厚度跟該重佈通孔的直徑比例約1.4至約2.5，且於該重佈通孔中無接縫處及外伸形成於該導電重佈層。
  2. 如請求項1所述之結構，其中該多邊形相鄰邊之間的角度至少108°。
  3. 一凸塊底層金屬化層結構，包含：一基板上的一金屬接合墊，其中該基板具有半導體元件在其上形成；一第一保護層，設置在該金屬接合墊和該基板上，其中該第一保護層具有一暴露出該金屬接合墊的重佈通孔，其中該重佈通孔從頂部看具有相鄰邊之間的角度大於90°的一多邊形；一重佈層，設置在該重佈通孔中和該第一保護層上；一第二保護層，設置在該重佈層上，其中該第二 保護層具有一暴露出一部分之該重佈層的末端通孔；以及一凸塊底層金屬層，設置在末端通孔中和在第二保護層上，其中該重佈層的厚度跟該重佈通孔的直徑比例約1.4至約2.5，且於該重佈通孔中無接縫處及外伸形成於該重佈層。
  4. 如請求項3所述之結構，其中該多邊形相鄰邊之間的角度至少108°。
  5. 一種形成凸塊底層金屬化層結構的方法，包含：在設置於一基板上的一金屬接合墊上形成一第一保護層；在該第一保護層中形成一重佈通孔以暴露出該金屬接合墊，其中該重佈通孔從頂部看具有相鄰邊之間的角度大於90°的一多邊形；在該重佈通孔中和在該第一保護層上沉積一第一金屬層；圖案化該第一金屬層以形成一重佈層；在該重佈層上形成一第二保護層；在該第二保護層中形成一末端通孔以暴露出一部分的該重佈層；在該末端通孔中和該第二保護層上形成一第二金屬層；以及圖案化該第二金屬層以形成一凸塊底層金屬 層，其中該重佈層的厚度與該重佈通孔的直徑比例約1.4至約2.5，且於該重佈通孔中無接縫處及外伸形成於該重佈層。
  6. 如請求項5所述之方法，其中該多邊形相鄰邊之間的角度至少108°。
TW103127648A 2014-02-13 2014-08-12 凸塊底層金屬化層結構及其形成方法和重佈金屬化層結構 TWI599006B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US14/179,688 US9373594B2 (en) 2014-02-13 2014-02-13 Under bump metallization

Publications (2)

Publication Number Publication Date
TW201532218A TW201532218A (zh) 2015-08-16
TWI599006B true TWI599006B (zh) 2017-09-11

Family

ID=53775590

Family Applications (1)

Application Number Title Priority Date Filing Date
TW103127648A TWI599006B (zh) 2014-02-13 2014-08-12 凸塊底層金屬化層結構及其形成方法和重佈金屬化層結構

Country Status (4)

Country Link
US (2) US9373594B2 (zh)
KR (1) KR101651012B1 (zh)
CN (1) CN104851859B (zh)
TW (1) TWI599006B (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9984987B2 (en) * 2016-08-05 2018-05-29 Nanya Technology Corporation Semiconductor structure and manufacturing method thereof

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7244671B2 (en) 2003-07-25 2007-07-17 Unitive International Limited Methods of forming conductive structures including titanium-tungsten base layers and related structures
JP2005116756A (ja) * 2003-10-07 2005-04-28 Fujitsu Ltd 半導体装置及びその製造方法
GB2464549B (en) * 2008-10-22 2013-03-27 Cambridge Silicon Radio Ltd Improved wafer level chip scale packaging
KR101307490B1 (ko) * 2009-03-30 2013-12-11 메기가 코포레이션 상부 포스트-패시베이션 기술 및 하부 구조물 기술을 이용한 집적 회로 칩
US8283781B2 (en) * 2010-09-10 2012-10-09 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device having pad structure with stress buffer layer
US8581389B2 (en) * 2011-05-27 2013-11-12 Taiwan Semiconductor Manufacturing Company, Ltd. Uniformity control for IC passivation structure
US8871629B2 (en) * 2011-11-08 2014-10-28 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of and semiconductor devices with ball strength improvement
US8569886B2 (en) * 2011-11-22 2013-10-29 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus of under bump metallization in packaging semiconductor devices
US9159686B2 (en) 2012-01-24 2015-10-13 Taiwan Semiconductor Manufacturing Company, Ltd. Crack stopper on under-bump metallization layer
US20130320522A1 (en) 2012-05-30 2013-12-05 Taiwan Semiconductor Manufacturing Company, Ltd. Re-distribution Layer Via Structure and Method of Making Same
US9035457B2 (en) * 2012-11-29 2015-05-19 United Microelectronics Corp. Substrate with integrated passive devices and method of manufacturing the same

Also Published As

Publication number Publication date
US9373594B2 (en) 2016-06-21
KR101651012B1 (ko) 2016-08-24
US20160268221A1 (en) 2016-09-15
TW201532218A (zh) 2015-08-16
US20150228593A1 (en) 2015-08-13
CN104851859A (zh) 2015-08-19
CN104851859B (zh) 2017-11-21
US10134694B2 (en) 2018-11-20
KR20150095547A (ko) 2015-08-21

Similar Documents

Publication Publication Date Title
US11784124B2 (en) Plurality of different size metal layers for a pad structure
TWI429042B (zh) 半導體元件及其製法
US10008459B2 (en) Structures having a tapering curved profile and methods of making same
KR101548428B1 (ko) 랜딩 패드에 의하여 중첩되는 임베디드 금속 트레이스를 구비한 기판을 갖는 패키지
TWI449139B (zh) 積體電路結構
TWI467720B (zh) 裝置及低應力晶片封裝陣列製造方法
US9953954B2 (en) Wafer-level chip-scale package with redistribution layer
US9093333B1 (en) Integrated circuit device having extended under ball metallization
US8710656B2 (en) Redistribution layer (RDL) with variable offset bumps
US12027447B2 (en) Semiconductor device having a dual material redistribution line
US8736067B2 (en) Semiconductor device having a pad
US8441127B2 (en) Bump-on-trace structures with wide and narrow portions
US20130256871A1 (en) Semiconductor chip device with fragmented solder structure pads
TW201533847A (zh) 積體電路結構及其形成方法
US9524944B2 (en) Method for fabricating package structure
US9559076B2 (en) Package having substrate with embedded metal trace overlapped by landing pad
KR101416596B1 (ko) 반도체 패키지 및 그 제조방법
TWI579937B (zh) 基板結構及其製法暨導電結構
TWI599006B (zh) 凸塊底層金屬化層結構及其形成方法和重佈金屬化層結構
US7879651B2 (en) Packaging conductive structure and method for forming the same
KR101418440B1 (ko) 반도체 패키지 및 그 제조방법