CN104851859B - 凸块下金属化 - Google Patents

凸块下金属化 Download PDF

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Publication number
CN104851859B
CN104851859B CN201410281358.6A CN201410281358A CN104851859B CN 104851859 B CN104851859 B CN 104851859B CN 201410281358 A CN201410281358 A CN 201410281358A CN 104851859 B CN104851859 B CN 104851859B
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layer
hole
redistribution
passivation layer
polygon
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CN104851859A (zh
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李智飞
张复诚
郑志成
陈信吉
黄远国
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供了一种凸块下金属化结构及其形成方法。凸块下金属化结构具有从上向下看呈圆形或者相邻边之间的角大于90°的多边形的再分布通孔。因此，本发明能够改进之后形成的金属层的阶梯覆盖。

Description

凸块下金属化
技术领域
本发明总的来说涉及半导体领域，更具体地，涉及凸块下金属化结构。
背景技术
半导体工业在近几十年来最重要的趋势是一直力求增强器件性能，同时还要持续减小半导体器件部件尺寸。在如今的半导体器件中，部件尺寸普遍处于深亚微米范围。随着部件尺寸减小，亚微米金属互连变得越发重要。理论上来说，金属层应该均匀沉积并且应该以相同金属密度填充金属线的轮廓。然而，对于亚微米金属互连件的尺寸来说，通常会遇到沉积金属层的不良阶梯覆盖(poor step coverage)的情况。而且，当通过增加亚微米金属互连件的厚度来解决RC延迟问题时，只会使不良阶梯覆盖问题变得越发严重。
发明内容
根据本发明的一个方面，提供了一种再分布金属化结构，包括：绝缘钝化层，具有使设置于衬底上的金属焊盘暴露的再分布通孔，其中，再分布通孔从上向下看呈圆形或多边形，多边形的相邻边之间的角大于90°；以及导电再分布层，填充再分布通孔并且设置在钝化层上。
优选地，绝缘钝化层由氮化硅、无掺杂硅酸盐玻璃、聚酰亚胺或它们的任意组合制成。
优选地，导电再分布层由复合金属层制成。
优选地，多边形的相邻边之间的角为至少108°。
优选地，多边形的相邻边之间的角为至少135°。
优选地，导电再分布层的厚度与再分布通孔的直径的比值为大约1.4至大约2.5。
根据本发明的另一方面，提供了一种凸块下金属化结构，包括：金属焊盘，位于衬底上，衬底上形成有半导体器件；第一钝化层，设置于金属焊盘和衬底上，具有暴露金属焊盘的再分布通孔，其中，再分布通孔从上向下看呈圆形或多边形，多边形的相邻边之间的角大于90°；再分布层，设置在再分布通孔中和第一钝化层上；第二钝化层，设置在再分布层上并且具有暴露部分再分布层的末端通孔；以及凸块下金属层，设置在末端通孔中和第二钝化层上。
优选地，第一钝化层由氮化硅、无掺杂硅酸盐玻璃、聚酰亚胺或它们的任意组合制成。
优选地，再分布层包括复合金属层。
优选地，多边形的相邻边之间的角为至少108°。
优选地，多边形的相邻边之间的角为至少135°。
优选地，导电再分布层的厚度与再分布通孔的直径的比值为大约1.4至大约2.5。
优选地，第二钝化层由氮化硅、聚酰亚胺层或它们的组合制成。
根据本发明的又一方面，提供了一种形成凸块下金属化结构的方法，包括：在设置在衬底上的金属焊盘上形成第一钝化层；通过在第一钝化层中形成再分布通孔暴露金属焊盘，其中，再分布通孔从上向下看呈圆形或多边形，多边形的相邻边之间的角大于90°；在再分布通孔中和第一钝化层上沉积第一金属层；通过图案化第一金属层形成再分布层；在再分布层上形成第二钝化层；通过在第二钝化层中形成末端通孔暴露部分再分布层；在末端通孔中和第二钝化层上形成第二金属层；以及通过图案化第二金属层形成凸块下金属层。
优选地，第一钝化层由氮化硅、无掺杂硅酸盐玻璃、聚酰亚胺或它们的任意组合制成。
优选地，再分布层包括复合金属层制成。
优选地，多边形的相邻边之间的角为至少108°。
优选地，多边形的相邻边之间的角为至少135°。
优选地，导电再分布层的厚度与再分布通孔的直径的比值为大约1.4至大约2.5。
优选地，第二钝化层由氮化硅、聚酰亚胺层或它们的组合制成。
附图说明
当结合附图进行阅读时，根据下面详细的描述可以更好地理解本发明的各方面。应该注意的是，根据工业中的标准实践，各种部件没有被按比例绘制。实际上，为了清楚地讨论，各种部件的数量和尺寸可以任意增大或减小。
图1A是沉积在被金属层部分填充的传统再分布通孔中的该金属层的俯视图。
图1B是示出了在传统再分布通孔中沉积金属层之后的横截面图的扫描电子显微镜图像。
图2A是根据本发明的一些实施例的沉积在被金属层部分填充的再分布通孔中的该金属层的俯视图。
图2B是示出了根据本发明的一些实施例的在具有从上向下看时呈八边形的再分布通孔中沉积金属层之后的横截面图的扫描电子显微镜(SEM)图像。
图3是根据本发明的一些实施例的形成凸块下金属化结构的流程图。
图4A至图4D是示出了根据本发明的一些实施例的形成凸块下金属化结构的工艺的横截面图。
具体实施方式
为了实现所提出的主题的不同特征，以下发明提供了多个不同实施例或实例。以下描述了部件和配制的特定实例以简化本发明。当然，这些仅仅是实例而并不旨在进行限制。例如，以下描述中第一部件形成在第二部件上方或之上可以包括第一部件和第二部件直接接触而形成的实施例，还可以包括第一部件和第二部件之间可以形成有附加部件以使第一部件和第二部件可以不直接接触的实施例。另外，在各个实例中，本发明可以重复使用参考标号和/或字母。这种重复目的在于简化和清晰，其本身并不表示所描述的各个实施例和/或配置之间的关系。
此外，在本文中可以使用诸如“在……之下”、“在……下面”、“较低的”、“在……上面”、“较高的”等等空间关系术语以便于描述附图中所示出的一个元件或部件与其他元件或部件之间的关系。这些空间关系术语旨在包含除附图中所示出的方向以外的器件在使用或操作中的不同方向。装置可以另外定向(旋转90度或者处于其他方向)，并且可以相应地对本文所使用的空间关系描述进行同样的解释。
如上所述，由于在如今的半导体器件中亚微米金属互连变得越发重要，因此RC延迟问题可能变得越发严重。因此，增加亚微米金属互连件的厚度可以解决越发严重的RC延迟问题。然而，一方面，增加亚微米金属互连件的厚度可以解决RC延迟问题，而另一方面，沉积金属层的不良阶梯覆盖问题却可能变得更为严重。凸块下金属化也可能遇到上述进退两难的问题。
对于如今的倒装芯片技术，再分布金属层可以用来重定位集成电路(IC)的I/O接合焊盘，从而具有低成本、高密度、高灵活性和高性能的优点。然而，由于设计规则所限，覆盖接合焊盘的钝化层中的再分布通孔所占据的面积和相邻再分布通孔的距离无法再增大。因此，增加再分布金属线的厚度是降低之后形成的再分布金属层的RC延迟的唯一选择，并且因此增大了再分布通孔的长宽比。
然而，当再分布金属线的厚度与再分布通孔的直径的比值增加到至少1.4时，会由于沉积金属层的不良阶梯覆盖而造成针孔故障(pin hole failure)。图1A是沉积在被金属层部分填充的传统再分布通孔中的该金属层的俯视图。根据设计规则，从上向下看去，传统再分布通孔100的形状为方形。当再分布通孔100形成在覆盖金属焊盘(未在图1A中示出)的第一钝化层(未在图1A中示出)中之后，开始在再分布通孔100中沉积第一金属层110来覆盖第一钝化层。
在图1A中，再分布通孔100被部分填充，并且可以看出有缝隙120差不多沿着再分布通孔100的相邻边之间的对角线形成。这是因为，再分布通孔100的边的中部的金属沉积率较快，而再分布通孔100的角部的金属沉积率较慢。除了上述金属沉积率不均匀，再分布通孔100的相邻边之间的角θ1小于或等于90°。再分布通孔100的相邻边之间的角度较小使其更容易生成缝隙120，并且在沉积于再分布通孔100中的第一金属层110的上部上产生悬垂(overhangs)(未在图1A中示出)。由于随后用于图案化第一金属层110以形成再分布金属层，图案化覆盖再分布金属层的第二钝化层并且图案化形成在第二钝化层中的末端通孔中的第二金属层的酸性蚀刻溶液会通过这些缝隙120流进第一金属层110内而腐蚀该第一金属层110，因此这些缝隙120和悬垂导致之后形成的再分布金属层产生针孔故障。
而且，在再分布通孔100中的第一金属层110的沉积期间，如果于沉积在再分布通孔100中的第一金属层110的上部形成悬垂的问题严重，则甚至会在位于再分布通孔100中的金属层110中形成空隙(void)。该空隙会积聚酸性溶液，从而使腐蚀问题越发严重，并且大大增加再分布金属层的RC延迟。
图1B是示出了在传统再分布通孔中沉积金属层之后的横截面图的扫描电子显微镜(SEM)图像。图1B中示出的横截面SEM图像对应于图1A中的剖切线BB’的横截面。在图1B中，第一钝化层140沉积在金属焊盘130上。随后在第一钝化层140中形成再分布通孔100以暴露金属焊盘130。随后沉积第一金属层110以填充再分布通孔100并且覆盖第一钝化层140。在图案化第一金属层110以形成再分布金属层110a之后，进而在该再分布金属层110a上沉积第二钝化层150。在图1B中示出的SEM图像中，可以清晰地看出，沿着缝隙120形成了严重的U型腐蚀区域125。结果，严重降低了IC芯片的成品率。
鉴于上述内容，如何同时解决RC延迟问题和针孔故障成了棘手的问题。然而，最终发现，如果再分布通孔100的相邻边之间的角θ1增大，则可以同时既解决针孔故障问题又保持RC延迟较小。
图2A是根据本发明的一些实施例的沉积在被金属层部分填充的再分布通孔中的该金属层的俯视图。在图2A中，第一金属层210沉积在形成于覆盖金属焊盘的第一钝化层(未在图2A中示出)中的再分布通孔200中。再分布通孔200由第一金属层210部分填充。从上向下看时，图2A中的再分布通孔200呈八边形。因此，呈八边形的再分布通孔200的相邻边之间的角θ2(135°)大于图1A中呈方形的再分布通孔100的相邻边之间的角θ1(90°)。可以看出，在再分布通孔200的相邻边之间没有形成缝隙。
图2B是示出了在具有从上向下看时呈八边形的再分布通孔中沉积金属层之后的横截面图的扫描电子显微镜(SEM)图像。图2B中示出的横截面SEM图像对应于图2A中的剖切线BB’的横截面。在图2B中，再分布通孔200形成在覆盖金属焊盘230的第一钝化层240中。第一金属层210填充再分布通孔200，第二钝化层250覆盖第一金属层210。可以看出，在图2B中没有形成缝隙，因此在图2B中未发现腐蚀区域。
鉴于上述内容，可以理解为，当在通孔中沉积金属层时，随着通孔的相邻边之间的角θ增大，通孔角部的金属沉积率会由于通孔角部的开放空间更大而增大。因此，通孔边缘中部和通孔角部的金属沉积率之间的差异可能减小，从而使金属沉积率更均匀，并且还会缓解悬垂问题。金属沉积率更均匀能够防止通孔的相邻边之间形成缝隙并且防止形成悬垂，从而防止了随后形成在通孔中的金属插塞的针孔故障。因此，增大通孔相邻边之间的角θ能够有效解决针孔故障问题。
根据一些实施例，通孔相邻边之间的角θ大于90°以解决针孔故障问题。根据其他一些实施例，通孔相邻边之间的角θ为至少108°以解决针孔故障问题。根据其他一些实施例，通孔相邻边之间的角θ为至少135°以解决针孔故障问题。或者在一些实施例中，通孔可以是圆形以在通孔各个位置具有均匀金属沉积率。
根据一些实施例，下面提供了一种形成凸块下金属化结构的方法。图3是根据本发明的一些实施例的形成凸块下金属化结构的流程图。图4A至图4D是示出了根据本发明的一些实施例的形成凸块下金属化结构的工艺的横截面图。图3和图4A至图4D同时在下面论述。
在图3的步骤310和图4A中，第一钝化层420形成在衬底400上的金属焊盘410上。衬底400上具有已经形成的一些半导体器件(未在图4A中示出)和一些金属互连结构(未在图4A中示出)。金属焊盘410可以由诸如Al或Cu的金属形成或者由诸如AlCu或AlCuSi的金属合金形成。可以通过先进行沉积工艺再进行图案化工艺来实施金属焊盘的形成方法。上述沉积工艺可以是化学气相沉积、物理气相沉积或者镀。上述图案化工艺可以是光刻和蚀刻的组合。
第一钝化层420可以由氮化硅、无掺杂硅酸盐玻璃、聚酰亚胺或它们的组合制成。例如，根据一些实施例，第一钝化层420可以是氮化硅层。根据其他一些实施例，第一钝化层420还可以由下部氮化硅层和上部聚酰亚胺层构成。可以通过化学气相沉积、旋涂或者它们的组合来实施第一钝化层420的形成方法。
在图3的步骤320中和图4A中，通过在第一钝化层420中形成再分布通孔425暴露金属焊盘410。可以通过先进行光刻工艺再进行蚀刻工艺来实施再分布通孔425的形成方法。从上向下看，再分布通孔425为圆形或者相邻边之间的角大于90°(比如至少108°或者至少135°)的多边形。根据一些实施例，再分布通孔425的直径或宽度为大约1μm至大约4μm。
在图3的步骤330和图4B中，第一金属层随后沉积在再分布通孔425中和第一钝化层420上。第一金属层可以由复合金属层制成，以符合粘合、阻挡、导体和保护的要求。根据一些实施例，第一金属层可以由底部金属层和顶部金属层制成。例如，底部金属层可以是Al、Ni、V、Cu、Ti或NiV，顶部金属层可以是Ni、V、Cu、NiV、Cr或W。第一金属层的沉积方法可以是物理气相沉积、化学气相沉积或者电镀。
根据其他一些实施例，当第一金属层的厚度与再分布通孔425的直径(或宽度)的比例为至少大约1.4(比如从大约1.4至大约2.5)时，再分布通孔425的相邻边之间的角最好大于90°(比如至少108°或者至少135°)，以防止形成缝隙和悬垂。例如，当再分布通孔425的直径或宽度为大约2μm时，只要第一金属层的厚度大于或等于2.8μm，则会产生缝隙和悬垂并且造成针孔故障。
随后在步骤340和图4B中，金属层随后被图案化以形成导电再分布层430。可以通过光刻和蚀刻的组合实施图案化方法。蚀刻工艺所使用的蚀刻溶液可能含酸，这可能导致在再分布通孔425中形成有缝隙的情况下，位于再分布通孔425中的导电再分布层430中发生针孔故障。
在图3的步骤350和图4C中，第二钝化层440形成在导电再分布层430和第一钝化层420上。第二钝化层440可以由例如氮化硅、聚酰亚胺或者它们的组合制成。可以通过化学气相沉积、旋涂或者它们的组合来实施第二钝化层440的形成方法。
在图3的步骤360中和图4C中，通过在第二钝化层440中形成末端通孔445来暴露部分导电再分布层430。可以通过先进行光刻工艺再进行蚀刻工艺来实施末端通孔445的形成方法。蚀刻工艺可以使用含另一种酸的蚀刻溶液。类似地，酸可能在再分布通孔425中形成有缝隙的情况下在位于再分布通孔425中的导电再分布层430中造成针孔故障。
在图3的步骤370中和图4D中，第二金属层形成在末端通孔445中和第二钝化层440上。第二金属层可以由复合金属层制成。根据一些实施例，第二金属层可以包括底部粘合层、扩散阻挡层、可湿焊料层和可选的氧化阻挡层。根据其他一些实施例，第二金属层可以是Cr/CrCu/Cu、Ti/NiV、Ti/Cu、Ti/W/Au或者Ni/Au的复合金属层。
在图3的步骤380和图4D中，通过图案化第二金属层形成凸块下金属层450。可以通过光刻和蚀刻工艺的组合实施第二金属层的图案化方法。蚀刻工艺所使用的蚀刻溶液可能含酸，这可能导致在再分布通孔425中形成有缝隙的情况下，位于再分布通孔425中的导电再分布层430中发生针孔故障。
因此，尽管由设计规则所限，由每个再分布通孔所占据的面积和相邻再分布通孔之间的间距无法再增大。然而，仍可以通过增加再分布层的高度并且将再分布通孔的形状由方形改变为圆形或者再分布通孔的相邻边之间的角大于90°的多边形来解决RC延迟问题和针孔故障。
根据一些实施例，提供了一种再分布金属化结构。该再分布金属化结构包括具有再分布通孔的绝缘钝化层以及填充再分布通孔并且设置在钝化层上的导电再分布层。再分布通孔暴露设置在衬底上的金属焊盘，并且再分布通孔从上向下看呈圆形或多边形，多边形的相邻边之间的角大于90°。
根据其他一些实施例，提供了一种凸块下金属化结构。该凸块下金属化结构包括位于衬底上的金属焊盘、设置在该金属焊盘上并且具有暴露该金属焊盘的再分布通孔的第一钝化层、暴露金属焊盘的再分布通孔、设置在再分布通孔中和第一钝化层上的再分布层、设置在再分布层上并且具有暴露部分再分布层的末端通孔的第二钝化层、以及设置在末端通孔中和第二钝化层上的凸块下金属层。再分布通孔从上向下看呈圆形或多边形，多边形的相邻边之间的角大于90°。
根据其他一些实施例，提供了一种形成凸块下金属化结构的方法。该方法包括以下步骤。在设置在衬底上的金属焊盘上形成第一钝化层。通过在第一钝化层中形成再分布通孔暴露金属焊盘，其中，再分布通孔从上向下看呈圆形或多边形，多边形的相邻边之间的角大于90°。在再分布通孔中和第一钝化层上设置第一金属层。通过图案化第一金属层形成再分布层。在再分布层上形成第二钝化层。通过在第二钝化层中形成末端通孔暴露部分再分布层。在末端通孔中和第二钝化层上形成第二金属层。通过图案化第二金属层形成凸块下金属层。
以上论述了多个实施例的部件，使得本领域普通技术人员可以更好地理解本发明的各个方面。本领域普通技术人员应该理解，可以很容易地使用本发明作为基础来设计或修改其他用于执行与本文所介绍实施例相同的目的和/或实现相同优点的工艺和结构。本领域普通技术人员还应该意识到，这种等效构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，可以进行多种变化、替换以及改变。

Claims (17)

1.一种再分布金属化结构，包括：
绝缘钝化层，具有使设置于衬底上的金属焊盘暴露的再分布通孔，其中，所述再分布通孔从上向下看呈圆形或多边形，所述多边形的相邻边之间的角大于90°；以及
导电再分布层，填充所述再分布通孔并且设置在所述钝化层上，其中，所述导电再分布层的厚度与所述再分布通孔的直径的比值为1.4至2.5，并且在所述再分布通孔中没有形成缝隙和悬垂。
2.根据权利要求1所述的结构，其中，所述绝缘钝化层由氮化硅、无掺杂硅酸盐玻璃、聚酰亚胺或它们的任意组合制成。
3.根据权利要求1所述的结构，其中，所述导电再分布层由复合金属层制成。
4.根据权利要求1所述的结构，其中，所述多边形的相邻边之间的角为至少108°。
5.根据权利要求1所述的结构，其中，所述多边形的相邻边之间的角为至少135°。
6.一种凸块下金属化结构，包括：
金属焊盘，位于衬底上，所述衬底上形成有半导体器件；
第一钝化层，设置于所述金属焊盘和所述衬底上，具有暴露所述金属焊盘的再分布通孔，其中，所述再分布通孔从上向下看呈圆形或多边形，所述多边形的相邻边之间的角大于90°；
再分布层，设置在所述再分布通孔中和所述第一钝化层上；
第二钝化层，设置在所述再分布层上并且具有暴露部分所述再分布层的末端通孔；以及
凸块下金属层，设置在所述末端通孔中和所述第二钝化层上；
其中，所述再分布层的厚度与所述再分布通孔的直径的比值为1.4至2.5，并且在所述再分布通孔中没有形成缝隙和悬垂。
7.根据权利要求6所述的结构，其中，所述第一钝化层由氮化硅、无掺杂硅酸盐玻璃、聚酰亚胺或它们的任意组合制成。
8.根据权利要求6所述的结构，其中，所述再分布层包括复合金属层。
9.根据权利要求6所述的结构，其中，所述多边形的相邻边之间的角为至少108°。
10.根据权利要求6所述的结构，其中，所述多边形的相邻边之间的角为至少135°。
11.根据权利要求6所述结构，其中，所述第二钝化层由氮化硅、聚酰亚胺层或它们的组合制成。
12.一种形成凸块下金属化结构的方法，所述方法包括：
在设置在衬底上的金属焊盘上形成第一钝化层；
通过在所述第一钝化层中形成再分布通孔暴露所述金属焊盘，其中，所述再分布通孔从上向下看呈圆形或多边形，所述多边形的相邻边之间的角大于90°；
在所述再分布通孔中和所述第一钝化层上沉积第一金属层；
通过图案化所述第一金属层形成再分布层；
在所述再分布层上形成第二钝化层；
通过在所述第二钝化层中形成末端通孔暴露部分所述再分布层；
在所述末端通孔中和所述第二钝化层上形成第二金属层；以及
通过图案化所述第二金属层形成凸块下金属层；
其中，所述再分布层的厚度与所述再分布通孔的直径的比值为1.4至2.5，并且在所述再分布通孔中没有形成缝隙和悬垂。
13.根据权利要求12所述的方法，其中，所述第一钝化层由氮化硅、无掺杂硅酸盐玻璃、聚酰亚胺或它们的任意组合制成。
14.根据权利要求12所述的方法，其中，所述再分布层包括复合金属层制成。
15.根据权利要求12所述的方法，其中，所述多边形的相邻边之间的角为至少108°。
16.根据权利要求12所述的方法，其中，所述多边形的相邻边之间的角为至少135°。
17.根据权利要求12所述的方法，其中，所述第二钝化层由氮化硅、聚酰亚胺层或它们的组合制成。
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102217061A (zh) * 2008-10-22 2011-10-12 剑桥硅无线电通信有限公司 改善的晶圆级芯片尺寸封装
CN102403290A (zh) * 2010-09-10 2012-04-04 台湾积体电路制造股份有限公司 半导体组件及制造半导体组件的方法
CN102800650A (zh) * 2011-05-27 2012-11-28 台湾积体电路制造股份有限公司 用于ic钝化结构的均匀度控制

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7244671B2 (en) * 2003-07-25 2007-07-17 Unitive International Limited Methods of forming conductive structures including titanium-tungsten base layers and related structures
JP2005116756A (ja) * 2003-10-07 2005-04-28 Fujitsu Ltd 半導体装置及びその製造方法
JP5714564B2 (ja) * 2009-03-30 2015-05-07 クゥアルコム・インコーポレイテッドＱｕａｌｃｏｍｍ Ｉｎｃｏｒｐｏｒａｔｅｄ 上部ポストパッシベーション技術および底部構造技術を使用する集積回路チップ
US8871629B2 (en) * 2011-11-08 2014-10-28 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of and semiconductor devices with ball strength improvement
US8569886B2 (en) * 2011-11-22 2013-10-29 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus of under bump metallization in packaging semiconductor devices
US9159686B2 (en) 2012-01-24 2015-10-13 Taiwan Semiconductor Manufacturing Company, Ltd. Crack stopper on under-bump metallization layer
US20130320522A1 (en) 2012-05-30 2013-12-05 Taiwan Semiconductor Manufacturing Company, Ltd. Re-distribution Layer Via Structure and Method of Making Same
US9035457B2 (en) * 2012-11-29 2015-05-19 United Microelectronics Corp. Substrate with integrated passive devices and method of manufacturing the same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102217061A (zh) * 2008-10-22 2011-10-12 剑桥硅无线电通信有限公司 改善的晶圆级芯片尺寸封装
CN102403290A (zh) * 2010-09-10 2012-04-04 台湾积体电路制造股份有限公司 半导体组件及制造半导体组件的方法
CN102800650A (zh) * 2011-05-27 2012-11-28 台湾积体电路制造股份有限公司 用于ic钝化结构的均匀度控制

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