TWI683398B - 半導體封裝體及其形成方法 - Google Patents
半導體封裝體及其形成方法 Download PDFInfo
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- TWI683398B TWI683398B TW107138950A TW107138950A TWI683398B TW I683398 B TWI683398 B TW I683398B TW 107138950 A TW107138950 A TW 107138950A TW 107138950 A TW107138950 A TW 107138950A TW I683398 B TWI683398 B TW I683398B
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- conductive
- metal
- patterns
- conductive pattern
- electrically coupled
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Abstract
一種半導體封裝體,包含積體被動元件(IPD),積體被動元件包含:一或多個被動元件,位於第一基底上;以及金屬化層,位於一或多個被動元件上且電耦接至一或多個被動元件,其中金屬化層的最頂部金屬化層包含第一多個導電圖案以及與第一多個導電圖案交錯的第二多個導電圖案。IPD亦包含位於最頂部金屬化層上的第一凸塊下金屬化(UBM)結構,其中第一UBM結構包含:第一多個導電帶,第一多個導電帶中的每一者電耦接至第一多個導電圖案中的各別一者;以及第二多個導電帶,與第一多個導電帶交錯,第二多個導電帶中的每一者電耦接至第二多個導電圖案中的各別一者。
Description
本發明的實施例是有關於半導體封裝體及其形成方法。
歸因於各種電子組件(例如電晶體、二極體、電阻器、電容器等)的積體密度的持續改良,半導體行業已經歷快速增長。主要而言,積體密度的此改良來自最小特徵大小的反覆減小,此允許將更多組件整合至給定區域中。由於近來對甚至更小的電子元件的需求已增長,因而對半導體晶粒的更小且更具創造性的封裝技術的需要已增長。
此等封裝技術的實例為積體扇出型(integrated fan-out;InFO)封裝技術。在InFO封裝中,將晶粒嵌入於模塑材料中。重佈線結構形成於晶粒的第一側上且電耦接至晶粒。重佈線結構延伸超出晶粒的側向範圍。重佈線結構的導電特徵(諸如導電線或導電墊)允許在超出晶粒的邊界的位置處對晶粒的電連接。
本發明實施例的一種半導體封裝體,包括積體被動元件。積體被動元件包括一或多個被動元件、金屬化層以及第一凸
塊下金屬化結構。一或多個被動元件位於第一基底上。金屬化層,位於一或多個被動元件上且電耦接至一或多個被動元件,其中金屬化層的最頂部金屬化層包括第一多個導電圖案以及第二多個導電圖案。第二多個導電圖案與第一多個導電圖案交錯。第一凸塊下金屬化結構位於最頂部金屬化層上,其中第一凸塊下金屬化結構包括第一多個導電帶以及第二多個導電帶。第一多個導電帶中的每一者電耦接至第一多個導電圖案中的各別一者。第二多個導電帶與第一多個導電帶交錯,第二多個導電帶中的每一者電耦接至第二多個導電圖案中的各別一者。
本發明實施例的一種半導體封裝體,包括積體被動元件以及積體扇出型封裝體。積體被動元件包括被動元件、內連線結構以及第一凸塊下金屬化結構。被動元件位於基底上。內連線結構位於被動元件及基底上,內連線結構的頂部金屬化層具有多個第一金屬圖案及平行於多個第一金屬圖案的多個第二金屬圖案,多個第二金屬圖案與多個第一金屬圖案交錯。第一凸塊下金屬化結構電耦接至內連線結構的頂部金屬化層,第一凸塊下金屬化結構具有多個第一金屬帶及平行於多個第一金屬帶的多個第二金屬帶,多個第二金屬帶與多個第一金屬帶交錯,多個第一金屬帶電耦接至多個第一金屬圖案,且多個第二金屬帶電耦接至多個第二金屬圖案。積體扇出型封裝體包括晶粒、重佈線結構以及第二凸塊下金屬化結構。晶粒嵌入於模塑材料中。重佈線結構位於模塑材料上,重佈線結構電耦接至晶粒。第二凸塊下金屬化結構電耦接至重佈線結構,第二凸塊下金屬化結構的形狀匹配第一凸塊下金屬化結構的形狀,第二凸塊下金屬化結構接合至第一凸塊下金
屬化結構。
本發明實施例的一種形成半導體封裝體的方法,包括:在基底上的被動元件上形成內連線結構,內連線結構電耦接至被動元件,內連線結構的頂部金屬化層包括多個第一金屬圖案及平行於多個第一金屬圖案的多個第二金屬圖案;以及在內連線結構上形成第一凸塊下金屬化結構,第一凸塊下金屬化結構包括多個第一金屬帶及平行於多個第一金屬帶的多個第二金屬帶,多個第一金屬帶電耦接至多個第一金屬圖案中的各別一者,且多個第二金屬帶電耦接至多個第二金屬圖案中的各別一者。
110、140‧‧‧重佈線結構
111、113、142、144、146、148、191、193‧‧‧介電層
114、131、133、135‧‧‧導電線
119‧‧‧導電柱
120‧‧‧晶粒
128‧‧‧晶粒接點
129‧‧‧介電材料
130‧‧‧模塑材料
131G、131GB、131GF、131P、131PB、131PF、149G、149G'、149G"、149GB、149GF、149P、149P'、149P"、149PB、149PF、187G、187P、189G、189P、221‧‧‧導電圖案
132、134、136、138‧‧‧導通孔
149、189‧‧‧UBM結構
160‧‧‧頂部封裝體
161‧‧‧基底
162‧‧‧半導體晶粒
163‧‧‧導電墊
165‧‧‧模塑材料
167‧‧‧接合線
168‧‧‧導電接頭
173‧‧‧焊料區
180、180A、180B、180C、180D、180E、180F‧‧‧IPD181‧‧‧基底
182、184‧‧‧墊
183、183A、183B‧‧‧被動元件
185、187‧‧‧金屬化層
186、188、188A、188B、188C、188D、188G、188L、188P‧‧‧通孔
188E‧‧‧端部部分
189B、189GB、189PB‧‧‧基部
189FA、189FB、189FC、189FD、189FE、189GF、189PF‧‧‧指狀件
199‧‧‧內連線結構
211、211A、211B‧‧‧電流路徑
215‧‧‧電感器
231‧‧‧延伸區域
500、510、520、530‧‧‧區域
1100‧‧‧InFO封裝體
1100'‧‧‧底部封裝體
1200、1300‧‧‧半導體封裝體
3000‧‧‧方法
3010、3020‧‧‧步驟
A-A~G-G‧‧‧橫截面
D1、D2、D3、S1~S13‧‧‧距離
D4~D9、T1、T2、W1~W4、WL、WS‧‧‧寬度
L‧‧‧長度
X、Y‧‧‧方向
當結合隨附圖式閱讀時,自以下實施方式(detailed description)最佳地理解本揭露內容的態樣。應注意,根據業界中的標準慣例,各種特徵未按比例繪製。事實上,可出於論述清楚起見而任意地增大或減小各種特徵的尺寸。
圖1示出一些實施例中的貼合有積體被動元件(integrated passive device;IPD)的InFO封裝體的一部分的橫截面視圖。
圖2、圖3、圖4A至圖4C、圖5A至圖5C、圖6A至圖6C、圖7A至圖7C以及圖8至圖12示出一些實施例中的不同實施例IPD的各種視圖。
圖13A、圖13B、圖14A、圖14B、圖15、圖16、圖17A以及圖17B示出一些實施例中的繪示InFO封裝體的最頂部重佈線層及IPD的最頂部金屬化層的設計以及InFO封裝體的最頂部重佈線層與IPD的最頂部金屬化層之間的相互作用的各種實施例。
圖18為示出一些實施例中的多個電感器的並聯耦接的電路圖。
圖19及圖20示出一些實施例中的針對InFO封裝體的UBM結構的導電圖案的各種設計。
圖21及圖22示出一些實施例中的針對IPD的凸塊下金屬化(under bump metallization;UBM)結構的各種設計。
圖23示出一些實施例中的半導體元件的橫截面視圖。
圖24示出一些實施例中的製造半導體元件的方法的流程圖。
以下揭露內容提供用以實施本發明的不同特徵的諸多不同實施例或實例。下文描述組件及配置的具體實例以簡化本揭露內容。當然,此等組件及配置僅為實例且並不意欲為限制性的。舉例而言,在以下描述中,第一特徵在第二特徵上方或在第二特徵上的形成可包含第一特徵及第二特徵直接接觸地形成的實施例,且亦可包含額外特徵可形成於第一特徵與第二特徵之間以使得第一特徵與第二特徵可不直接接觸的實施例。此外,本揭露內容可在各種實例中重複附圖標號及/或字母。除非另外規定,否則類似標號指示相同或類似組件。
另外,為易於描述,本文中可使用諸如「在...下面(beneath)」、「在...下方(below)」、「下部(lower)」、「在...上方(above)」、「上部(upper)」以及類似術語的空間相對術語來描述如在圖式中所示出的一個構件或特徵與另一構件或特徵的關係。除圖式中所描繪的定向之外,空間相對術語亦意欲涵蓋元件在使
用或操作中的不同定向。設備可以其他方式定向(旋轉90度或處於其他定向)且本文中所使用的空間相對描述詞可同樣相應地進行解譯。
在半導體封裝體的上下文中且具體而言在包括積體被動元件(IPD)的半導體封裝體的方法及結構的上下文中論述本揭露內容的實施例。在一些實施例中,IPD元件的凸塊下金屬化(UBM)結構包括帶形導電圖案或梳形導電圖案。在一些實施例中,帶形導電圖案或梳形導電圖案的指狀件與IPD的頂部金屬化層的導電圖案平行。在一些實施例中,帶形導電圖案或梳形導電圖案的指狀件垂直於IPD的頂部金屬化層的導電圖案。在一些實施例中,IPD的UBM結構接合至積體扇出型(InFO)封裝體的UBM結構。在一些實施例中,InFO封裝體的最頂部重佈線層具有導電圖案,所述導電圖案與IPD的頂部金屬化層的導電圖案平行或垂直於IPD的頂部金屬化層的導電圖案。
圖1示出半導體封裝體1200的一部分的橫截面視圖,半導體封裝體1200包含InFO封裝體1100及貼合至InFO封裝體1100的IPD 180。如圖1中所示出,InFO封裝體1100的UBM結構149例如經由焊料區173接合至IPD 180的UBM結構189。注意,圖1中所示出的各種特徵的形狀僅出於說明目的且不為限制性的。其他形狀亦為可能的。舉例而言,IPD的UBM結構189可並未如圖1中所示出般將左側上的通孔188與右側上的通孔188連接。作為另一實例,焊料區173可並未如圖1中所示出般為連續區,且可包含焊料的兩個或更多個獨立的區。下文中論述UBM結構189的各種實施例。半導體封裝體1200的此等及其他變化全部意欲包含
於本揭露內容的範疇內。
如圖1中所示出,InFO封裝體1100包括嵌入於模塑材料130中的晶粒120(亦稱為半導體晶粒,或積體電路(integrated circuit;IC)晶粒),及形成於晶粒120的前側(例如,晶粒120的具有晶粒接點128的側)上的重佈線結構140。重佈線結構140包括形成於重佈線結構140的一或多個介電層(例如介電層142/介電層144/介電層146/介電層148)中的導電特徵,諸如導電線(例如導電線131/導電線133/導電線135)及導通孔(例如導通孔132/導通孔134/導通孔136/導通孔138)。用於與IPD接合的UBM結構149形成於重佈線結構140的最頂部介電層(例如介電層142)上且電耦接至重佈線結構140。
晶粒120可包含半導體基底,諸如摻雜或未摻雜的矽,或絕緣層上半導體(semiconductor-on-insulator;SOI)基底的主動層。半導體基底可包含其他半導體材料,諸如:鍺;化合物半導體,包含碳化矽、砷化鎵、磷化鎵、氮化鎵、磷化銦、砷化銦及/或銻化銦;合金半導體,包含矽鍺(SiGe)、磷化鎵砷(GaAsP)、砷化銦鋁(AlInAs)、砷化鎵鋁(AlGaAs)、砷化銦鎵(GaInAs)、磷化銦鎵(GaInP)及/或磷砷化銦鎵(GaInAsP);或其組合。亦可使用其他基底,諸如多層或梯度基底。諸如電晶體、二極體、電容器、電阻器等的元件可形成於半導體基底中及/或半導體基底上,且可藉由內連線結構內連以形成積體電路,所述內連線結構包括例如半導體基底上的一或多個介電層中的金屬化圖案。
晶粒120更包括進行外部連接的墊,諸如鋁墊。墊在可稱為晶粒120的主動側或前側的位置上。鈍化膜形成於晶粒120
的前側處且在墊的部分上。開口穿過鈍化膜延伸至墊。諸如導電柱(例如包括諸如銅的金屬)的晶粒接點128延伸至鈍化膜的開口中且機械耦接及電耦接至各別墊。晶粒接點128可藉由例如鍍覆或類似者來形成。晶粒接點128電耦接至晶粒120的積體電路。
介電材料129形成於晶粒120的主動側上,諸如形成於鈍化膜及/或晶粒接點128上。介電材料129側向包封晶粒接點128,且介電材料129與晶粒120側向共端。介電材料129可以是:聚合物,諸如聚苯并噁唑(polybenzoxazole;PBO)、聚醯亞胺、苯并環丁烯(benzocyclobutene;BCB)或類似者;氮化物,諸如氮化矽或類似者;氧化物,諸如氧化矽、磷矽酸鹽玻璃(phosphosilicate glass;PSG)、硼矽酸鹽玻璃(borosilicate glass;BSG)、硼摻磷矽酸鹽玻璃(boron-doped phosphosilicate glass;BPSG)或類似者;或其組合,且可例如藉由旋轉塗佈、疊層、CVD或類似者形成。
參考圖1,作為實例,晶粒120周圍的模塑材料130可包括環氧樹脂、有機聚合物、添加有或未添加有二氧化矽基填料或玻璃填料的聚合物,或其他材料。可使用任何適合的形成方法來形成模塑材料130,諸如晶圓級模塑、壓縮模塑、轉移模塑或類似者。儘管未示出,但可在將晶粒120貼合至載具的第一側之後形成模塑材料130,在此之後,模塑材料130形成於載具的第一側上及晶粒120周圍。在一些實施例中,導電柱(見例如圖23中的導電柱119)在形成模塑材料130之前形成於載具的第一側上。
如圖1中所示出,重佈線結構140形成於晶粒120及模塑材料130上。在一些實施例中,重佈線結構140的一或多個介
電層(例如介電層142、介電層144、介電層146以及介電層148)由以下形成:聚合物,諸如PBO、聚醯亞胺、BCB或類似者;氮化物,諸如氮化矽;氧化物,諸如氧化矽、PSG、BSG、BPSG或類似者。一或多個介電層可藉由適合的沈積製程來形成,諸如旋轉塗佈、CVD、疊層、類似者或其組合。
在一些實施例中,重佈線結構140的導電特徵包括由諸如銅、鈦、鎢、鋁或類似物的適合導電材料形成的導電線(例如導電線131/導電線133/導電線135)及導通孔(例如導通孔132/導通孔134/導通孔136/導通孔138)。可藉由以下步驟來形成重佈線結構140:形成介電層;在介電層中形成開口以暴露底層導電特徵;在介電層上及開口中形成晶種層;在晶種層上形成具有所設計圖案的圖案化光阻;對所設計圖案中的及晶種層上的導電材料進行鍍覆(例如電鍍或無電式鍍覆);以及移除光阻及未在其上形成導電材料的晶種層的部分。形成重佈線結構140的其他方法亦為可能的且全部意欲包含於本揭露內容的範疇內。
圖1的重佈線結構140中的介電層的數目及導電特徵的層的數目僅為非限制性實例。介電層的其他數目及導電特徵的層的其他數目亦為可能的且全部意欲包含於本揭露內容的範疇內。本文中的論述可將重佈線層(redistribution layer;RDL)131稱為重佈線結構140的最頂部RDL,應理解,當在重佈線結構140中使用其他數目的RDL時,最頂部RDL指代距晶粒120最遠的RDL。
圖1亦示出InFO封裝體1100的UBM結構149,UBM結構149形成於重佈線結構140上且電耦接至重佈線結構140。為形成UBM結構149,在重佈線結構140的最頂部介電層(例如介
電層142)中形成開口以暴露重佈線結構140的導電特徵(例如銅線或銅墊)。在形成開口之後,UBM結構149可形成為與暴露的導電特徵電接觸。在一實施例中,UBM結構149包括三層導電材料,諸如鈦層、銅層以及鎳層。然而,存在適合於UBM結構149的形成的材料及層的諸多適合的配置,諸如鉻/鉻銅合金/銅/金的配置、鈦/鈦鎢/銅的配置,或銅/鎳/金的配置。可用於UBM結構149的任何適合的材料或材料層全部意欲包含於本揭露內容的範疇內。
可藉由以下來產生UBM結構149:在最頂部介電層(例如介電層142)上且沿穿過最頂部介電層至重佈線結構140的暴露的導電特徵的開口的內部形成每一層。可使用諸如電化學鍍覆的鍍覆製程來執行每一層的形成,但取決於所使用的材料,可替代地使用其他形成製程,諸如濺鍍、蒸鍍或PECVD製程。
在一些實施例中,UBM結構149可與IPD 180的UBM結構189具有(例如在製造誤差容限內)實質上相同的形狀及/或實質上相同的大小。舉例而言,在平面視圖中,InFO封裝體1100的UBM結構149的邊界可與IPD 180的UBM結構189的邊界完全交疊。因此,在下文中的論述中,除非另外規定,否則假定UBM結構149的形狀及/或大小匹配UBM結構189的彼等形狀及/或大小。
仍參考圖1,IPD 180包括基底181及形成於基底181中/基底181上的多個被動元件183(例如被動元件183A及被動元件183B),諸如電容器或電感器。內連線結構199包含介電層(例如介電層191/介電層193)及形成於介電層中的金屬化層(例如金屬
化層185、金屬化層187)。此外,內連線結構199亦包含形成於介電層191/介電層193中的通孔(例如通孔186/通孔188)。UBM結構189形成於IPD 180的最頂部介電層(例如介電層193)上。UBM結構189經由內連線結構199電耦接至被動元件183。如圖1中所示出,UBM結構189藉由例如焊料區173接合至UBM結構149。在其他實施例中,UBM結構189藉由例如直接接合製程直接接合至UBM結構149,因此UBM結構189與UBM結構149之間未形成焊料區。
IPD 180的基底181可以是與晶粒120的基底相同或類似的半導體基底,因此不重複細節。被動元件183形成於基底181中/基底181上。被動元件183中的每一者具有用於將被動元件183電耦接至被動元件183外部的電路的墊182/墊184,諸如銅墊或鋁墊。在一些實施例中,墊中的一者(例如,可稱為電源墊的墊182)被配置為電耦接至電源供應器,例如5伏電壓供應器、3伏電壓供應器、1.3伏電壓供應器或類似者;且另一墊(例如,可稱為接地墊的墊184)被配置為電耦接至諸如電接地的參考電壓。可使用任何適合的方法來形成內連線結構199,諸如已知且用於形成晶粒120的內連線結構的方法。
在一些實施例中,被動元件183為電容器,且內連線結構199藉由例如並聯連接被動元件183來將被動元件183中的兩者或更多者電耦接在一起。舉例而言,接地墊184藉由金屬化層185電耦接在一起。電源墊182藉由例如金屬化層185/金屬化層187、通孔186/通孔188以及UBM結構189電耦接在一起。本領域的技術人員將瞭解,各自具有電容C的N個並聯連接的電容器
的等效電容為N×C。因此,藉由並聯連接多個電容器183,IPD 180能夠將大得多的等效電容(例如0.001微法拉至100微法拉)提供至外部電路或外部元件(例如InFO封裝體1100)。
如圖1中所示出,金屬化層185(例如導電線)形成於被動元件183上且與被動元件183電耦接。金屬化層187形成於介電層191上,且UBM結構189形成於內連線結構199的最頂部介電層(例如介電層193)上。通孔186形成於金屬化層185與金屬化層187之間且電耦接金屬化層185及金屬化層187,且通孔188形成於金屬化層187與UBM結構189之間且電耦接金屬化層187及UBM結構189。注意,IPD 180的所有特徵並非均在圖1的橫截面視圖中可見。此外,圖1中所示出的UBM結構189及電連接是出於說明目的且不為限制性的。如下文中所論述,UBM結構189的各種設計及UBM結構189與內連線結構199之間的各種電連接為可能的。此等及其他修改全部意欲包含於本揭露內容的範疇內。
出於說明目的,圖1中的內連線結構199具有兩個介電層191/介電層193及兩個金屬化層185/金屬化層187。其他數目的介電層、其他數目的金屬化層以及通孔的其他數目的層亦為可能的且全部意欲包含於本揭露內容的範疇內。本文中的論述可將金屬化層187稱為內連線結構199的(例如距基底181最遠的)最頂部金屬化層,且可將介電層193稱為內連線結構199的最頂部介電層,應理解,當在內連線結構199中使用其他數目的介電層及其他數目的金屬化層時,最頂部金屬化層及最頂部介電層分別指代內連線結構199的距基底181最遠的金屬化層及介電層。
圖2、圖3、圖4A至圖4C、圖5A至圖5C、圖6A至圖
6C、圖7A至圖7C以及圖8至圖12示出繪示不同實施例IPD的UBM結構189的設計的各種視圖(例如平面視圖、橫截面視圖)。出於清楚起見,圖式中未示出IPD的所有特徵。
圖2示出根據一實施例的IPD 180A的平面視圖。注意,出於清楚起見,圖2的平面視圖中未示出IPD 180A的所有層。類似而言,各別平面視圖(例如圖3、圖4A、圖5A、圖6A以及圖7A)中未示出下文中所論述的各種實施例IPD(例如IPD 180B至IPD 180F)中的每一者的所有層。在圖2的實例中,IPD 180A的最頂部金屬化層187包括多個導電圖案(例如金屬圖案)187P及導電圖案187G。具體而言,導電圖案187P/導電圖案187G包括彼此平行的多個導電特徵(例如導電線、金屬線、金屬帶)。舉例而言,多個導電圖案187P/導電圖案187G的(例如,沿圖2的Y方向的)縱向軸彼此平行,且導電圖案187P/導電圖案187G可與彼此均勻地間隔開,如在圖2中所示出。此外,導電圖案187P(或導電圖案187G)電耦接至相同電壓位準。舉例而言,導電圖案187P藉由內連線結構199(見例如圖1)電耦接至電源墊182,且因此與電源墊182具有相同電壓。類似而言,導電圖案187G藉由內連線結構199(見例如圖1)電耦接至接地墊184,且因此與接地墊184具有相同電壓。因此,可將導電圖案187P稱為電源圖案187P,且可將導電圖案187G稱為接地圖案187G。此外,導電圖案187P與導電圖案187G交錯。換言之,電源圖案187P及接地圖案187G交替地設置於最頂部介電層193上。在一些實施例中,導電圖案187P/導電圖案187G具有相同或類似的形狀及/或相同或類似的大小。
在圖2中,IPD 180A的UBM結構189包括多個導電圖案(例如導電線、金屬線、金屬帶)189P及導電圖案189G。在所示出的實施例中,多個導電圖案189P/導電圖案189G彼此平行。導電圖案189P/導電圖案189G可與彼此均勻地間隔開。在一些實施例中,導電圖案189P/導電圖案189G具有相同或類似的形狀及/或相同或類似的大小。如圖2中所示出,導電圖案189P與導電圖案187P之間存在一對一對應關係,且導電圖案189G與導電圖案187G之間存在一對一對應關係。換言之,導電圖案189P中的每一者藉由通孔188電耦接至導電圖案187P中的各別一者,且導電圖案189G中的每一者藉由通孔188電耦接至導電圖案187G中的各別一者。
如圖2中所示出,導電圖案189P/導電圖案189G平行於導電圖案187P/導電圖案187G。儘管在圖2中將導電圖案189P/導電圖案189G示出為(例如,沿X方向量測的)寬度小於導電圖案187P/導電圖案187G的(例如,沿X方向量測的)寬度,但導電圖案189P/導電圖案189G可與導電圖案187P/導電圖案187G具有相同寬度或寬度大於導電圖案187P/導電圖案187G的寬度。類似而言,儘管在圖2中導電圖案189P/導電圖案189G的(例如,沿Y方向量測的)長度小於導電圖案187P/導電圖案187G的長度,但此等是出於說明目的且不為限制性的。導電圖案189P/導電圖案189G可與導電圖案187P/導電圖案187G具有相同長度或長度大於導電圖案187P/導電圖案187G的長度。此外,在圖2中將通孔188的形狀示出為圓形。亦可使用其他適合的形狀且全部意欲包含於本揭露內容的範疇內,所述其他適合的形狀諸如卵形、
矩形(見例如圖3中的通孔188)、線形(見例如圖4中的通孔188)、矩形的群組(見例如圖5A中的通孔188)、類似者或其組合。
圖3示出根據一實施例的IPD 180B的平面視圖。圖3中的IPD 180B類似於圖2中的IPD 180A,但有一些修改。舉例而言,UBM結構189的導電圖案189P/導電圖案189G垂直於最頂部金屬化層187的導電圖案187P/導電圖案187G。此外,選擇通孔188的位置以將導電圖案189P與對應導電圖案187P連接,且將導電圖案189G與對應導電圖案187G連接。
仍參考圖3,導電圖案189P/導電圖案189G的(例如,沿圖3的Y方向量測的)寬度及/或(例如,沿圖3的X方向量測的)長度可小於、等於或大於導電圖案187P/導電圖案187G的彼等寬度及/或長度。圖3中通孔188的形狀為矩形,然而,亦可使用其他適合的形狀,諸如環形、卵形、線形、緊密間隔開的通孔的接地或類似形狀。
圖4A示出根據一實施例的IPD 180C的平面視圖。圖4B繪示圖4A的區域500的放大視圖,且圖4C示出沿圖4A的橫截面A-A的IPD 180C的橫截面視圖。
在圖4A中,IPD 180C的最頂部金屬化層187具有與圖2的導電圖案187P/導電圖案187G相同或類似的多個導電圖案187P/導電圖案187G。然而,IPD 180C的UBM結構189包括兩個梳形導電圖案。梳形導電圖案中的一者具有基部189PB,且多個指狀件189PF實體上連接至基部189PB。指狀件189PF彼此平行,且基部189PB實質上垂直於指狀件189PF,如圖4A中所示出。在所示出的實施例中,指狀件189PF平行於導電圖案187P,且與導
電圖案187P具有一對一對應關係。通孔188將指狀件189PF中的每一者電耦接至導電圖案187P中的各別一者。在圖4A的實例中,通孔188具有線形,例如具有較大的(沿圖4A的Y方向量測的)長度與(沿圖4A的X方向量測的)寬度的比率,諸如在2與50之間的範圍內。如圖4A中所示出,線形通孔188中的每一者重疊於對應指狀件189PF的高百分比(例如,約50%與約99%之間)的面積。線形通孔188的較大橫截面積可有利地減小所形成的IPD的電阻。
另一梳形導電圖案具有基部189GB,且多個指狀件189GF實體上連接至基部189GB。指狀件189GF彼此平行,且基部189GB實質上垂直於指狀件189GF,如圖4A中所示出。在所示出的實施例中,指狀件189GF平行於導電圖案187G,且與導電圖案187G具有一對一對應關係。通孔188將指狀件189GF中的每一者電耦接至導電圖案187G中的各別一者。
如圖4A中所示出,指狀件189PF與指狀件189GF交錯。在一些實施例中,指狀件189PF與指狀件189GF與彼此均勻地間隔開,且所有指狀件189PF/指狀件189GF可具有相同或類似的大小。在一些實施例中,相鄰指狀件189PF與指狀件189GF之間的距離D1可在約5微米與約50微米之間的範圍內。此外,在一些實施例中,梳形導電圖案的指狀件(例如指狀件189GF)的端部與另一梳形導電圖案的基部(例如基部189PB)之間的距離D2可在約5微米與約50微米之間的範圍內。
圖4B示出圖4A的區域500的放大視圖。如圖4B中所示出,指狀件(例如指狀件189GF)的寬度W1可在約5微米與約
50微米之間的範圍內。通孔188的側與指狀件(例如指狀件189GF)的對應側之間的距離S1可在約2微米與約20微米之間的範圍內,且通孔188的端部與指狀件(例如指狀件189GF)的對應端部之間的距離S2可在約2微米與約20微米之間的範圍內。此外,指狀件(例如指狀件189GF)的側與導電圖案(例如導電圖案187G)的對應側之間的距離S3可在約2微米與約20微米之間的範圍內。
圖4C示出IPD 180C的一部分的橫截面視圖。如圖4C中所示出,頂部金屬化層187的導電圖案187G及UBM結構189的指狀件189GF電耦接至接地墊184;且頂部金屬化層187的導電圖案187P及UBM結構189的指狀件189PF電耦接至電源墊182。
圖5A示出根據一實施例的IPD 180D的平面視圖。圖5B繪示圖5A的區域510的放大視圖,且圖5C示出沿橫截面B-B的圖5A的IPD 180D的橫截面視圖。
IPD 180D類似於圖4A中的IPD 180C,但通孔188的形狀不同。特定而言,梳形導電圖案的指狀件(例如指狀件189PF)中的每一者藉由多個通孔188電耦接至最頂部金屬化層187的各別導電圖案(例如導電圖案187P),其中通孔188中的每一者更包括緊密間隔開的通孔的群組,例如如圖5B中所示出的通孔188A/通孔188B/通孔188C/通孔188D。
在圖5B的放大視圖中,每一通孔188包含四個緊密間隔開的矩形通孔188A/通孔188B/通孔188C/通孔188D的群組。相同群組中的四個通孔可具有相同大小。四個通孔中的每一者的寬度T1可在約2微米與約10微米之間的範圍內,且四個通孔中的
每一者的寬度T2可在約2微米與約10微米之間的範圍內。群組中的相鄰通孔之間的沿圖5B的Y方向量測的距離S4可在約2微米與約10微米之間的範圍內,且群組中的相鄰通孔之間的沿圖5B的X方向量測的距離S5可在約2微米與約10微米之間的範圍內。此外,指狀件(例如指狀件189GF)的寬度W2可在約5微米與約50微米之間的範圍內。此外,通孔188的外部側與指狀件(例如指狀件189GF)的對應側之間的沿圖5B的X方向量測的距離S6可在約2微米與約10微米之間的範圍內。指狀件(例如指狀件189GF)的側與導電圖案(例如導電圖案187G)的對應側之間的沿圖5B的X方向量測的距離S7可在約2微米與約20微米之間的範圍內。在一些實施例中,設置於相同指狀件(例如指狀件189PF或指狀件189GF)上的兩個相鄰通孔188(各自包含緊密間隔開的通孔的群組)之間的距離在約2微米與約100微米之間,其中沿圖5A的Y方向在每一通孔188的中心之間量測所述距離。
圖5C示出IPD 180D的一部分的橫截面視圖。如圖5C中所示出,頂部金屬化層187的導電圖案187P及UBM結構189的指狀件189PF電耦接至電源墊182。圖5C亦繪示相同群組中的藉由如圖5A中所示出的橫截面B-B所切割的通孔188A及通孔188B。儘管在橫截面B-B中不可見,但UBM結構189的指狀件189GF經由另一通孔188電耦接至頂部金屬化層187的導電圖案187G,之後導電圖案187G經由通孔186電耦接至接地墊184。
圖6A示出根據一實施例的IPD 180E的平面視圖。圖6B繪示圖6A的區域520的放大視圖,且圖6C示出沿橫截面C-C的圖6A的IPD 180E的橫截面視圖。
在圖6A中,IPD 180E的最頂部金屬化層187具有與圖4A的導電圖案187P/導電圖案187G相同或類似的多個導電圖案187P/導電圖案187G。然而,IPD 180E的UBM結構189包括相關於圖4A的UBM結構189旋轉了90度的兩個梳形導電圖案。特定而言,梳形導電圖案的基部(例如基部189PB及基部189GB)與最頂部金屬化層187的導電圖案187P/導電圖案187G平行,且梳形導電圖案的指狀件(例如指狀件189PF及指狀件189GF)垂直於最頂部金屬化層187的導電圖案187P/導電圖案187G。
參考圖6A,梳形導電圖案中的每一者的基部(例如基部189PB或基部189GB)經由線形通孔188L電耦接至各別導電圖案(例如導電圖案187P或導電圖案187G)。在一些實施例中,線形通孔188L重疊於對應基部(例如基部189PB或基部189GB)的高百分比(例如,約50%與約99%之間)的面積。線形通孔188L的較大橫截面面積可有利地減小所形成的IPD的電阻。矩形通孔188G(例如,沿導電圖案187G中的每一者的縱向方向)形成於導電圖案187G上(例如正上方)且將指狀件189GF與導電圖案187G電連接。類似而言,矩形通孔188P(例如,沿導電圖案187P中的每一者的縱向方向)形成於導電圖案187P上(例如正上方)且將指狀件189PF與導電圖案187P電連接。
圖6B示出圖6A中的區域520的放大視圖。在圖6B中,指狀件(例如指狀件189PF)的寬度W3可在約5微米與約50微米之間的範圍內。矩形通孔188P的側與指狀件(例如指狀件189PF)的對應側之間的距離S8可在約2微米與約10微米之間的範圍內。矩形通孔188P的另一側與導電圖案(例如導電圖案187P)
的對應側之間的距離S9可在約2微米與約10微米之間的範圍內。
圖6C示出IPD 180E的一部分的橫截面視圖。如圖6C中所示出,頂部金屬化層187的導電圖案187P及UBM結構189的指狀件189PF電耦接至電源墊182。儘管在橫截面C-C中不可見,但UBM結構189的指狀件189GF經由另一通孔188電耦接至頂部金屬化層187的導電圖案187G,之後導電圖案187G經由通孔186電耦接至接地墊184。
圖7A示出根據一實施例的IPD 180F的平面視圖。圖7B繪示圖7A的區域530的放大視圖,且圖7C示出沿橫截面D-D的圖7A的IPD 180F的橫截面視圖。
參考圖7A,IPD 180F的導電圖案187P/導電圖案187G及梳形導電圖案(例如導電圖案189PB/導電圖案189PF及導電圖案189GB/導電圖案189GF)與圖6A中的IPD 180E的彼等導電圖案187P/導電圖案187G及梳形導電圖案(例如導電圖案189PB/導電圖案189PF及導電圖案189GB/導電圖案189GF)相同或類似。與圖6A相比,已使用緊密間隔開的通孔(見圖7B中的通孔188A/通孔188B/通孔188C/通孔188D)的群組來替換圖6A中的矩形通孔188P/通孔188G中的每一者。緊密間隔開的通孔的大小及緊密間隔開的通孔之間的間隔可與圖5B中所示出的彼等大小及間隔相同或類似,不重複細節。
現參考圖7B,指狀件(例如指狀件189PF)的寬度W4可在約5微米與約50微米之間的範圍內。緊密間隔開的通孔的群組188的外部側與指狀件(例如指狀件189PF)的對應側之間的距離S10可在約2微米與約10微米之間的範圍內。指狀件(例如
指狀件189PF)的側與導電圖案(例如導電圖案187P)的對應側之間的距離S11可在約2微米與約10微米之間的範圍內。
圖7C示出IPD 180F的一部分的橫截面視圖。如圖7C中所示出,頂部金屬化層187的導電圖案187P及UBM結構189的指狀件189PF電耦接至電源墊182。圖7C亦繪示通孔的相同群組中的藉由橫截面D-D所切割的通孔188A及通孔188B。儘管在橫截面D-D中不可見,但UBM結構189的指狀件189GF經由另一通孔188電耦接至頂部金屬化層187的導電圖案187G,之後導電圖案187G經由通孔186電耦接至接地墊184。
UBM結構189的各種實施例設計改良IPD的效能。舉例而言,帶形UBM結構(見例如圖2及圖3)及梳形UBM結構(見例如圖4A、圖5A、圖6A以及圖7A)提供高覆蓋度比率,所述比率允許在UBM結構與IPD的最頂部金屬化層187的導電圖案187P/導電圖案187G之間形成高密度通孔(例如通孔188),因而減小所形成的IPD的等效串聯電阻(equivalent series resistance;ESR)。在一些實施例中,覆蓋度比率(例如,UBM結構189的面積的總和與導電圖案187的面積的總和之間的比率)在約0.1與約0.99之間,且通孔的密度(例如,通孔188的面積的總和與UBM結構189的面積的總和之間的比率)在約0.1與約0.99之間。此外,藉由帶形UBM結構的交錯的導電圖案189P/導電圖案189G或藉由梳形UBM結構的交錯的指狀件189PF/指狀件189GF提供的交錯的電源/接地圖案對電流路徑(例如穿過導電圖案189P/導電圖案189G、通孔188以及導電圖案187P/導電圖案187G的路徑)進行分路,因而減小所形成的IPD的等效串聯電感(equivalent
series inductance;ESL)。
圖8至圖12中示出UBM結構設計的額外實施例。特定而言,圖8至圖12各自示出針對IPD 180的UBM結構189的實施例設計的平面視圖。在圖8至圖12中的每一者中,IPD的頂部金屬化層187具有交錯的導電圖案187P/導電圖案187G,其中導電圖案187P經組態以電耦接至電源供應器電壓,且導電圖案187G經組態以電耦接至參考電壓(例如電接地)。
在圖8中,UBM結構189具有導電圖案189P及導電圖案189G,所述導電圖案189P及導電圖案189G藉由通孔188分別電耦接至導電圖案187P及導電圖案187G。圖8中的通孔188中的每一者包括緊密間隔開的通孔的陣列。導電圖案189G/導電圖案189P的寬度D4小於導電圖案189G與導電圖案189P之間的距離D3,如圖8中所示出。
在圖9中,UBM結構189具有導電圖案189P及導電圖案189G,所述導電圖案189P及導電圖案189G藉由通孔188分別電耦接至導電圖案187P及導電圖案187G。在一些實施例中,圖9中的通孔188中的每一者的(沿D6的方向量測的)寬度在導電圖案189P/導電圖案189G的寬度D6的約50%與99%之間。導電圖案189G/導電圖案189P的寬度D6大於導電圖案189G與導電圖案189P之間的距離D5,如圖9中所示出。
圖10示出具有梳形導電圖案的UBM結構,所述梳形導電圖案具有垂直於頂部金屬化層的底層導電圖案187P/導電圖案187G的指狀件189PF/指狀件189GF。與圖6A的UBM結構180E相比,圖10中的梳形導電圖案中的一者具有指狀件(例如最右指
狀件189GF),所述指狀件寬於連接至基部189GB的其他兩個指狀件(例如,左側的及中間的指狀件189GF)。此外,基部(例如基部189GB、基部189PB)中的每一者具有延伸超出其所連接至的指狀件的邊界的端部部分188E。
圖11示出具有梳形導電圖案的UBM結構,所述梳形導電圖案具有與頂部金屬化層的底層導電圖案187P/導電圖案187G平行的指狀件189PF/指狀件189GF。在圖11中,線形通孔188與對應底層導電圖案187G/導電圖案187P實質上交疊(例如交疊50%與約99%之間)。此外,線形通孔188延伸至基部(例如基部189GB、基部189PB)區域中且與基部的部分交疊。在一些實施例中,最外指狀件(例如,圖11中的最頂部指狀件189PF及圖11中的最下部指狀件189GF)寬於最外指狀件之間的內指狀件(例如指狀件189PF及指狀件189GF)。
圖12示出具有與頂部金屬化層的底層導電圖案187P/導電圖案187G平行的交錯的帶形導電圖案189P及導電圖案189F的UBM結構。在圖12的實例中,最頂部導電圖案189P及最底部導電圖案189G具有寬度WL,所述寬度WL大於設置於所述最頂部導電圖案189P與最底部導電圖案189G之間的導電圖案189P/導電圖案189G的寬度WS。在一些實施例中,寬度WL在約5微米與約50微米之間,且寬度WS在約5微米與約50微米之間。
執行模擬來分析圖8至圖12中所示出的不同實施例設計的效能。在100兆赫(MHz)的頻率下模擬具有圖8至圖12的UBM結構的IPD 180的ESR及ESL。在模擬中,假定ESR及ESL隨UBM結構的厚度而增大。在模擬中模擬IPD 180的自最頂部金
屬化層187至UBM結構189的層。可將圖8的UBM結構用作基準設計(baseline design)以與針對UBM結構的其他設計相比。模擬繪示具有18微米的厚度時,圖8的UBM結構具有0.38毫歐(mΩ)的ESR及1.40皮亨(pH)的ESL。具有18微米的厚度時,圖9的UBM結構具有0.06毫歐的ESR及0.81皮亨的ESL;具有35微米的厚度時,圖9的UBM結構具有0.10毫歐的ESR及2.08皮亨的ESL。使用UBM結構的35微米的厚度來執行針對圖10至圖12的UBM結構的模擬,且在期間觀測ESR及ESL的改良。舉例而言,圖10的UBM結構具有0.19毫歐的ESR及0.96皮亨的ESL,圖11的UBM結構具有0.10毫歐的ESR及0.79皮亨的ESL,以及圖12的UBM結構具有0.08毫歐的ESR及0.66皮亨的ESL。
在一些實施例中,根據最頂部金屬化層187的導電圖案187P/導電圖案187G的設計來設計IPD所貼合至的InFO封裝體1100的最頂部RDL 131(見圖1),以進一步減小IPD的ESL。圖13A、圖13B、圖14A、圖14B、圖15、圖16、圖17A以及圖17B示出繪示最頂部RDL 131及最頂部金屬化層187的導電圖案187P/導電圖案187G的設計以及最頂部RDL 131與最頂部金屬化層187的導電圖案187P/導電圖案187G之間的相互作用的各種實施例。
圖13A示出在一實施例中的繪示InFO封裝體1100的最頂部RDL 131、InFO封裝體1100的重佈線結構140的通孔132(見圖1)、InFO封裝體1100的UBM結構149(見圖1)的導電圖案149P/導電圖案149G,以及IPD 180的最頂部金屬化層187的導電圖案187P/導電圖案187G的平面視圖。出於清楚起見,圖13A中未示出所有特徵。如先前所論述,InFO封裝體的UBM結構149
的導電圖案149P/導電圖案149G可匹配IPD的UBM結構189的導電圖案189P/導電圖案189G(例如,與所述導電圖案189P/導電圖案189G具有相同形狀及/或相同大小)。舉例而言,在平面視圖中,導電圖案149P中的每一者匹配各別導電圖案189P,且(例如,藉由焊料區173)電耦接至各別導電圖案189P。類似而言,導電圖案149G中的每一者匹配各別導電圖案189G,且(例如,藉由焊料區173)電耦接至各別導電圖案189G。
在圖13A中,最頂部RDL 131具有與導電圖案131G交錯的導電圖案131P。導電圖案131P藉由通孔132電耦接至導電圖案149P,且導電圖案131G藉由通孔132電耦接至導電圖案149G。如圖13A中所示出,導電圖案131P/導電圖案131G垂直於導電圖案187P/導電圖案187G。換言之,導電圖案131P/導電圖案131G的縱向軸垂直於導電圖案187P/導電圖案187G的縱向軸。
圖13B示出沿橫截面E-E的圖13A的橫截面視圖。出於清楚起見,圖13B中僅示出InFO封裝體1100的接近IPD的部分。圖13B繪示UBM結構149的交錯的導電圖案149P/導電圖案149G。虛線箭頭線211(例如虛線箭頭線211A、虛線箭頭線211B)示出自(例如,連接至電源供應器的)電源圖案149P至(例如,連接至電接地的)接地圖案149G的電流路徑。在一些實施例中,如藉由電流路徑211A所示出,電流經由通孔132(在橫截面E-E中不可見)自電源圖案149P流動至最頂部RDL層131的導電圖案131G,且經由另一通孔132流動返回至接地圖案149G。在一些實施例中,如藉由電流路徑211B所示出,電流經由通孔132/通孔134(在橫截面E-E中不可見)自電源圖案149P流動至最頂
部RDL 131下方(例如,比RDL 131更靠近晶粒120)的RDL層,且經由另一通孔134、導電圖案131G以及另一通孔132流動返回至接地圖案149G。
圖14A繪示類似於圖13A的另一實施例設計的平面視圖,但具有與導電圖案187P/導電圖案187G平行的導電圖案131P/導電圖案131G。圖14B示出沿圖14A中的橫截面F-F的橫截面視圖。類似於圖13B,圖14B中的虛線箭頭線211示出電流路徑。在一些實施例中,藉由使導電圖案131P/導電圖案131G垂直於導電圖案187P/導電圖案187G,圖13A中的導電圖案131P/導電圖案131G的設計藉由對最頂部RDL 131與最頂部金屬化層187之間的電流路徑進行分路來進一步減小ESL。
圖15及圖16示出針對InFO封裝體的最頂部RDL 131及IPD的最頂部金屬化層187的兩個額外實施例設計。在圖15中,導電圖案131P/導電圖案131G與UBM結構149的導電圖案149P/導電圖案149G具有相同大小及相同形狀,因此在圖15的平面視圖中,導電圖案131P/導電圖案131G與導電圖案149P/導電圖案149G完全交疊。此外,由於圖15的導電圖案149P/導電圖案149G匹配IPD的UBM結構189的導電圖案189P/導電圖案189G(例如,具有相同形狀及相同大小),故導電圖案131P/導電圖案131G亦匹配UBM結構189的導電圖案189P/導電圖案189G(例如,具有相同大小及相同形狀)。如圖15中所示出,導電圖案131P/導電圖案131G垂直於IPD的最頂部金屬化層187的導電圖案187P/導電圖案187G。在圖16中,導電圖案131P/導電圖案131G亦垂直於IPD的導電圖案187P/導電圖案187G,但與導電圖案
149P/導電圖案149G具有不同形狀。
圖17A示出針對InFO封裝體的最頂部RDL 131及IPD的最頂部金屬化層187的另一實施例設計。在圖17A中,最頂部RDL 131包括與UBM結構149的梳形導電圖案(例如導電圖案149PB/導電圖案149PF、導電圖案149GB/導電圖案149GF)完全交疊的梳形導電圖案(例如導電圖案131PB/導電圖案131PF、導電圖案131GB/導電圖案131GF)。舉例而言,最頂部RDL 131的梳形導電圖案包含連接至指狀件131PF(或指狀件131GF)的基部131PB(或基部131GB)。類似而言,UBM結構149的梳形導電圖案包含連接至指狀件149PF(或指狀件149GF)的基部149PB(或基部149GB)。
圖17B示出沿橫截面G-G的圖17A的橫截面視圖。類似於圖13B,圖17B亦示出電流路徑211。藉由例如UBM結構149的梳形UBM圖案的交錯的指狀件149PF/指狀件149GF與最頂部RDL 131的交錯的指狀件(例如指狀件131GF/指狀件131PF)所提供的交錯的電源/接地圖案,以提供將電流路徑分路至InFO封裝體中的多個平行導電路徑,因而進一步減小所形成的IPD的ESL。其他實施例設計中的多個平行導電路徑(諸如圖13B及圖14B中所示出的彼等導電路徑)可由於類似原因而減小ESL。
圖18為示出藉由多個電感器的並聯耦接來減小電感的電路圖。在圖18的實例中,將多個電感器215並聯耦接。如本領域的技術人員易於瞭解的,多個並聯連接的電感器215的等效電感小於電感器215中的任一者的電感。舉例而言,若將各自具有電感L的五個電感器215並聯連接,則並聯連接的電感器215的等
效電感為L/5。此可進一步解釋藉由使用交錯的電源/接地圖案來減小ESL的原因,如上文所論述。
圖19及圖20示出對InFO封裝體1100的UBM結構149的導電圖案149P/導電圖案149G進行各種修改以解決某些製造問題。舉例而言,由於特徵大小在半導體製造中持續縮減,故兩個相鄰導電圖案149P與導電圖案149G之間的間距可能非常小,以致當使用焊料將導電圖案149P/導電圖案149G接合至IPD 180的導電圖案189P/導電圖案189G時,可發生焊料橋接問題。焊料橋接導致電短路,此可導致所形成的半導體元件發生故障及/或損壞。製造期間的另一問題為所謂的預填充空隙問題,其中當使用底填充材料(圖1中未示出)來填充InFO封裝體1100與IPD 180之間的間隔時,空隙(例如空白間隔)可形成於導電圖案之間(例如,導電圖案149P與導電圖案149G之間,或導電圖案189P與導電圖案189G之間)。
圖19示出經修改的帶形導電圖案149P'/導電圖案149G'。如圖19中所示出,經放大導電圖案221(例如,諸如銅圖案的金屬圖案,或銅墊)形成於導電圖案149P/導電圖案149G中的每一者的端部處,以形成經修改的導電圖案149P'/導電圖案149G'。經放大導電圖案221有助於在接合期間吸收所施加的多餘焊料,因而減少或避免焊料橋接問題。可在與用來形成原始導電圖案149P/導電圖案149G的相同處理步驟中形成經放大導電圖案221。導電圖案221的形狀可以是圓形、卵形、淚形、矩形或任何適合的形狀。在一些實施例中,經放大導電圖案221的寬度或直徑在約5微米與約100微米之間。
圖20示出其他經修改的導電圖案149P"/導電圖案149G"。導電圖案149P"/導電圖案149G"類似於圖19中的導電圖案149P'/導電圖案149G',但由多個分段帶來替換帶形導電圖案149P/導電圖案149G中的每一者,所述分段帶可具有在相同線(例如,原始導電圖案149P/導電圖案149G的縱向軸線)上對準的縱向軸。分段帶之間的開口允許底填充材料更好地流動至相鄰導電圖案149P"/導電圖案149G"之間的間隔中,因而減少或避免預填充空隙問題。在一些實施例中,藉由使用針對圖19及圖20中所示出的導電圖案(例如導電圖案149P'/導電圖案149G'、導電圖案149P"/導電圖案149G")的經修改的設計,歸因於經修改的設計中的經放大導電圖案221及/或分段帶,InFO封裝體的UBM結構149的導電圖案不再匹配IPD的UBM結構189的導電圖案(例如導電圖案189P/導電圖案189G)。
圖19及圖20使用帶形導電圖案作為實例。然而,亦可以梳形導電圖案來使用所述原理。舉例而言,經放大區域可形成於UBM結構149的梳形導電圖案的每一指狀件的端部處。此外,可由多個分段帶替換每一指狀件。此等及其他修改全部意欲包含於本揭露內容的範疇內。
圖21及圖22示出一些實施例中的針對IPD 180的UBM結構189的各種經修改的設計。圖21繪示具有基部189B及貼合至基部189B的指狀件189FA/指狀件189FB/指狀件189FC的梳形導電圖案。此外,圖21示出另一梳形導電圖案的兩個指狀件189FD及指狀件189FE。在極簡設計中,所有指狀件及基部可具有相同寬度D5,所述寬度可在5微米與約50微米之間的範圍內。然而,
由於特徵大小持續縮減,焊料橋接變得較可能,尤其在指狀件鄰接基部的區域中。
為解決焊料橋接問題,將梳形導電圖案的基部189B加寬以具有寬度D7,所述寬度可在約5微米與約100微米之間的範圍內。加寬基部189B使焊料擴散開,因而減少焊料橋接問題。此外,可將連接至基部189B的端部的指狀件中的一者(諸如指狀件189FA)加寬以具有寬度D6,所述寬度可在約5微米與約100微米之間的範圍內。當指狀件189FA靠近另一相鄰導電特徵(例如另一導電圖案)時,將指狀件189FA加寬可尤其有用。為進一步減少焊料橋接,可將指狀件189FD/指狀件189FE的端部與基部189B之間的距離S13增大至約5微米與約100微米之間的值,同時可將相鄰指狀件之間的距離S12保持在約5微米與約50微米之間的較小值上。
圖22示出針對IPD 180的UBM結構189的另一經修改的設計。圖22中的UBM結構189的導電圖案類似於圖21的彼等導電圖案,但有修改。特定而言,梳形導電圖案的基部189B與指狀件具有相同寬度D5。此外,延伸區域231形成為接近於指狀件鄰接基部189B之處。延伸區域231可以是在與用來形成梳形導電圖案的相同處理步驟處形成的導電圖案(例如,諸如銅圖案的金屬圖案)。延伸區域231的長度L可在約5微米與約100微米之間的範圍內。延伸區域231的寬度D9可在約5微米與約100微米之間的範圍內,以使得寬度D8在約10微米與約200微米之間的範圍內,寬度D8為寬度D5與寬度D9的總和。出於說明目的,將延伸區域231的形狀示出為矩形,但亦可使用其他適合的形狀,諸
如卵形、環形、軌道形(在矩形的相對端部處具有半圓的矩形)或類似形狀。在一些實施例中,藉由使用針對圖21及圖22中所示出的梳形導電圖案的經修改的設計,IPD的UBM結構189的梳形導電圖案不再匹配InFO封裝體的UBM結構149的梳形導電圖案(例如導電圖案149PB/導電圖案149PF、導電圖案149GB/導電圖案149GF)。
圖23示出一些實施例中的包括底部封裝體1100'、頂部封裝體160以及IPD 180的半導體封裝體1300的橫截面視圖。圖1中所示出的半導體封裝體1200可對應於圖23中所示出的半導體封裝體1300的一部分。
在圖23中,將IPD 180貼合至底部封裝體1100',IPD 180可以是上文所揭露的IPD(例如IPD 180A、IPD 180B、IPD 180C、IPD 180D、IPD 180E以及IPD 180F)中的任一者,底部封裝體1100'為InFO封裝體,諸如圖1的InFO封裝體1100。底部封裝體1100'具有前側重佈線結構140與背側重佈線結構110之間的晶粒120。前側重佈線結構140可與圖1的重佈線結構140相同或類似,且背側重佈線結構110包含形成於一或多個介電層(例如介電層111/介電層113)中的導電特徵(例如導電線114及通孔)。模塑材料130形成於前側重佈線結構140與背側重佈線結構110之間。諸如銅柱的導電柱119形成於模塑材料130中。導電柱119將前側重佈線結構140與背側重佈線結構110電耦接。
仍參考圖23,將可以是記憶體封裝體的頂部封裝體160經由導電接頭168接合至底部封裝體1100'。如圖23中所示出,頂部封裝體160具有基底161及貼合至基底161的上部表面的一
或多個半導體晶粒162(例如記憶體晶粒)。在一些實施例中,基底161包含矽、砷化鎵、絕緣體上矽(「silicon on insulator;SOI」)或其他類似材料。在一些實施例中,基底161為多層電路板。在一些實施例中,基底161包含雙馬來醯亞胺三嗪(bismaleimide triazine;BT)樹脂、FR-4(由具有耐火的環氧樹脂黏合劑的編織玻璃纖維布構成的複合材料)、陶瓷、玻璃、塑膠、載帶、膜或其他支撐材料。基底161可包含形成於基底161中/基底161上的導電特徵(例如導電線及通孔)。如圖23中所示出,基底161具有形成於基底161的上部表面及下部表面上的導電墊163,導電墊163電耦接至基底161的導電特徵。一或多個半導體晶粒162藉由例如接合線167電耦接至導電墊163。模塑材料165形成於基底161上及半導體晶粒162周圍,所述模塑材料可包括環氧樹脂、有機聚合物、聚合物或類似者。在一些實施例中,模塑材料165可與基底161相接,如圖23中所示出。
在一些實施例中,執行回焊製程以將半導體封裝體160電耦接及機械耦接至背側重佈線結構110。導電接頭168形成於導電墊163與導電特徵114之間。在一些實施例中,導電接頭168包括焊料區、導電柱(例如,在銅柱的至少端部表面上具有焊料區的銅柱),或任何其他適合的導電接頭。
對各種所揭露實施例的修改為可能的且全部意欲包含於本揭露內容的範疇內。舉例而言,可將帶形導電圖案(例如導電圖案187P/導電圖案187G、導電圖案189P/導電圖案189G)的數目及梳形導電圖案的指狀件的數目修改成任何適合的數目。作為另一實例,最頂部金屬化層187的各種導電圖案(例如導電圖案
187P/導電圖案187G)的寬度及長度可相對於UBM結構189的對應導電圖案(例如導電圖案189P/導電圖案189G)的彼等寬度及長度來調節(例如等於、小於或大於),因此不限於各種實施例中所示出的寬度及長度。各種實施例中的通孔(例如通孔188)的形狀可以是除所示出的形狀之外的任何適合的形狀。此外,雖然將圖19及圖20中的導電圖案描述為針對InFO封裝體的UBM結構149的設計,但亦可將此等設計應用於IPD的UBM結構189。反之,可將用於圖21至圖22中所示出的IPD的導電圖案應用於InFO封裝體的UBM結構149。
實施例可達成優點。舉例而言,IPD的帶形UBM結構189(見例如圖2及圖3)及IPD的梳形UBM結構189(見例如圖4A、圖5A、圖6A以及圖7A)提供高覆蓋度比率,所述比率允許在UBM結構189與IPD的最頂部金屬化層187之間形成高密度通孔,因而減小所形成的IPD的ESR。此外,藉由帶形UBM結構189的交錯的導電圖案189P/導電圖案189G或藉由梳形UBM結構189的交錯的指狀件189PF/指狀件189GF所提供的交錯的電源/接地圖案對電流路徑進行分路,以減小所形成的IPD的ESL。諸如圖19至圖22中所示出的經修改的UBM導電圖案以減少焊料橋接及/或預填充空隙,因而改良所形成的半導體元件的可靠度及製造良率。
圖24示出根據一些實施例的製造半導體元件的方法3000的流程圖。應理解,圖24中所示出的實施例方法僅為諸多可能的實施例方法的實例。於本領域具有通常知識者將認識到諸多變化、替代物以及修改。舉例而言,可添加、移除、替換、重新
配置以及重複如圖24中所示出的各種步驟。
參考圖24,在步驟3010中,內連線結構形成於基底上的被動元件上,內連線結構電耦接至被動元件,內連線結構的頂部金屬化層包括第一金屬圖案及平行於第一金屬圖案的第二金屬圖案。內連線結構可以是例如圖1中的內連線結構199,且被動元件可以是例如被動元件183。內連線結構的頂部金屬化層187可包含彼此平行的第一金屬圖案(例如金屬圖案187P)及第二金屬圖案(例如金屬圖案187G)。在步驟3020中,第一凸塊下金屬化(UBM)結構形成於內連線結構上,第一UBM結構包括第一金屬帶及平行於第一金屬帶的第二金屬帶,第一金屬帶電耦接至第一金屬圖案中的各別一者,且第二金屬帶電耦接至第二金屬圖案中的各別一者。第一UBM結構(例如UBM結構189)可包含彼此平行的第一金屬帶(例如金屬帶189P、金屬帶189PF或金屬帶189GF)及第二金屬帶(例如金屬帶189G、金屬帶189PF或金屬帶189GF)。第一金屬帶及第二金屬帶可藉由例如通孔188電耦接至各別金屬圖案(例如金屬圖案187P或金屬圖案187G)。第一金屬帶(例如金屬帶189P)可平行(見例如圖2)於第一金屬圖案(例如金屬圖案187P),或可垂直(見例如圖3)於第一金屬圖案。
在一實施例中,半導體封裝體包含積體被動元件(IPD),所述積體被動元件包含:一或多個被動元件,位於第一基底上;以及金屬化層,位於一或多個被動元件上且電耦接至一或多個被動元件,其中金屬化層的最頂部金屬化層包含第一多個導電圖案以及與第一多個導電圖案交錯的第二多個導電圖案。IPD亦包含位於最頂部金屬化層上的第一凸塊下金屬化(UBM)結構,其中
第一UBM結構包含:第一多個導電帶,所述第一多個導電帶中的每一者電耦接至第一多個導電圖案中的各別一者;以及第二多個導電帶,與第一多個導電帶交錯,所述第二多個導電帶中的每一者電耦接至第二多個導電圖案中的各別一者。在一實施例中,第一多個導電帶被配置為電耦接至電源供應器,且第二多個導電帶被配置為電耦接至參考電壓。在一實施例中,第一多個導電圖案與第一多個導電帶平行。在一實施例中,IPD的第一UBM結構更包含:第一導電帶,垂直於第一多個導電帶,第一導電帶與第一多個導電帶處於相同平面,第一導電帶實體上連接至第一多個導電帶;以及第二導電帶,垂直於第二多個導電帶,第二導電帶與第二多個導電帶處於相同平面,第二導電帶實體上連接至第二多個導電帶。在一實施例中,第一多個導電圖案垂直於第一多個導電帶。在一實施例中,IPD的第一UBM結構更包含:第一導電帶,垂直於第一多個導電帶,第一導電帶與第一多個導電帶處於相同平面,第一導電帶實體上連接至第一多個導電帶;以及第二導電帶,垂直於第二多個導電帶,第二導電帶與第二多個導電帶處於相同平面,第二導電帶實體上連接至第二多個導電帶。在一實施例中,半導體封裝體更包含積體扇出型(InFO)封裝體,所述InFO封裝體包含:晶粒,嵌入於模塑材料中;重佈線結構,位於晶粒及模塑材料上,重佈線結構電耦接至晶粒,其中重佈線結構的頂部重佈線層包含第三多個導電圖案以及與第三多個導電圖案交錯的第四多個導電圖案;以及第二UBM結構,位於重佈線結構上,第二UBM結構電耦接至重佈線結構的頂部重佈線層,第二UBM結構接合至第一UBM結構,第三多個導電圖案經由第二UBM結
構電耦接至第一多個導電圖案,第四多個導電圖案經由第二UBM結構電耦接至第二多個導電圖案。在一實施例中,第二UBM結構與第一UBM結構具有相同大小及相同形狀。在一實施例中,InFO封裝體的第二UBM結構包含:第三多個導電帶,電耦接至第一UBM結構的第一多個導電帶;以及第四多個導電帶,電耦接至第一UBM結構的第二多個導電帶,其中第三多個導電帶中的每一者包含沿線設置的非連續分段,且第四多個導電帶中的每一者包括沿線設置的非連續分段。在一實施例中,第三多個導電圖案平行於第一多個導電圖案,且第四多個導電圖案平行於第二多個導電圖案。在一實施例中,第三多個導電圖案垂直於第一多個導電圖案,且第四多個導電圖案垂直於第二多個導電圖案。
在一實施例中,半導體封裝體包含積體被動元件(IPD),所述積體被動元件包含:被動元件,位於基底上;內連線結構,位於被動元件及基底上,內連線結構的頂部金屬化層具有多個第一金屬圖案及平行於多個第一金屬圖案的多個第二金屬圖案,多個第二金屬圖案與多個第一金屬圖案交錯;以及第一凸塊下金屬化(UBM)結構,電耦接至內連線結構的頂部金屬化層,第一UBM結構具有多個第一金屬帶及平行於多個第一金屬帶的多個第二金屬帶,多個第二金屬帶與多個第一金屬帶交錯,多個第一金屬帶電耦接至多個第一金屬圖案,且多個第二金屬帶電耦接至多個第二金屬圖案。半導體封裝體更包含積體扇出型(InFO)封裝體,所述積體扇出型封裝體包含:晶粒,嵌入於模塑材料中;重佈線結構,位於模塑材料上,重佈線結構電耦接至晶粒;以及第二UBM結構,電耦接至重佈線結構,第二UBM結構的形狀匹配第一UBM
結構的形狀,第二UBM結構接合至第一UBM結構。在一實施例中,多個第一金屬帶與多個第一金屬圖案平行。在一實施例中,多個第一金屬帶垂直於多個第一金屬圖案。在一實施例中,IPD的第一UBM結構更包含實體上連接至多個第一金屬帶的第三金屬帶,其中第三金屬帶垂直於多個第一金屬帶,且其中第三金屬帶的寬度大於多個第一金屬帶中的至少一者的寬度。在一實施例中,InFO封裝體的重佈線結構的頂部重佈線層包含多個第三金屬圖案及多個第四金屬圖案,且其中多個第三金屬圖案的形狀匹配第一UBM結構的多個第一金屬帶的形狀,且多個第四金屬圖案的形狀匹配第一UBM結構的多個第二金屬帶的形狀。
在一實施例中,形成半導體封裝體的方法包含:在基底上的被動元件上形成內連線結構,內連線結構電耦接至被動元件,內連線結構的頂部金屬化層包括多個第一金屬圖案及平行於多個第一金屬圖案的多個第二金屬圖案;以及在內連線結構上形成第一凸塊下金屬化(UBM)結構,第一UBM結構包括多個第一金屬帶及平行於多個第一金屬帶的多個第二金屬帶,多個第一金屬帶電耦接至多個第一金屬圖案中的各別一者,且多個第二金屬帶電耦接至多個第二金屬圖案中的各別一者。在一實施例中,形成第一UBM結構包含使多個第一金屬帶形成為垂直於多個第一金屬圖案。在一實施例中,方法更包含將第一UBM結構接合至半導體封裝體的第二UBM結構,其中所述接合將多個第一金屬帶耦接至半導體封裝體的電源供應器,且將多個第二金屬帶耦接至半導體封裝體的電接地。在一實施例中,半導體封裝體包含電耦接至晶粒的重佈線結構,其中第二UBM結構電耦接至重佈線結
構,其中重佈線結構的位於晶粒遠端的頂部重佈線層包括多個第三金屬帶及平行於多個第三金屬帶的多個第四金屬帶,其中多個第三金屬帶與多個第一金屬圖案垂直。
前文概述若干實施例的特徵,以使本領域的技術人員可更好地理解本揭露內容的態樣。本領域的技術人員應理解,其可易於使用本揭露內容作為設計或修改用於實現本文中所引入的實施例的相同目的及/或達成相同優點的其他製程及結構的基礎。本領域的技術人員亦應認識到,此類等效構造並不脫離本揭露內容的精神及範疇,且本領域的技術人員可在不脫離本揭露內容的精神及範疇的情況下在本文中作出各種改變、替代以及更改。
120‧‧‧晶粒
128‧‧‧晶粒接點
129‧‧‧介電材料
130‧‧‧模塑材料
131、133、135‧‧‧導電線
132、134、136、138‧‧‧導通孔
140‧‧‧重佈線結構
142、144、146、148、191、193‧‧‧介電層
149、189‧‧‧UBM結構
173‧‧‧焊料區
180‧‧‧IPD
181‧‧‧基底
182、184‧‧‧墊
183A、183B‧‧‧被動元件
185、187‧‧‧金屬化層
186、188‧‧‧通孔
199‧‧‧內連線結構
1100‧‧‧InFO封裝體
1200‧‧‧半導體封裝體
Claims (13)
- 一種半導體封裝體,包括:積體被動元件,包括:一或多個被動元件,位於第一基底上;金屬化層,位於所述一或多個被動元件上且電耦接至所述一或多個被動元件,其中所述金屬化層的最頂部金屬化層包括:第一多個導電圖案;以及第二多個導電圖案,與所述第一多個導電圖案交錯;以及第一凸塊下金屬化結構,位於所述最頂部金屬化層上,其中所述第一凸塊下金屬化結構包括:第一多個導電帶,所述第一多個導電帶中的每一者電耦接至所述第一多個導電圖案中的各別一者;以及第二多個導電帶,與所述第一多個導電帶交錯,所述第二多個導電帶中的每一者電耦接至所述第二多個導電圖案中的各別一者。
- 如申請專利範圍第1項所述之半導體封裝體,其中所述第一多個導電帶被配置為電耦接至電源供應器,且所述第二多個導電帶被配置為電耦接至參考電壓。
- 如申請專利範圍第1項所述之半導體封裝體,其中所述第一多個導電圖案與所述第一多個導電帶平行或垂直。
- 如申請專利範圍第3項所述之半導體封裝體,其中所述積體被動元件的所述第一凸塊下金屬化結構更包括: 第一導電帶,垂直於所述第一多個導電帶,所述第一導電帶與所述第一多個導電帶處於相同平面,所述第一導電帶實體上連接至所述第一多個導電帶;以及第二導電帶,垂直於所述第二多個導電帶,所述第二導電帶與所述第二多個導電帶處於相同平面,所述第二導電帶實體上連接至所述第二多個導電帶。
- 如申請專利範圍第1項所述之半導體封裝體,更包括積體扇出型封裝體,所述積體扇出型封裝體包括:晶粒,嵌入於模塑材料中;重佈線結構,位於所述晶粒及所述模塑材料上,所述重佈線結構電耦接至所述晶粒,其中所述重佈線結構的頂部重佈線層包括:第三多個導電圖案;以及第四多個導電圖案,與所述第三多個導電圖案交錯;以及第二凸塊下金屬化結構,位於所述重佈線結構上,所述第二凸塊下金屬化結構電耦接至所述重佈線結構的所述頂部重佈線層,所述第二凸塊下金屬化結構接合至所述第一凸塊下金屬化結構,所述第三多個導電圖案經由所述第二凸塊下金屬化結構電耦接至所述第一多個導電圖案,所述第四多個導電圖案經由所述第二凸塊下金屬化結構電耦接至所述第二多個導電圖案。
- 如申請專利範圍第5項所述之半導體封裝體,其中所述積體扇出型封裝體的所述第二凸塊下金屬化結構包括:第三多個導電帶,電耦接至所述第一凸塊下金屬化結構的所 述第一多個導電帶;以及第四多個導電帶,電耦接至所述第一凸塊下金屬化結構的所述第二多個導電帶,其中所述第三多個導電帶中的每一者包括沿線設置的非連續分段,且所述第四多個導電帶中的每一者包括沿線設置的非連續分段。
- 一種半導體封裝體,包括:積體被動元件,包括:被動元件,位於基底上;內連線結構,位於所述被動元件及所述基底上,所述內連線結構的頂部金屬化層具有多個第一金屬圖案及平行於所述多個第一金屬圖案的多個第二金屬圖案,所述多個第二金屬圖案與所述多個第一金屬圖案交錯;以及第一凸塊下金屬化結構,電耦接至所述內連線結構的所述頂部金屬化層,所述第一凸塊下金屬化結構具有多個第一金屬帶及平行於所述多個第一金屬帶的多個第二金屬帶,所述多個第二金屬帶與所述多個第一金屬帶交錯,所述多個第一金屬帶電耦接至所述多個第一金屬圖案,且所述多個第二金屬帶電耦接至所述多個第二金屬圖案;以及積體扇出型封裝體,包括:晶粒,嵌入於模塑材料中;重佈線結構,位於所述模塑材料上,所述重佈線結構電耦接至所述晶粒;以及第二凸塊下金屬化結構,電耦接至所述重佈線結構,所述第二凸塊下金屬化結構的形狀匹配所述第一凸塊下金屬化 結構的形狀,所述第二凸塊下金屬化結構接合至所述第一凸塊下金屬化結構。
- 如申請專利範圍第7項所述之半導體封裝體,其中所述多個第一金屬帶與所述多個第一金屬圖案平行或垂直。
- 如申請專利範圍第8項所述之半導體封裝體,其中所述多個第一金屬帶與所述多個第一金屬圖案垂直,且所述積體被動元件的所述第一凸塊下金屬化結構更包括實體上連接至所述多個第一金屬帶的第三金屬帶,其中所述第三金屬帶垂直於所述多個第一金屬帶,且其中所述第三金屬帶的寬度大於所述多個第一金屬帶中的至少一者的寬度。
- 如申請專利範圍第7項所述之半導體封裝體,其中所述積體扇出型封裝體的所述重佈線結構的頂部重佈線層包括多個第三金屬圖案及多個第四金屬圖案,且其中所述多個第三金屬圖案的形狀匹配所述第一凸塊下金屬化結構的所述多個第一金屬帶的形狀,且所述多個第四金屬圖案的形狀匹配所述第一凸塊下金屬化結構的所述多個第二金屬帶的形狀。
- 一種形成半導體封裝體的方法,包括:在基底上的被動元件上形成內連線結構,所述內連線結構電耦接至所述被動元件,所述內連線結構的頂部金屬化層包括多個第一金屬圖案及平行於所述多個第一金屬圖案的多個第二金屬圖案;以及在所述內連線結構上形成第一凸塊下金屬化結構,所述第一凸塊下金屬化結構包括多個第一金屬帶及平行於所述多個第一金屬帶的多個第二金屬帶,所述多個第一金屬帶電耦接至所述多個 第一金屬圖案中的各別一者,且所述多個第二金屬帶電耦接至所述多個第二金屬圖案中的各別一者。
- 如申請專利範圍第11項所述之方法,其中形成所述第一凸塊下金屬化結構包括使所述多個第一金屬帶形成為垂直於所述多個第一金屬圖案。
- 如申請專利範圍第11項所述之方法,更包括:將所述第一凸塊下金屬化結構接合至半導體封裝體的第二凸塊下金屬化結構,其中所述接合將所述多個第一金屬帶耦接至所述半導體封裝體的電源供應器,且將所述多個第二金屬帶耦接至所述半導體封裝體的電接地。
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US10861841B2 (en) * | 2018-09-28 | 2020-12-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device with multiple polarity groups |
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US11616026B2 (en) * | 2020-01-17 | 2023-03-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method of manufacture |
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CN113347786B (zh) | 2020-02-18 | 2023-12-26 | 财团法人工业技术研究院 | 具导电通孔阵列基板的电子装置 |
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US10840227B2 (en) | 2020-11-17 |
CN109755192A (zh) | 2019-05-14 |
US20190131287A1 (en) | 2019-05-02 |
KR20190050282A (ko) | 2019-05-10 |
US20210074694A1 (en) | 2021-03-11 |
US11631658B2 (en) | 2023-04-18 |
CN109755192B (zh) | 2021-01-22 |
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