TWI708341B - 半導體封裝、半導體元件及形成半導體元件的方法 - Google Patents
半導體封裝、半導體元件及形成半導體元件的方法 Download PDFInfo
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- TWI708341B TWI708341B TW108105799A TW108105799A TWI708341B TW I708341 B TWI708341 B TW I708341B TW 108105799 A TW108105799 A TW 108105799A TW 108105799 A TW108105799 A TW 108105799A TW I708341 B TWI708341 B TW I708341B
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Abstract
一種半導體封裝,所述半導體封裝包含:具有第一凸塊下
金屬化(UBM)結構的半導體元件,其中第一UBM結構包含:多個第一導電條,第一導電條在第一方向上延伸;多個第二導電條,與多個第一導電條分離且交錯,第二導電條在第一方向上延伸,其中多個第一導電條在第一方向上以第一偏移距離與多個第二導電條偏移;以及基底,包含第二UBM結構,第二UBM結構包含多個第三導電條,多個第三導電條中的每一者接合至多個第一導電條中的一者或多個第二導電條中的一者。
Description
本發明的實施例是有關於一種半導體封裝、半導體元件及形成半導體元件的方法。
半導體產業歸因於對多種電子組件(例如電晶體、二極體、電阻器、電容器等)的積體密度(integration density)的持續改良而經歷快速發展。主要地,積體密度的此改良源自於最小特徵尺寸的迭代減小,其允許將更多組件整合至給定區域中。隨著近年來對甚至更小的電子元件的需求增長,已出現對於更小且更具創造性的半導體晶粒的封裝技術的需求。
本發明的實施例提供一種半導體封裝,包括:半導體元件,包括第一凸塊下金屬化結構,其中所述第一凸塊下金屬化結構包括:多個第一導電條,所述多個第一導電條在第一方向上延伸;以及多個第二導電條,與所述多個第一導電條分離且交錯,所述第
二導電條在所述第一方向上延伸,其中所述多個第一導電條在所述第一方向上以第一偏移距離與所述多個第二導電條偏移;以及基底,包括第二凸塊下金屬化結構,所述第二凸塊下金屬化結構包括多個第三導電條,所述多個第三導電條中的每一者經組態以接合至所述多個第一導電條中的一者或所述多個第二導電條中的一者。
本發明的實施例提供一種半導體元件,包括:積體被動元件,包括安置於所述積體被動元件的表面上的多個第一接合結構及多個第二接合結構,其中所述第一接合結構及所述第二接合結構具有第一長度,以及其中所述第一接合結構以第一偏移距離與所述第二接合結構偏移;及基底,包括安置於所述基底的表面上的多個第三接合結構及多個第四接合結構,其中所述第三接合結構及所述第四接合結構具有大於所述第一長度的第二長度,其中所述第三接合結構以第二偏移距離與所述第四接合結構偏移,其中所述多個第三接合結構中的每一者與所述多個第一接合結構中相對應一者接合。
本發明的實施例提供一種形成半導體元件的方法,包括:在半導體元件上方形成第一凸塊下金屬化結構的第一圖案,所述第一凸塊下金屬化結構的第一圖案包括平行導電條;在基底上方形成第二凸塊下金屬化結構的第二圖案,所述第二凸塊下金屬化結構的第二圖案包括平行導電條;在所述第一凸塊下金屬化結構上形成焊料材料;在所述第二凸塊下金屬化結構上方置放所述第一凸塊下金屬化結構,其中所述第一凸塊下金屬化結構中的每一者的第一末端與各別第二凸塊下金屬化結構的第一末端對準,以
及其中所述第一凸塊下金屬化結構中的每一者的第二末端與各別第二凸塊下金屬化結構的第二末端偏移;以及執行回焊製程以使所述焊料材料朝向所述各別第二凸塊下金屬化結構中的每一者的所述第二末端流動。
110、140:重佈線結構
111、113、142、144、146、148、191、193:介電層
114、133、135:導線
119:導電柱
120:晶粒
128:晶粒連接件
129:介電材料
130、165:模製材料
131:導線/重佈線層
132、134、136、138、186、188:通孔
149、189:凸塊下金屬化結構
160:頂部封裝
161、181:基底
162:半導體晶粒
163:導電墊
168:導電接點
173:焊料區域
180:積體被動元件
182:墊
183、183A、183B:被動元件
185、187:金屬化層
199:互連結構
200:接合頭部
202:焊料
204:焊劑材料
300、310、502、512、516:凸塊下金屬化圖案
301A、301B、301C、302A、302B、302C、303、311A、311B、311C、312A、312B、312C、313、、508、514、518、602、604:條
351、352:位置
504A:第一區段
504B:第二區段
1100:積體扇出型封裝
1100':底部封裝
1200、1300:半導體封裝
A-A、B-B、C-C、D-D:視圖
H1、H2:距離
L1、L2、L3、L4:長度
LD1、LD2、LD3:長度差
O1、O2、O3:偏移
OS1、OS2、OS3:偏移分離
P1、P2:節距
W1、W2、W3、W4:寬度
結合附圖閱讀以下詳細描述會最佳地理解本揭露的態樣。應注意,根據業界中的標準慣例,各種構件未按比例繪製。事實上,出於論述清楚起見,可任意地增大或減小各種構件的尺寸。
圖1示出根據一些實施例接合至積體扇出型(integrated fan-out;InFO)封裝的積體被動元件(Integrated Passive Device;IPD)的橫截面視圖。
圖2A至圖2B示出根據一些實施例將積體被動元件接合至積體扇出型封裝的中間步驟的橫截面視圖。
圖3A至圖3C示出根據一些實施例的凸塊下金屬化(Under-Bump Metallization;UBM)結構的圖案的平面視圖。
圖4示出根據一些實施例將積體被動元件接合至積體扇出型封裝的中間步驟的平面視圖。
圖5A至圖5B示出根據一些實施例的UBM結構的圖案的平面視圖。
圖6A至圖6D示出根據一些實施例的UBM結構的圖案的平面視圖。
圖7示出根據一些實施例的半導體封裝的橫截面視圖。
以下揭露內容提供用於實施本發明的不同特徵的多個不同實施例或實例。下文描述組件及配置的特定實例以簡化本揭露。當然,這些特定實例僅為實例且不意欲為限制性的。舉例而言,在以下描述中,第一構件在第二構件上方或第二構件上形成可包含第一構件與第二構件直接接觸地形成的實施例,且亦可包含可在第一構件與第二構件之間形成額外構件以使得第一構件與第二構件可不直接接觸的實施例。另外,本揭露可在各種實例中重複附圖標號及/或字母。此重複是出於簡單及清楚的目的,且本身並不指示所論述的各種實施例及/或組態之間的關係。
此外,為易於描述,可在本文中使用諸如「在...下面(beneath)」、「「在...下方(below)」、「下部(lower)」、「在...上方(above)」、「上部(upper)」及類似者的空間相對術語來描述如諸圖中所示出的一個元件或構件與另一元件或構件的關係。除諸圖中所描繪的定向以外,空間相對術語意欲涵蓋元件在使用或操作中的不同定向。設備可以其他方式定向(旋轉90度或處於其他定向),且本文中所使用的空間相對描述詞可同樣相應地進行解譯。
在半導體封裝,特別是包括接合至積體扇出型封裝的積體被動元件的半導體封裝的方法及結構的情形下論述本揭露的實施例。在一些實施例中,積體被動元件及積體扇出型封裝的凸塊下金屬化(UBM)結構包含條形構件。相較於在積體扇出型封裝的UBM結構中,條形構件在積體被動元件的UBM結構中可具有不同長度或不同佈置。在一些情況下,以此方式使用不同UBM結構可改良接合。
圖1示出根據一實施例的半導體封裝1200的部分的橫截面視圖。半導體封裝1200包含積體扇出型封裝1100及附接至積體扇出型封裝1100的積體被動元件180。如圖1中所示出,積體扇出型封裝1100包含可接合至積體被動元件180的一或多個相應UBM結構189的一或多個UBM結構149。如圖1中所示,UBM結構149可經由焊料區域173接合至UBM結構189。儘管圖1的橫截面視圖中僅繪示積體扇出型封裝1100的一個UBM結構149及積體被動元件180的一個UBM結構189,但在一些實施例中,積體扇出型封裝1100可包含多個UBM結構149,或積體被動元件180可包含多個UBM結構189。在一些實施例中,UBM結構149的數目與UBM結構189的數目相同。應注意,圖1中所示的各種構件僅出於說明的目的且不為限制性的,且其他形狀、組態或佈置亦為可能的。舉例而言,UBM結構189、UBM結構149或焊料區域173可包含分離區域。UBM結構189可以與所示不同的方式連接至積體扇出型封裝1100,且UBM結構149可以與所示不同的方式連接至積體被動元件180。下文中論述UBM結構189及UBM結構149的各種實施例。半導體封裝1200的這些及其他變化全部意欲包含於本揭露的範疇內。
如圖1中所示出,積體扇出型封裝1100包含嵌入於模製材料(molding material)130中的晶粒120(亦稱作半導體晶粒或積體電路(integrated circuit;IC)晶粒),以及形成於具有晶粒連接件128的晶粒120的前側上的重佈線結構140。重佈線結構140包含形成於重佈線結構140的一或多個介電層(例如142、144、146、148)中的導電構件,諸如導線(例如131、133、135)及通
孔(例如132、134、136、138)。UBM結構149可形成於重佈線結構140的最頂部介電層(例如142)上方且電性耦接至重佈線結構140。UBM結構149亦可經由重佈線結構140電性耦接至一或多個晶粒連接件128。如下文所描述,UBM結構149可經組態以接合至積體被動元件180的UBM結構189。
晶粒120可包含基底,諸如包含矽的半導體基底,可經摻雜或未經摻雜,或可為絕緣層上半導體(semiconductor-on-insulator;SOI)基底的主動層。基底可包含其他半導體材料,諸如鍺,化合物半導體,諸如碳化矽、砷化鎵、磷化鎵、氮化鎵、磷化銦、砷化銦或銻化銦、其組合或類似物。基底可包含二元、三元或四元化合物半導體,諸如SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP、GaInAsP、其組合或類似物。亦可使用其他類型的基底,諸如多層或具有分級摻雜或分級組成的基底。諸如電晶體(例如FinFET、MOSFET等)、二極體、電容器、電阻器、振盪器或其他主動或被動元件可形成於半導體基底中及/或半導體基底上且可藉由互連結構互連。互連結構可包含例如基底上的一或多個介電層中的金屬化圖案,進而形成積體電路。
晶粒120亦可包含藉以形成外部連接件的墊(未繪示),諸如鋁墊。墊可位於晶粒120的「主動側」(或「前側」)。鈍化膜(未繪示)可形成於晶粒120的前側處及墊的部分上。開口可形成為延伸穿過鈍化膜至墊,且諸如導電柱(其可包含諸如銅的金屬)的晶粒連接件128延伸至鈍化膜的開口中。以此方式,晶粒連接件128機械耦接且電性耦接至墊。晶粒連接件128可藉由例如鍍敷製程或類似製程而形成。晶粒連接件128經電性耦接至晶粒120
的積體電路。
介電材料129可形成於晶粒120的主動側上,諸如形成於鈍化膜或晶粒連接件128上。介電材料129可側向包封晶粒連接件128,且介電材料129可與晶粒120側向共端。介電材料129可為聚合物,諸如聚苯并噁唑(polybenzoxazole;PBO)、聚醯亞胺(polyimide)、苯并環丁烯(benzocyclobutene;BCB);氮化物,諸如氮化矽;氧化物,諸如氧化矽、磷矽酸鹽玻璃(phosphosilicate glass;PSG)、硼矽酸鹽玻璃(borosilicate glass;BSG)、硼摻磷矽酸鹽玻璃(boron-doped phosphosilicate glass;BPSG);另一類型的材料或其組合。介電材料129可例如藉由旋塗、層壓、化學氣相沉積(chemical vapor deposition,CVD)、物理氣相沉積(physical vapor deposition,PVD)、原子層沉積(atomic layer deposition,ALD)或類似者形成。
進一步參考圖1,圍繞晶粒120的模製材料130可包含以下材料:諸如環氧樹脂、有機聚合物、聚合物(經或未經添加有基於矽石的填充劑(filler)或玻璃填充劑)或另一類型的材料。可使用任何適合的形成方法來形成模製材料130,諸如晶圓級模製(wafer level molding)、壓縮模製(compressive molding)、轉移模製(transfer molding)或類似者。儘管未示出,但可在將晶粒120附接至載體的第一側之後形成模製材料130,其後,模製材料130形成於載體的第一側上方且晶粒120周圍。在一些實施例中,諸如基底穿孔(through-substrate via;TSV)的導電柱在形成模製材料130之前形成於載體的第一側上方。
如圖1中所示出,重佈線結構140形成於晶粒120及模
製材料130上方。在一些實施例中,重佈線結構140的一或多個介電層(例如142、144、146、148)由諸如上文針對介電材料129所描述實例的材料而形成,或可由另一材料形成。重佈線結構140的一或多個介電層可藉由合適的沉積製程而形成,諸如旋塗、CVD、層壓、類似者或其組合。
在一些實施例中,重佈線結構140的導電構件包含由合適的導電材料所形成的導線(例如131、133、135)及導電通孔(例如132、134、136、138),所述導電材料諸如銅、鈦、鎢、鋁、組合或類似物。在一些實施例中,重佈線結構140可藉由以下操作形成:形成介電層;在介電層中形成開口以暴露底層導電特徵;在介電層上方及開口中形成晶種層;在晶種層上方形成具有經設計圖案的圖案化光阻;將導電材料鍍敷(例如電鍍或無電式鍍覆)於經設計圖案中及晶種層上方;以及移除光阻及晶種層上未形成導電材料的晶種層部分。在一些實施例中,儘管重佈線結構140可使用金屬鑲嵌製程或雙金屬鑲嵌製程而形成,但形成重佈線結構140的其他方法亦為可能的且完全意欲包含於本揭露的範疇內。
意欲將圖1的重佈線結構140中的介電層及導電構件作為非限制性實例。舉例而言,其他數目的介電層及其他數目的導電構件的層亦為可能的且全部意欲包含於本揭露的範疇內。本文中的論述可將重佈線層(redistribution layer;RDL)131稱為重佈線結構140的最頂部RDL,且應理解,當在重佈線結構140中使用其他數目的RDL時,最頂部RDL指離晶粒120最遠的RDL。
圖1亦示出形成於積體扇出型封裝1100上方且經電性耦接至重佈線結構140的UBM結構149。在一些實施例中,UBM結
構149包含一或多種導電材料的一或多個層,諸如銀、金、鋁、鈀、鎳、鎳合金、鎢合金、鉻、鉻合金、類似物、另一金屬化材料或其組合。在一些實施例中,UBM結構149包含三個導電材料層,諸如鈦層、銅層以及鎳層。然而,存在許多合適的材料佈置及層佈置,諸如鉻/鉻銅合金/銅/金佈置、鈦/鈦鎢/銅佈置或銅/鎳/金佈置,所述材料佈置及層佈置適用於形成UBM結構149。可用於UBM結構149的任何適合的材料或材料層全部意欲包含於本揭露的範疇內。在一些情況下,UBM結構149可包含黏著層、障壁層及潤濕層,其可按所述次序佈置。
在一些實施例中,UBM結構149可藉由在重佈線結構140的最頂部介電層(例如142)中形成開口以暴露重佈線結構140的導電構件(例如銅線或銅墊)而形成。在形成開口之後,UBM結構149的材料可形成於開口中,UBM結構149的材料與經暴露導電特徵具有電接觸。舉例而言,UBM結構149可藉由在最頂部介電層(例如142)上方且穿過最頂部介電層至重佈線結構140的經暴露導電特徵沿開口的內部形成UBM結構149的每一層而形成。儘管每一層的形成可使用諸如電鍍或無電式鍍覆的鍍敷製程來執行,但可替代地使用諸如濺鍍、蒸鍍或電漿輔助化學氣相沉積(plasma enhanced chemical vapor deposition,PECVD)製程的其他形成製程。
如圖1中所示,積體被動元件180可包含基底181及一或多個被動元件183(例如183A及183B)。被動元件183可包含電容器、電阻器、電感器或其他被動元件,且可形成於基底181中或於基底181上。圖1中所示的被動元件183A及被動元件183B
為說明性實例,且在其他實施例中,被動元件183可包含較多、較少或不同的被動元件。在一些實施例中,積體被動元件180包含互連結構199,所述互連結構包含介電層(例如191、193)及形成於介電層中的金屬化層(例如185、187)。另外,互連結構199亦包含形成於介電層191及介電層193中的通孔(例如186、188)。UBM結構189形成於積體被動元件180的最頂部介電層(例如193)上方。UBM結構189經由互連結構199電性耦接至被動元件183。如圖1中所示,UBM結構189可藉由例如焊料區域173接合至UBM結構149。在一些實施例中,焊料區域173具有約0.5微米與約250微米之間的厚度。
積體被動元件180的基底181可為與上文針對晶粒120的基底所描述的相同或類似的基底,或可為不同類型的基底。被動元件183中的每一者可具有用於將被動元件183電性耦接至被動元件183外部的電路的墊182,諸如銅墊或鋁墊。可使用任何適合的方法來形成互連結構199,諸如上文所描述用於形成晶粒120的互連結構的方法。
如圖1中所示出,金屬化層185形成於被動元件183上方且與被動元件183電性耦接。金屬化層185可為例如連接至墊182的導線。金屬化層187形成於介電層191上方,且UBM結構189可形成於互連結構199的最頂部介電層(例如193)上方。通孔186可形成於金屬化層185與金屬化層187之間且將金屬化層185與金屬化層187電性耦接,且通孔188可形成於金屬化層187與UBM結構189之間且將金屬化層187與UBM結構189電性耦接。應注意,並非積體被動元件180的所有構件均在圖1的橫截
面視圖中可見。舉例而言,可在金屬化層185與基底181之間插入額外介電層。另外,圖1中所示出的UBM結構189及各種電連接件為說明性實例且不為限制性的。如下文中所論述,UBM結構189的各種設計及UBM結構189與互連結構199之間的各種電連接件為可能的。這些及其他修改全部意欲包含於本發明的範疇內。
圖1中的互連結構199具有作為說明性實例的兩個介電層191、介電層193以及兩個金屬化層185、金屬化層187。其他數目的介電層、其他數目的金屬化層以及其他數目的通孔亦為可能的且全部意欲包含於本揭露的範疇內。本文中的論述可將金屬化層187稱為互連結構199的(例如離基底181最遠的)最頂部金屬化層,且可將介電層193稱為互連結構199的最頂部介電層,且應理解,當在互連結構199中使用其他數目的介電層及其他數目的金屬化層時,最頂部金屬化層及最頂部介電層分別指代互連結構199離基底181最遠的金屬化層及介電層。
圖2A至圖2B示出根據一實施例將積體被動元件180接合至積體扇出型封裝1100以形成半導體封裝1200的中間步驟的橫截面視圖。圖2A至圖2B中所示的積體被動元件180包含UBM結構189,所述UBM結構可類似於先前所描述的積體被動元件180。圖2A至圖2B所示的積體扇出型封裝1100包含可類似於先前所描述的積體扇出型封裝1100的UBM結構149。圖2A繪示出積體被動元件180在取放過程的部分中藉由接合頭部200來固持。在其他實施例中,可使用其他技術以將積體被動元件180接合至積體扇出型封裝1100。
如圖2A中所示,焊料202形成於積體被動元件180的
UBM結構189上。焊料202的材料可包含共晶材料,且本文中詞語「焊料」的使用包含鉛系焊料及無鉛焊料兩者,諸如鉛系焊料的Pb-Sn組成物,無鉛焊料包含InSb、錫、銀以及銅(「SAC」)組成物,以及於電氣應用中具有共同熔點且形成導電焊料連接件的其他共晶材料。對於無鉛焊料,作為實例,可改變SAC焊料的組成物,諸如SAC 105(Sn 98.5%、Ag 1.0%、Cu 0.5%)、SAC 305以及SAC 405。諸如焊球的無鉛導電材料亦可由SnCu化合物形成,而無需使用銀(Ag)。無鉛焊料亦可包含錫與銀Sn-Ag,而無需使用銅。這些為實例,且可使用其他類型或組成的焊料202。焊料202可使用如本領域中已知的技術形成於UBM結構189上。
在圖2A中,焊劑材料204形成於積體扇出型封裝1110的UBM結構149上。焊劑材料204可藉由例如噴注製程(jetting process)、焊劑模印製程(flux stencil process)或另一製程而塗覆於UBM結構149的表面,且可形成至約1微米與約100微米之間的厚度。焊劑材料204可為例如免清潔焊劑(no-clean flux)或另一類型的焊劑。在一些情況下,焊劑材料204包含焊料材料或焊料膏。
在一些實施例中,焊劑材料204包含可改善後續形成的焊料區域173於UBM結構149或UBM結構189上方的連接的材料。舉例而言,焊劑材料204可藉由使UBM結構149或UBM結構189上的自然氧化物層脫氧來改善連接。焊劑材料204亦可具有其他特性或尺寸,或包含其他類型的材料。在一些情況下,類似於焊劑材料204的焊劑材料亦可形成於積體被動元件180的UBM結構189上。
圖2B繪示接合至積體扇出型封裝1100的積體被動元件180。在一些實施例中,在加工公差內,UBM結構149可在接合程序期間與UBM結構189對準。圖2B亦繪示在對焊料202執行回焊製程以形成焊料區域173之後的積體被動元件180及積體扇出型封裝1100。焊料區域173將積體被動元件180的UBM結構189接合且電性連接至積體扇出型封裝1100的UBM結構149。在一些情況下,在將積體被動元件180置放於積體扇出型封裝1100上之後但在執行回焊製程之前,可執行其他處理步驟。舉例而言,可對半導體封裝1200可能或可能未繪示於圖2A至圖2B中的部分執行其他處理步驟。
在一些實施例中,回焊製程包含將焊料202加熱至預定溫度,例如加熱至焊料202的材料的熔點。在回焊製程期間,焊料202經歷導致焊料202黏著至UBM結構189及UBM結構149的潤濕製程(wetting process)。在一些情況下,回焊製程可導致焊料202在UBM結構189或UBM結構149上展開。在一些實施例中,在回焊製程之後,焊劑材料204的部分經保留剩餘在焊料區域173的邊緣周圍。在一些實施例中,可隨後使用清潔製程來移除剩餘焊劑材料(未繪示)。
轉至圖3A至圖3C,繪示根據一實施例的UBM圖案300及UBM圖案310的平面視圖。圖3A的平面視圖由圖2A中所示的視圖A-A指示,圖3B的平面視圖由圖2A中所示的視圖B-B指示,且圖3C的平面視圖由圖2A中所示的視圖C-C指示(例如繪示UBM圖案300及UBM圖案310的交疊視圖)。如下文更詳細地描述,UBM圖案300包含多個UBM結構,且UBM圖案310亦
包含多個UBM結構。UBM圖案300經組態以例如藉由焊料區域173接合至UBM圖案310。在圖3A至圖3C中,出於清楚起見,一些構件未繪示。如先前所描述,UBM圖案300或UBM圖案310中的一些或全部可類似於積體被動元件180的UBM結構189,或可類似於積體扇出型封裝1100的UBM結構149。雖然UBM圖案300、UBM圖案310以及下文所描述的UBM結構的其他圖案在其他實施例中可安置於積體被動元件180上或積體扇出型封裝1100上,出於清楚起見,UBM圖案300經描述為安置於積體被動元件180上,且UBM圖案310經描述為安置於積體扇出型封裝1100上。UBM圖案300、UBM圖案310包含多個分離狹長或條形UBM結構(在本文中稱為「條」),但在一些實施例中,本文中所描述的UBM結構可具有不為「條形」的構件。如下文所描述,UBM圖案300及UBM圖案310各自包含相對於相同UBM圖案的條或相對於另一UBM圖案的條具有不同長度或位置的條組。圖3A至圖3C以及其他圖中所示的條的佈置為說明性實例,且本文中所描述的UBM圖案在不背離本揭露的範疇的情況下,可具有比所繪示更多的條、更少的條或不同條特徵、大小或佈置。假定本文中所描述的尺寸及相對尺寸在加工公差內。另外,儘管在將積體被動元件接合至積體扇出型封裝的情形中描述本文中的UBM圖案、UBM結構以及技術,但UBM圖案、UBM結構以及技術可用於接合其他結構、封裝、元件、IC、晶圓以及類似物,且所有此類情形均在本揭露的範疇內。
圖3A中所示的UBM圖案300包含條301A至301C、條302A至302C以及條303。圖3B中所示的UBM圖案310包含條
311A至311C、條312A至312C以及條313。在一些情況下,可將條301A至301C、條302A至302C、條311A至311C以及條312A至312C各自視為不同的條組。在一些實施例中,UBM圖案可包含比所繪示更多的條組。在圖3A中所示的實施例中,條301A至301C與條302A至302C具有相同長度L1及相同寬度W1。條303具有長度L2且共用相同寬度W1。L2在圖3A中經繪示為不同於長度L1,而在其他實施例中L2可與L1相同。在一些實施例中,長度L1可在約10微米與約1000微米之間,且寬度W1可在約10微米與約1000微米之間。在一些實施例中,UBM圖案300的條可具有約1:1與約1:100之間的寬度/長度比,諸如約1:8.5。在一些實施例中,UBM圖案300的條可以約10微米與約1000微米之間的寬度W2分離,且可具有約20微米與約2000微米之間的相鄰條的節距P1。在一些實施例中,UBM圖案300的條具有「錯列(staggered)」佈置以使得一個條組(例如301A至301C)相對於另一條組(例如302A至302C)於縱向方向上偏移,其中一個組的條與其他組的條交錯。舉例而言,如圖3A中所示,條301A至301C相對於條302A至302C具有O1的偏移。在一些實施例中,條組之間的偏移O1可在約10微米與約1000微米之間。換言之,一個條組接近積體被動元件180的邊緣的末端比其他條組接近積體被動元件180的邊緣的末端更接近於所述邊緣。如圖3A中所示,UBM圖案300亦包含一實例額外條303,所述實例額外條具有與條301A至301C或條302A至302C不同的尺寸,且具有與條301A至301C的左側末端對準的左側末端及與條302A至302C的右側末端對準的右側末端。出於說明性目的,條303經繪示為一
實例,且在一些實施例中,條303可省略,或可存在具有不同長度或偏移的其他額外條。
參考圖3B,UBM圖案310的條311A-C及條312A-C具有相同長度L3及相同寬度W3。條313具有在圖3B中經繪示為與長度L3相同的長度L4,但L4在其他實施例中可不同於L3。在一些實施例中,長度L3可在約10微米與約1000微米之間,且寬度W3可在約10微米與約1000微米之間。在一些實施例中,UBM圖案310的條可具有約1:1與約1:100之間的寬度/長度比,諸如約1:8.5。在一些實施例中,長度L3大於長度L2。在一些實施例中,UBM圖案310的條可以約10微米與約1000微米之間的寬度W4分離,且可具有約20微米與約2000微米之間的相鄰條的節距P2。在一些實施例中,節距P2與UBM圖案300的節距P1相同,或寬度W3與UBM圖案300的寬度W1相同。在一些實施例中,UBM圖案310的條具有錯列佈置以使得一個條組(例如311A-C)相對於另一條組(例如312A-C)於縱向方向上偏移,其中一個組的條與其他組的條交錯。如圖3B中所示,條311A-C相對於條312A-C具有O2的偏移。在一些實施例中,條組之間的偏移O2可在約10微米與約1000微米之間。UBM圖案310亦可包含具有不同長度或偏移的一或多個額外條,例如條313可具有與條311A-C或條312A-C不同的長度L4,或可相對於條311A-C及條312A-C具有偏移O3。在一些實施例中,偏移O3可在約10微米與約1000微米之間。在一些實施例中,條313可省略,或可存在具有不同長度或偏移的其他額外條。在一些實施例中,條313具有與UBM圖案300的條303相同的長度或相同的寬度。即,在所
述實施例中,L4等於L2且條313共用相同寬度W1。
圖3C繪示根據一實施例的形成於UBM圖案300上的焊料202及已與UBM圖案310對準的UBM圖案300。圖3C繪示在圖2A中指示為C-C的視圖,其中斜線區域指示UBM圖案310且點線區域指示具有焊料202的UBM圖案310。UBM圖案300的每一條可與UBM圖案310的條相對應。舉例而言,條301A與條311A相對應,條302A與條312A相對應,等等。在接合製程期間,UBM圖案300的每一條經接合至UBM圖案310的其各別相應條。在所繪示的實施例中,條301A至301C及條302A至302C中的每一者具有與其相應條311A至311C及條312A至312C的末端對準的末端。舉例而言,條301A的末端在圖3C中所示的位置351處與相應條311A的末端對準,且條302C的末端在圖3C中所示的位置352處與相應條312C的末端對準。如圖3C中所示,條301A至301C及條302A至302C的長度L1小於條311A至311C及條312A至312C的長度L3,且因此條311A至311C及條312A至312C中的每一者的部分不由焊料202覆蓋且因而「經暴露」。在一些實施例中,條311A至311C及條312A至312C的暴露部分可定位於每一條的相反末端處。在圖3C中所示的實例中,條311A至311C接近於積體被動元件180的一個邊緣的末端經暴露,且條312A至312C接近於積體被動元件180的相反邊緣的末端經暴露。可藉由控制UBM圖案310的條的長度、偏移或位置相對於UBM圖案300的條的長度、偏移或位置來控制暴露哪些條、條的哪些部分及條的暴露部分的尺寸或位置。在圖3A至圖3C中所示的實施例中,條303與條313對準且與條313大小相同,且因此
條313不具有暴露部分。
圖4繪示根據一實施例的接合製程期間的UBM結構300及UBM結構310。圖4繪示在圖2B中經指示為D-D的視圖,其中點線區域指示焊料區域173,且其中UBM圖案300由點線繪示。在圖4中,類似於圖3C,UBM圖案300經置放於積體扇出型封裝1100的UBM圖案310上。隨後對焊料202執行回焊製程以形成焊料區域173。回焊製程可類似於上文參照圖2B所描述的回焊製程。在回焊製程期間,焊料202熔化,且由於潤濕而在第一方向上於條311A至311C的暴露部分上方且在由圖4中的箭頭所指示的第二方向(與第一方向相反)上於條312A至312C的暴露部分上方展開。由於潤濕焊料202黏著至UBM結構300及UBM結構310,因此在焊料202展開時在相同方向上藉由焊料202將潤濕力施加於每一條301A至301C及條302A至302C上。另外,由於條的錯列佈置,焊料202在第一方向上擴散的量為約等於焊料202在相反第二方向上擴散的量。因此,施加於積體被動元件180上的潤濕力大致平衡,其中來自於第一方向上的一個條組的潤濕力與來自於相反第二方向上的其他條組的潤濕力約等量且相反。在一些實施例中,經組態以使焊料202在一個方向上展開的條的數目與經組態以使焊料202在相反方向上展開的的條的數目相同。
在一些情況下,在執行回焊製程之後,積體被動元件180相對於積體扇出型封裝1100可具有傾斜定向(「傾斜」),且由於條的佈置平衡潤濕力可減小積體被動元件180在回焊製程之後所具有的傾斜量。積體被動元件180的傾斜可歸因於不均勻焊料展開、不均勻加熱、未對準或其他原因。在一些情況下,傾斜積體被
動元件180在接合至積體扇出型封裝1100之後可導致積體被動元件180的一個邊緣與積體扇出型封裝1100之間的距離(例如如圖2B中所示的H1)不同於積體被動元件180的相反邊緣與積體扇出型封裝1100之間的距離(例如如圖2B中所示的H2)。在一些情況下,傾斜積體被動元件180可降低焊料區域173使積體被動元件180接合至積體扇出型1100的品質。舉例而言,傾斜可導致焊料區域173具有金屬間化合物(inter-metallic compound;IMC)的過量形成、冷接點問題、焊料區域173的開裂、焊料區域173至UBM結構189或UBM結構149的不佳黏著或可能降低元件效能的其他問題。以此方式,如本文中所描述的UBM結構的圖案的使用可由於積體被動元件180的傾斜而減小距離H1與距離H2之間的差。在一些實施例中,如本文中所描述的UBM結構的圖案的使用可產生H1與H2之間小於約1000微米的差。以此方式,積體被動元件180傾斜的量可減小且因此可改善積體被動元件180與積體扇出型110之間的接合。
圖3A至圖4中所示的UBM結構300及UBM結構310為實例,且條的其他圖案或組態為可能的。圖5A至圖5B及圖6A至圖6D示出根據一些實施例的條的圖案的一些說明性實例,但其他圖案為可能的。舉例而言,條的每一圖案可用於積體被動元件180或積體扇出型封裝1100。在一些實施例中,可組合不同條圖案的特徵。舉例而言,分段條及未分段條(下文描述)可用於相同UBM圖案中。另外,具有不同長度、寬度、偏移或其他特性的條可經組合於相同UBM圖案中。UBM圖案亦可包含兩組或大於兩組具有相同特性的條組,諸如與一組未分段條交錯的一組分段條。
在一些實施例中,積體被動元件180的UBM圖案可具有帶有與積體扇出型封裝1100的UBM圖案不同特性的條。在一些實施例中,不同條組A、條組B以及條組C可以不同佈置交錯,諸如「AABBAABB」佈置、「ABCABC」佈置或另一佈置。這些及其他組態或組態的組合視為在本揭露的範疇內。
圖5A繪示根據一實施例的具有分段條的UBM圖案502及不具有分段條的UBM圖案512。UBM圖案502的UBM結構可經接合至UBM圖案512的UBM結構或其他UBM結構。UBM圖案502包含具有分段條的UBM結構,其中每一條分為分離區段。舉例而言,圖5A中所示的每一條包含第一區段504A及第二區段504B。條的區段可例如經由RDL或互連件電性連接或耦接。在其他情況下,條的一或多個區段可電性隔離,例如區段可為在接合製程之後保持電性浮置或以其他方式電性隔離的「虛設(dummy)」區段。在一些實施例中,區段可以約10微米與約1000微米之間的距離分離。在一些實施例中,條可具有超過兩個區段,且條的區段可為不同長度或具有不同距離的分離。圖5A中所示的UBM圖案502的分段條經繪示為具有偏移,但在其他情況下,分段條可不具有偏移。在一些情況下,一些條內的分離的位置或大小相對於其他條可具有偏移。在一些情況下,積體被動元件180上的UBM圖案及積體扇出型封裝1100上的UBM圖案兩者可具有分段條。在一些實施例中,儘管UBM圖案502的分段條的第一區段504A及第二區段504B分離與UBM圖案512的條514的暴露部分相對應,但條514亦可具有額外暴露部分。在一些實施例中,焊料202形成於第一區段504A及第二區段504B上,且在於回焊製程期間
擴張至條514的暴露部分中時提供平衡的潤濕力。
圖5B繪示根據一實施例的具有偏移的UBM圖案506及不具有偏移的UBM圖案516。UBM圖案516的UBM結構可經接合至UBM圖案506的UBM結構或其他UBM結構。如圖5B中所示,UBM圖案506包含偏移條508,但UBM圖案516包含不具有偏移的條518。在一些實施例中,條508的長度小於條518的長度,且因此條518在回焊製程期間具有暴露部分。在一些實施例中,焊料202形成於條508上,且在於回焊製程期間擴張至條518的暴露部分中時提供平衡的潤濕力。
圖6A至圖6D繪示根據一些實施例的具有條602的第一UBM圖案置放於具有條604的第二UBM圖案上方的平面視圖。圖6A至圖6D的平面視圖類似於圖3C的平面視圖,且第一UBM圖案及第二UBM圖案可類似於前述UBM圖案或UBM結構。在圖6A至圖6D中,斜線區域指示第二UBM圖案的條604,且交叉影線區域指示其中第一UBM圖案的條602完全與第二UBM圖案的條604交疊。在圖6A中,條602的長度以長度差異LD1小於條604的長度。交替條602亦以偏移分離OS1彼此偏移。在圖6A中所示的實施例中,長度差LD1大致等於偏移分離OS1。然而,兩個UBM圖案的條之間的長度差可不同於UBM圖案中的一者的條之間的偏移分離。舉例而言,在圖6B中,條602的偏移分離OS2小於條602與條604之間的長度差LD2。如所繪示,較大長度差可具有較大暴露區域,且因此在回焊期間產生較大潤濕力。在圖6C中,條602的偏移分離OS3大於條602與條604之間的長度差LD3。在圖6C中所示的實例組態中,條604與條602共同對
準的末端於縱向方向上延伸超出條604的經暴露末端。圖6D繪示其中條602或條604的偏移分離大於條602與條604之間的長度差的一實例組態。每一條帶602或條帶604可具有於縱向方向上相較於條帶602或條帶604的遠側末端更接近於UBM圖案的中心的近側末端。在圖6D的實例中,每一條帶604的近側末端與每一條帶602的近側末端共同對準,且暴露出每一條帶604的遠側末端。如圖4A至圖6D中所示,UBM圖案、UBM結構或條的不同組態為可能的。以此方式,UBM圖案的UBM結構中接合至一起的一個或兩個可經組態以用於特定應用或製程。
圖7示出在一些實施例中包含底部封裝1100'、頂部封裝160以及積體被動元件180的半導體封裝1300的橫截面視圖。圖1中所示出的半導體封裝1200可與圖7中所示出的半導體封裝1300的部分相對應,其中相似附圖標記指代相似元件。
在圖7中,積體被動元件180(可類似於先前所描述的積體被動元件180)經附接至底部封裝1100',所述底部封裝1100'可為類似於先前所描述的積體扇出型封裝1100的積體扇出型封裝。底部封裝1100'具有前側重佈線結構140與背側重佈線結構110之間的晶粒120。前側重佈線結構140可與圖1的重佈線結構140相同或類似,且背側重佈線結構110包含形成於一或多個介電層(例如111、113)中的導電構件(例如導線114及通孔)。模製材料130形成於前側重佈線結構140與背側重佈線結構110之間。諸如銅導柱或TSV的導電柱119形成於模製材料130中。導電柱119將前側重佈線結構140與背側重佈線結構110電性耦接。
如圖7中所示,頂部封裝160(可為記憶體封裝)經由導
電接點168接合至底部封裝1100'。如圖7中所示出,頂部封裝160具有基底161及附接至基底161的上部表面的一或多個半導體晶粒162(例如記憶體晶粒或其他元件)。在一些實施例中,基底161包含矽、砷化鎵、絕緣體上矽(silicon on insulator,SOI)或其他類似材料。在一些實施例中,基底161為多層電路板。在一些實施例中,基底161包含陶瓷、玻璃、塑膠、膠帶、膜或其他支撐材料。基底161可包含形成於基底161中/上的導電構件(例如導線及通孔)。如圖7中所示出,基底161具有形成於基底161的上部表面及下部表面上的導電墊163,所述導電墊163經電性耦接至基底161的導電構件。一或多個半導體晶粒162藉由例如接線167電性耦接至導電墊163。模製材料165(包括環氧樹脂、有機聚合物、聚合物或類似物)形成於基底161上方及半導體晶粒162周圍。在一些實施例中,模製材料165可與基底161共端,如圖7中所示出。
在一些實施例中,執行回焊製程以將半導體封裝160電性耦接且以機械方式耦接至背側重佈線結構110。導電接點168形成於導電墊163與導電構件114之間。在一些實施例中,導電接點168包含焊料區域、導電柱(例如在銅導柱或TSV的至少末端表面上具有焊料區域的銅導柱)或任何其他合適的導電接點。
實施例可達成優點。舉例而言,具有錯列佈置(例如具有帶有偏移的UBM結構組)或具有與相應經接合UBM結構不一樣長度的UBM結構的圖案的使用可減小元件在接合至基底之後所具有的傾斜。以此方式,可改善元件與基底之間的接合,且可減少接合中的缺陷,其可改善良率。在一些情況下,本文中所描述技術
的使用可實現具有低電阻及低電感的接合。另外,可不需要不同的處理工具。
在一實施例中,一種半導體封裝包含:半導體元件,所述半導體元件包含第一UBM結構,其中第一UBM結構包含:多個第一導電條,在第一方向上延伸;多個第二導電條,與多個第一導電條分離且交錯,所述第二導電條在第一方向上延伸,其中多個第一導電條在第一方向上以第一偏移距離與多個第二導電條偏移;以及基底,包含第二UBM結構,第二UBM結構包含多個第三導電條,多個第三導電條中的每一者經組態以接合至多個第一導電條中的一者或多個第二導電條中的一者。在一實施例中,半導體元件為積體被動元件。在一實施例中,基底為積體扇出型封裝。在一實施例中,第二UBM結構更包含多個第四導電條,其中多個第四導電條在第一方向上以第二偏移距離與多個第三導電條偏移。在一實施例中,第一偏移距離在約10微米與約1000微米之間。在一實施例中,第一UBM結構包含具有與第二UBM結構的半導體條相同橫向尺寸的半導體條。在一實施例中,多個第一半導體條具有第一長度,其中多個第二半導體條具有第一長度,且其中多個第三半導體條具有不同於第一長度的第二長度。在一實施例中,第一長度與第二長度之間的差為小於第一偏移距離的距離。
在一實施例中,一種半導體元件包含:積體被動元件,包含安置於積體被動元件的表面上的多個第一接合結構及多個第二接合結構,其中第一接合結構及第二接合結構具有第一長度,且其中第一接合結構以第一偏移距離與第二接合結構偏移;及基底,包含安置於基底的表面上的多個第三接合結構及多個第四接合結
構,其中第三接合結構及第四接合結構具有大於第一長度的第二長度,其中第三接合結構以第二偏移距離與第四接合結構偏移,且其中多個第三接合結構中的每一者經接合至多個第一接合結構中的各別一者。在一實施例中,第二長度大於第一長度約10微米與約1000微米之間。在一實施例中,多個第一接合結構使用焊料材料接合至多個第三接合結構。在一實施例中,第一接合結構中的每一者鄰近至少一個第二接合結構,且其中第一接合結構中的每一者於縱向方向上以第一偏移距離與相鄰第二接合結構偏移。在一實施例中,第一偏移距離小於第一長度與第二長度之間的差。在一實施例中,第二偏移距離與第一偏移距離相同。在一實施例中,多個第一接合結構的第一接合結構具有面向第一縱向方向的第一末端,且多個第三接合結構的第三接合結構具有面向第一縱向方向的第一末端,且其中多個第一接合結構的第一末端與多個第三接合結構的第一末端對準。在一實施例中,多個第一接合結構的第一接合結構處於平行佈置中。
在一實施例中,一種形成半導體元件的方法包含:在半導體元件上方形成第一UBM結構的第一圖案,第一UBM結構的第一圖案包含平行導電條;在基底上方形成第二UBM結構的第二圖案,第二UBM結構的第二圖案包含平行導電條;在第一UBM結構上形成焊料材料,在第二UBM結構上方置放第一UBM結構,其中第一UBM結構中的每一者的第一末端與各別第二UBM結構的第一末端對準,且其中第一UBM結構中的每一者的第二末端與各別第二UBM結構的第二末端偏移;以及執行回焊製程以使焊料材料朝向各別第二UBM結構中的每一者的第二末端流動。在一實
施例中,所述方法亦包含在第二UBM結構上形成焊劑材料。在一實施例中,在執行回焊製程之後,半導體元件的末端離基底的第一距離與半導體元件的相反末端離基底的第二距離之間的差小於約1000微米。在一實施例中,相較於每一各別第二UBM結構的第一末端,每一各別第二UBM結構的第二末端更接近於半導體元件的邊緣。
前文概述若干實施例的特徵以使得所屬領域中具通常知識者可更佳地理解本揭露的態樣。所屬領域中具通常知識者應理解,其可易於使用本揭露作為設計或修改用於實現本文中所引入實施例的相同目的及/或達成相同優點的其他方法及結構的基礎。所屬領域中具通常知識者亦應認識到,此類等效構造並不脫離本揭露的精神及範疇,且所屬領域中具通常知識者可在不脫離本揭露的精神及範疇的情況下於本文中作出各種改變、替代以及更改。
149、189:凸塊下金屬化結構
180:積體被動元件
200:接合頭部
202:焊料
204:焊劑材料
1100:積體扇出型封裝
A-A、B-B、C-C:視圖
Claims (10)
- 一種半導體封裝,包括:半導體元件,包括第一凸塊下金屬化結構,其中所述第一凸塊下金屬化結構包括:多個第一導電條,所述多個第一導電條在第一方向上延伸;以及多個第二導電條,與所述多個第一導電條分離且交錯,所述第二導電條在所述第一方向上延伸,其中所述多個第一導電條在所述第一方向上以第一偏移距離與所述多個第二導電條偏移;以及基底,包括第二凸塊下金屬化結構,所述第二凸塊下金屬化結構包括多個第三導電條,所述多個第三導電條中的每一者經組態以接合至所述多個第一導電條中的一者或所述多個第二導電條中的一者。
- 如申請專利範圍第1項所述的半導體封裝,其中所述基底為積體扇出型封裝件。
- 如申請專利範圍第1項所述的半導體封裝,所述第二凸塊下金屬化結構更包括多個第四導電條,其中所述多個第四導電條在所述第一方向上以第二偏移距離與所述多個第三導電條偏移。
- 如申請專利範圍第1項所述的半導體封裝,其中所述第一凸塊下金屬化結構包括半導體條,所述半導體條具有與所述第二凸塊下金屬化結構的半導體條相同的橫向尺寸。
- 如申請專利範圍第1項所述的半導體封裝,其中所述多 個第一半導體條具有第一長度,其中所述多個第二半導體條具有所述第一長度,以及其中所述多個第三半導體條具有不同於所述第一長度的第二長度。
- 一種半導體元件,包括:積體被動元件,包括安置於所述積體被動元件的表面上的多個第一接合結構及多個第二接合結構,其中所述第一接合結構及所述第二接合結構具有第一長度,以及其中所述第一接合結構以第一偏移距離與所述第二接合結構偏移;及基底,包括安置於所述基底的表面上的多個第三接合結構及多個第四接合結構,其中所述第三接合結構及所述第四接合結構具有大於所述第一長度的第二長度,其中所述第三接合結構以第二偏移距離與所述第四接合結構偏移,其中所述多個第三接合結構中的每一者與所述多個第一接合結構中相對應一者接合。
- 如申請專利範圍第6項所述的半導體元件,其中所述第一接合結構中的每一者鄰近至少一個第二接合結構,以及其中所述第一接合結構中的每一者在縱向方向上以所述第一偏移距離與相鄰的第二接合結構偏移。
- 如申請專利範圍第6項所述的半導體元件,其中所述多個第一接合結構的所述第一接合結構具有面向第一縱向方向的第一末端,且所述多個第三接合結構的所述第三接合結構具有面向所述第一縱向方向的第一末端,以及其中所述多個第一接合結構的所述第一末端與所述多個第三接合結構的所述第一末端對準。
- 如申請專利範圍第6項所述的半導體元件,其中所述多個第一接合結構的所述第一接合結構處於平行佈置中。
- 一種形成半導體元件的方法,包括:在半導體元件上方形成第一凸塊下金屬化結構的第一圖案,所述第一凸塊下金屬化結構的第一圖案包括平行導電條;在基底上方形成第二凸塊下金屬化結構的第二圖案,所述第二凸塊下金屬化結構的第二圖案包括平行導電條;在所述第一凸塊下金屬化結構上形成焊料材料;在所述第二凸塊下金屬化結構上方置放所述第一凸塊下金屬化結構,其中所述第一凸塊下金屬化結構中的每一者的第一末端與各別第二凸塊下金屬化結構的第一末端對準,以及其中所述第一凸塊下金屬化結構中的每一者的第二末端與各別第二凸塊下金屬化結構的第二末端偏移;以及執行回焊製程以使所述焊料材料朝向所述各別第二凸塊下金屬化結構中的每一者的所述第二末端流動。
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Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20150123759A1 (en) * | 2013-11-01 | 2015-05-07 | Taiwan Semiconductor Manufacturing Co., Ltd. | Inductor For Semiconductor Integrated Circuit |
TW201724427A (zh) * | 2015-12-28 | 2017-07-01 | 台灣積體電路製造股份有限公司 | 用於接合積體被動裝置於整合式扇出封裝中的墊中之開口 |
US20170221819A1 (en) * | 2016-01-29 | 2017-08-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Wireless Charging Package with Chip Integrated in Coil Center |
Family Cites Families (39)
Publication number | Priority date | Publication date | Assignee | Title |
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US6917510B1 (en) | 2004-10-27 | 2005-07-12 | Kemet Corporation | Extended terminal ceramic SMD |
US8759964B2 (en) | 2007-07-17 | 2014-06-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Wafer level package structure and fabrication methods |
US9293401B2 (en) | 2008-12-12 | 2016-03-22 | Stats Chippac, Ltd. | Semiconductor device and method for forming a low profile embedded wafer level ball grid array molded laser package (EWLP-MLP) |
WO2011125277A1 (ja) | 2010-04-07 | 2011-10-13 | 株式会社島津製作所 | 放射線検出器およびそれを製造する方法 |
US9048233B2 (en) | 2010-05-26 | 2015-06-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package systems having interposers |
US8361842B2 (en) | 2010-07-30 | 2013-01-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Embedded wafer-level bonding approaches |
US8884431B2 (en) | 2011-09-09 | 2014-11-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packaging methods and structures for semiconductor devices |
US9064879B2 (en) | 2010-10-14 | 2015-06-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packaging methods and structures using a die attach film |
US8797057B2 (en) | 2011-02-11 | 2014-08-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Testing of semiconductor chips with microbumps |
US8829676B2 (en) | 2011-06-28 | 2014-09-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect structure for wafer level package |
JP2013074054A (ja) | 2011-09-27 | 2013-04-22 | Renesas Electronics Corp | 電子装置、配線基板、及び、電子装置の製造方法 |
US9000584B2 (en) | 2011-12-28 | 2015-04-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packaged semiconductor device with a molding compound and a method of forming the same |
US8680647B2 (en) | 2011-12-29 | 2014-03-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packages with passive devices and methods of forming the same |
US8703542B2 (en) | 2012-05-18 | 2014-04-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Wafer-level packaging mechanisms |
US9991190B2 (en) | 2012-05-18 | 2018-06-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packaging with interposer frame |
US9443783B2 (en) | 2012-06-27 | 2016-09-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3DIC stacking device and method of manufacture |
US8809996B2 (en) | 2012-06-29 | 2014-08-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package with passive devices and method of forming the same |
US8785299B2 (en) | 2012-11-30 | 2014-07-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package with a fan-out structure and method of forming the same |
US8803306B1 (en) | 2013-01-18 | 2014-08-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fan-out package structure and methods for forming the same |
US8778738B1 (en) | 2013-02-19 | 2014-07-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packaged semiconductor devices and packaging devices and methods |
US9299649B2 (en) | 2013-02-08 | 2016-03-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3D packages and methods for forming the same |
US9263511B2 (en) | 2013-02-11 | 2016-02-16 | Taiwan Semiconductor Manufacturing Co., Ltd. | Package with metal-insulator-metal capacitor and method of manufacturing the same |
US9048222B2 (en) | 2013-03-06 | 2015-06-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of fabricating interconnect structure for package-on-package devices |
US8993380B2 (en) | 2013-03-08 | 2015-03-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and method for 3D IC package |
US9368460B2 (en) | 2013-03-15 | 2016-06-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fan-out interconnect structure and method for forming same |
US8877554B2 (en) | 2013-03-15 | 2014-11-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packaged semiconductor devices, methods of packaging semiconductor devices, and PoP devices |
US9281254B2 (en) | 2014-02-13 | 2016-03-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods of forming integrated circuit package |
US9425126B2 (en) | 2014-05-29 | 2016-08-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Dummy structure for chip-on-wafer-on-substrate |
US9496189B2 (en) | 2014-06-13 | 2016-11-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Stacked semiconductor devices and methods of forming same |
US9478443B2 (en) | 2014-08-28 | 2016-10-25 | Taiwan Semiconductor Manufacturing Company Limited | Semiconductor package and method of forming the same |
US9461018B1 (en) | 2015-04-17 | 2016-10-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fan-out PoP structure with inconsecutive polymer layer |
US9666502B2 (en) | 2015-04-17 | 2017-05-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Discrete polymer in fan-out packages |
JP6531603B2 (ja) * | 2015-10-01 | 2019-06-19 | 富士通株式会社 | 電子部品、電子装置及び電子装置の製造方法 |
KR101933408B1 (ko) | 2015-11-10 | 2018-12-28 | 삼성전기 주식회사 | 전자부품 패키지 및 이를 포함하는 전자기기 |
US9735131B2 (en) | 2015-11-10 | 2017-08-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multi-stack package-on-package structures |
KR102005352B1 (ko) | 2016-06-23 | 2019-07-31 | 삼성전자주식회사 | 팬-아웃 반도체 패키지 |
US10074597B2 (en) * | 2017-01-20 | 2018-09-11 | Infineon Technologies Austria Ag | Interdigit device on leadframe for evenly distributed current flow |
US10840227B2 (en) | 2017-11-02 | 2020-11-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Under-bump-metallization structure and redistribution layer design for integrated fan-out package with integrated passive device |
US10651053B2 (en) | 2017-11-22 | 2020-05-12 | Taiwan Semiconductor Manufacturing Co., Ltd. | Embedded metal insulator metal structure |
-
2018
- 2018-12-10 US US16/215,373 patent/US10658348B2/en active Active
-
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- 2019-02-21 TW TW108105799A patent/TWI708341B/zh active
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Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20150123759A1 (en) * | 2013-11-01 | 2015-05-07 | Taiwan Semiconductor Manufacturing Co., Ltd. | Inductor For Semiconductor Integrated Circuit |
TW201724427A (zh) * | 2015-12-28 | 2017-07-01 | 台灣積體電路製造股份有限公司 | 用於接合積體被動裝置於整合式扇出封裝中的墊中之開口 |
US20170221819A1 (en) * | 2016-01-29 | 2017-08-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Wireless Charging Package with Chip Integrated in Coil Center |
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CN110957295A (zh) | 2020-04-03 |
US20200279837A1 (en) | 2020-09-03 |
KR20200036692A (ko) | 2020-04-07 |
KR102251556B1 (ko) | 2021-05-14 |
US11049850B2 (en) | 2021-06-29 |
US20200105730A1 (en) | 2020-04-02 |
US10658348B2 (en) | 2020-05-19 |
CN110957295B (zh) | 2021-11-09 |
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