TWI717652B - 半導體封裝體及其形成方法 - Google Patents

半導體封裝體及其形成方法 Download PDF

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TWI717652B
TWI717652B TW107139407A TW107139407A TWI717652B TW I717652 B TWI717652 B TW I717652B TW 107139407 A TW107139407 A TW 107139407A TW 107139407 A TW107139407 A TW 107139407A TW I717652 B TWI717652 B TW I717652B
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conductive
die
rewiring
rewiring structure
carrier
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TW107139407A
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TW201923921A (zh
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陳潔
陳憲偉
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台灣積體電路製造股份有限公司
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Abstract

一種方法包含：用模製材料包圍晶粒及接近晶粒的導電柱，其中晶粒及導電柱設置於第一重佈線結構的第一側上方，其中第一重佈線結構的與第一側相對的第二側附接至第一載體；將設置於預製的第二重佈線結構的第一表面上的導電襯墊接合至晶粒且接合至導電柱，其中預製的第二重佈線結構的與第一表面相對的第二表面附接至第二載體；在接合導電襯墊之後，移除第二載體以暴露預製的第二重佈線結構的接近第二表面的導電特徵；以及在預製的第二重佈線結構的導電特徵上方形成導電凸塊且導電凸塊電性耦接至導電特徵。

Description

半導體封裝體及其形成方法
本發明的實施例是有關於半導體封裝體及其形成方法。
半導體工業由於各種電子組件(例如電晶體、二極體、電阻器、電容器等)的積體密度不斷改良而歷經快速發展。大多數情況下，此積體密度改良來自最小特徵尺寸的反覆減小，其允許將更多組件整合至給定區域中。由於近來對甚至更小的電子裝置的需求增長，因而需要更小且更具創造性的半導體晶粒封裝技術。
此等封裝技術的實例為疊層封裝(Package-on-Package；POP)技術。在PoP封裝中，頂部半導體封裝體堆疊於底部半導體封裝體的頂部上，以提供高水準的積體及組件密度。另一實例為多晶片模組(Multi-Chip-Module；MCM)技術，其中多個半導體晶粒封裝體於一個半導體封裝體中，以提供具有積體功能的半導體元件。
高水準的先進封裝技術的整合能夠產生具有增強型功能及較小佔據面積的半導體元件，其有利於諸如行動電話、平板電腦以及數位音樂播放器之小外形要素的裝置。另一優勢為連接半 導體封裝體內的互操作部件的導電路徑長度縮短。此改良半導體元件的電氣性能，因為電路之間的互連件的較短佈線得到較快信號傳播及降低的噪音及串擾。
本發明實施例的一種形成半導體封裝體的方法，包括：在第一載體上方形成第一重佈線結構；在所述第一重佈線結構上方形成導電柱；將第一晶粒的第一側附接至鄰近於所述導電柱的所述第一重佈線結構，所述第一晶粒的第二側背向所述第一重佈線結構，所述第一晶粒的所述第二側上設置有晶粒連接件；在所述第一重佈線結構上方形成模製材料，所述模製材料包圍所述第一晶粒及所述導電柱；將第二重佈線結構的第一側接合至所述晶粒連接件且接合至所述導電柱，與所述第二重佈線結構的所述第一側相對的所述第二重佈線結構的第二側附接至第二載體；在接合所述第二重佈線結構的所述第一側之後，移除所述第二載體以暴露所述第二重佈線結構的所述第二側上的導電特徵；以及在移除所述第二載體之後，在所述第二重佈線結構的所述第二側上的所述導電特徵上形成導電凸塊。
本發明實施例的一種形成半導體封裝體的方法，包括：用模製材料包圍晶粒及接近所述晶粒的導電柱，其中所述晶粒及所述導電柱設置於第一重佈線結構的第一側上方，其中所述第一重佈線結構的與所述第一側相對的第二側附接至第一載體；將設置於預製的第二重佈線結構的第一表面上的導電襯墊接合至所述晶粒且接合至所述導電柱，其中所述預製的第二重佈線結構的與 所述第一表面相對的第二表面附接至第二載體；在接合所述導電襯墊之後，移除所述第二載體以暴露所述預製的第二重佈線結構的接近所述第二表面的導電特徵；以及在所述預製的第二重佈線結構的所述導電特徵上方形成導電凸塊且所述導電凸塊電性耦接至所述導電特徵。
本發明實施例的一種半導體封裝體，包括晶粒、導電柱、第一重佈線結構以及第二重佈線結構。晶粒及導電柱嵌入於模製材料中。第一重佈線結構在所述晶粒的第一側上且電性耦接至所述導電柱。第二重佈線結構在所述晶粒的與所述第一側相對的第二側上，其中所述晶粒在所述晶粒的所述第二側上具有晶粒連接件，其中所述第二重佈線結構電性耦接至所述晶粒連接件及所述導電柱，且其中所述第二重佈線結構的第二寬度不同於所述第一重佈線結構的第一寬度。
100、100A、160、200、200A:半導體封裝體
101、133:載體
110、140、140A、140B、140C:重佈線結構
113、125、141:介電層
114、146:導電特徵
115、123、143:導電線
116:開口
117、124、145:通孔
118:黏著膜
119:導電柱
120、162:半導體晶粒
121、161:基底
122:互連結構
126:襯墊
127:鈍化膜
128:晶粒連接件
129:介電材料
130、165:模製材料
140L:第二側
140U:第一側
147、163:導電襯墊
148、149:焊料區域
151:凸塊下金屬化物結構
153:鈍化層
155:外部連接件
157:支架
159:膠帶
167:接線
168:導電接合點
171:電子裝置
310、320、330:區域
1000:方法
1010、1020、1030、1040:步驟
A-A、B-B:線
D1、D2:深度
W1、W2:寬度
當結合附圖閱讀時，自以下詳細描述最佳地理解本揭露內容的態樣。應注意，根據行業中的標準慣例，各種特徵未按比例繪製。事實上，可出於論述清楚起見，而任意地增大或減小各種特徵的尺寸。
圖1至圖4、圖5A、圖5B以及圖6至圖9示出根據一實施例的各製造階段的半導體封裝體的各種視圖。
圖10示出根據一實施例的半導體封裝體的橫截面視圖。
圖11A、圖11B以及圖12示出根據一實施例的各製造階段的半導體封裝體的各種視圖。
圖13示出根據一實施例的半導體封裝體的橫截面視圖。
圖14示出根據一些實施例的用於形成半導體封裝體的方法的流程圖。
以下揭露內容提供用於實施本發明的不同特徵的許多不同實施例或實例。下文描述組件及配置的特定實例以簡化本揭露內容。當然，此等組件及配置僅為實例且不意欲為限制性的。舉例而言，在以下描述中，第一特徵在第二特徵上方或上的形成可包含第一特徵與第二特徵直接接觸地形成的實施例，且亦可包含額外特徵可在第一特徵與第二特徵之間形成，使得第一特徵與第二特徵可不直接接觸的實施例。
此外，為易於描述，可在本文中使用諸如「在...下方」、「在...下」、「下部」、「在...上方」、「上部」及其類似者的空間相對術語，以描述如圖式中所示的一個元件或特徵與另外一或多個元件或特徵的關係。除圖式中所描繪的定向以外，空間相對術語意欲涵蓋裝置在使用或操作中的不同定向。設備可以其他方式定向(旋轉90度或處於其他定向)且本文中所使用的空間相對描述詞可同樣相應地進行解譯。
在各種實施例中提供半導體封裝體及形成半導體封裝體的方法。在一些實施例中，半導體封裝體具有嵌入於模製材料中的晶粒，以及在晶粒的相對側上的重佈線結構(例如，背側重佈線結構及前側重佈線結構)。在一些實施例中，前側重佈線結構在附接至晶粒之前預先成形。在一些實施例中，至少前側重佈線結 構是使用鑲嵌製程形成的，且因此，達成了導電線之間的更精細節距(pitch)以及重佈線結構的更高可靠性。
圖1至圖4、圖5A、圖5B以及圖6至圖9繪示根據一實施例的各製造階段的半導體封裝體100的各種視圖(例如，橫截面視圖、平面視圖)。在圖1中，重佈線結構110在載體101上方形成。重佈線結構110包括形成於一或多個介電層中的導電特徵(例如，導電線及通孔)。導電柱119在重佈線結構110的上部表面上方形成且電性耦接至重佈線結構110。
載體101可由諸如玻璃的材料製成，但亦可使用其他適合的材料，諸如矽、聚合物、聚合物複合物、金屬箔、陶瓷、玻璃環氧樹脂、氧化鈹或膠帶。重佈線結構110在載體101上方形成。重佈線結構110包括導電特徵，諸如一或多層導電線(例如，導電線115)及通孔(例如，通孔117)，以及一或多個介電層(例如，介電層113)。為簡單起見，介電層113在圖1中繪示為一個層，然而，如本領域技術人員容易瞭解，介電層113可包括多個介電層。
在一些實施例中，一或多個介電層113由聚合物形成，所述聚合物諸如聚苯并噁唑(polybenzoxazole；PBO)、聚醯亞胺、苯并環丁烯(benzocyclobutene；BCB)或其類似物。在其他實施例中，一或多個介電層113由氮化物(諸如，氮化矽)、氧化物(諸如，氧化矽)、磷矽酸鹽玻璃(phosphosilicate glass；PSG)、硼矽酸鹽玻璃(borosilicate glass；BSG)、摻硼磷矽酸鹽玻璃(boron-doped phosphosilicate glass；BPSG)或其類似物形成。一或多個介電層113可藉由任何可接受的沈積製程形成，諸如旋塗、 化學氣相沈積(chemical vapor deposition；CVD)、層壓(laminating)、類似製程或其組合。
在一些實施例中，重佈線結構110的導電特徵包括由諸如銅、鈦、鎢、鋁或其類似物的合適導電材料形成的導電線(例如，導電線115)、導電通孔(例如，導電通孔117)。在一些實施例中，導電特徵藉由以下操作形成：在重佈線結構110的介電層中形成開口以暴露底層導電特徵；在介電層上方及開口中形成晶種層(未圖示)；在晶種層上方形成具有經設計圖案的經圖案化光阻(未圖示)；將導電材料鍍覆(例如，電鍍或無電極鍍覆)於經設計圖案中及晶種層上方；以及移除光阻及晶種層上未形成導電材料的部分。
在一些實施例中，在形成重佈線結構110之前，將黏著層(未圖示)沈積或層壓於載體101上方。黏著層可為感光性的且可藉由例如在後續載體剝離製程中將紫外(ultra-violet；UV)光照射在載體101上而輕易地自載體101剝離。舉例而言，黏著層可為由明尼蘇達州聖保羅(St.Paul,Minnesota)的3M公司(3M Company)製造的光-熱轉換(light-to-heat-conversion；LTHC)塗層。
仍參考圖1，導電柱119在重佈線結構110上方形成。導電柱119可藉由以下操作形成：在重佈線結構110上方形成晶種層；在晶種層上方形成經圖案化光阻，其中所述經圖案化光阻中的開口中的每一者對應於待形成的導電柱119的位置；使用例如電鍍或無電極鍍覆，用諸如銅的導電材料來填充開口；使用例如灰化或剝離製程來移除光阻；以及移除晶種層上未形成導電柱119 的部分。
隨後，在圖2中，半導體晶粒120(亦可稱為晶粒或積體電路(integrated circuit；IC)晶粒)附接至重佈線結構110的上部表面。諸如晶粒貼合膜(die attaching film；DAF)的黏著膜118可用於將晶粒120附接至重佈線結構110。由於晶粒120的背側附接至重佈線結構110，故重佈線結構110亦可稱為背側重佈線結構。
在黏附至重佈線結構110之前，晶粒120可根據適用的製造製程經處理以在晶粒120中形成積體電路。舉例而言，晶粒120可包含半導體基底121(諸如經摻雜或未經摻雜的矽)或絕緣層上半導體(semiconductor-on-insulator；SOI)基底的主動層。半導體基底121可包含其他半導體材料，諸如鍺；化合物半導體，包含碳化矽、砷化鎵、磷化鎵、氮化鎵、磷化銦、砷化銦及/或銻化銦；合金半導體，包含SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP；或其組合。亦可使用其他基底，諸如多層基底或梯度基底。諸如電晶體、二極體、電容器、電阻器等裝置(未圖示)可在半導體基底121中及/或上形成，且可藉由互連結構122互連以形成積體電路，所述互連結構包括例如半導體基底121上的一或多個介電層125中的金屬化圖案(例如，導電線123及通孔124)。在一些實施例中，使用鑲嵌及/或雙鑲嵌製程來形成互連結構122。
晶粒120更包括進行外部連接的襯墊126，諸如鋁襯墊。襯墊126在可稱為晶粒120的主動側或前側的位置上。鈍化膜127在晶粒120上及襯墊126的部分上形成。開口穿過鈍化膜127達至襯墊126。諸如導電柱(例如，包含諸如銅的金屬)的晶粒連接 件128延伸至鈍化膜127的開口中且機械耦接及電性耦接至各別襯墊126。晶粒連接件128可藉由例如鍍覆或其類似方法形成。晶粒連接件128電性耦接至晶粒120的積體電路。
介電材料129在晶粒120的主動側上形成，諸如在鈍化膜127及/或晶粒連接件128上形成。介電材料129側向地密封晶粒連接件128，且介電材料129與晶粒120側向共端。介電材料129可為聚合物，諸如聚苯并噁唑(PBO)、聚醯亞胺、苯并環丁烯(BCB)或其類似物；氮化物，諸如氮化矽或其類似物；氧化物，諸如氧化矽、磷矽酸鹽玻璃(PSG)、硼矽酸鹽玻璃(BSG)、硼摻磷矽酸鹽玻璃(BPSG)或其類似物；或其組合；且所述介電材料可例如藉由旋塗、層壓、CVD或類似製程形成。
隨後，在圖3中，模製材料130在重佈線結構110上方、在晶粒120周圍以及在導電柱119周圍形成。作為實例，模製材料130可包括環氧樹脂、有機聚合物、添加或不添加矽石類或玻璃填充劑的聚合物或其他材料。在一些實施例中，模製材料130包括在塗覆時為凝膠型液體的液體模製化合物(liquid molding compound；LMC)。模製材料130在塗覆時亦可包括液體或固體。可替代地，模製材料130可包括其他絕緣材料及/或密封材料。在一些實施例中，使用晶圓級模製製程來塗覆模製材料130。模製材料130可使用例如壓縮模製、轉移模製或其他方法來模製。
隨後，在一些實施例中，使用固化製程來固化模製材料130。固化製程可包括使用退火製程或其他加熱製程將模製材料130加熱至預定溫度，保持預定時間段。固化製程亦可包括紫外(UV)曝光製程、紅外(infrared；IR)能量曝光製程、其組合或 其與加熱製程之組合。可替代地，可使用其他方法來固化模製材料130。在一些實施例中，不包含固化製程。
隨後，可執行諸如化學機械研磨(chemical and mechanical polish；CMP)的平坦化製程以移除模製材料130在晶粒120的前側上方的過量部分。在一些實施例中，在平坦化製程之後，模製材料130、導電柱119以及晶粒連接件128具有共面的上部表面。
接下來參考圖4，預先成形的重佈線結構140附接至圖3中所示的半導體封裝體100。在圖4的所示實例中，重佈線結構140在載體133上形成，之後附接至半導體封裝體100。重佈線結構140包括形成於一或多個介電層141中的一或多層導電特徵(例如，導電線143、通孔145)。載體133可由矽(例如，塊狀矽)形成，但對於載體133亦可使用其他合適的材料。儘管未圖示，但在形成重佈線結構140之前，可在載體133上形成諸如LTHC膜的黏著層。
如圖4中所示，重佈線結構140的第一側140U附接至載體133，且導電襯墊147(例如，銅襯墊)在重佈線結構140的與第一側140U相對的第二側140L上形成，所述導電襯墊147電性耦接至重佈線結構140的導電特徵。焊料區域149(例如，焊料膏)可在導電襯墊147上方形成。儘管圖4中未示出，但焊料區域(例如，焊料膏)亦可在導電柱119的上部表面上方及晶粒連接件128的上部表面上方形成。在各種實施例中，焊料區域將用於在後續回焊製程中在重佈線結構140與導電柱119/晶粒連接件128之間形成焊接接頭。由於重佈線結構140接合至晶粒120的前側，故重佈線結構140亦可稱為前側重佈線結構。
在一些實施例中，使用與在半導體晶粒中形成互連結構(例如，圖2中的互連結構122)相同或類似的形成方法在載體133上方形成重佈線結構140。特定言之，鑲嵌製程及/或雙鑲嵌製程用於形成重佈線結構140。在一實施例鑲嵌製程中，使用諸如化學氣相沈積(CVD)的合適沈積方法在載體133上方形成介電層。一旦形成介電層，即使用例如微影及蝕刻製程在介電層中形成開口(諸如，溝槽)。隨後，藉由濺鍍、物理氣相沈積(physical vapor deposition；PVD)或類似製程在開口中沈積障壁層，所述障壁層可包括鈦(Ti)、鉭(Ta)、氮化鈦(TiN)、氮化鉭(TaN)、其類似物或其組合。隨後在障壁層上方形成晶種層，所述晶種層可包括銅(Cu)、Ti、Ta、TiN、TaN或其組合。隨後，藉由例如電鍍製程或無電極鍍覆製程在開口中及晶種層上方形成諸如銅的填充金屬。填充金屬可過度填充開口且可在介電層的上部表面上方形成。隨後執行諸如CMP的平坦化製程以移除開口外部的填充金屬的過量部分、障壁層的過量部分以及晶種層的過量部分。開口內的剩餘導電材料形成重佈線結構140的導電特徵(例如，一層導電特徵)。在雙鑲嵌製程中，每一溝槽可具有上部溝槽及下部溝槽，其中上部溝槽對應於導電線的位置且下部溝槽對應於通孔的位置。隨後在同一處理步驟中藉由填充金屬填充上部溝槽及下部溝槽，其中上部溝槽經填充以形成導電線且下部溝槽經填充以形成通孔。類似於鑲嵌製程的過程，可在上部溝槽及下部溝槽中形成障壁層及晶種層。
藉由在載體133上方形成重佈線結構140，可使用鑲嵌製程及/或雙鑲嵌製程來形成前側重佈線結構140。相比之下，在不 使用本發明所揭露方法的情況下，或許不可能使用鑲嵌製程或雙鑲嵌製程來形成前側重佈線結構140。作為一實例，在圖3中所示的處理之後，考慮前側重佈線結構在模製材料130上方及晶粒120上方逐層形成的情況。可包括有機化合物(諸如，聚合物)的模製材料130可能無法耐受與用於鑲嵌/雙鑲嵌製程中的CVD沈積製程相關的高溫(例如，超過400℃)。因此，鑲嵌/雙鑲嵌製程可能無法成為用於在模製材料130上方形成前側重佈線結構的選擇方案。藉由在比模製材料130更耐受高溫的載體133上方形成重佈線結構140，本揭露克服模製材料130的熱積存(thermal budge)限制，從而允許使用鑲嵌/雙鑲嵌製程來形成重佈線結構140。
在一些實施例中，相較於藉由不使用鑲嵌/雙鑲嵌製程在模製材料130上方形成重佈線結構的形成方法所達成的重佈線結構，使用鑲嵌/雙鑲嵌製程形成的重佈線結構140達成導電線之間的更精細節距。另外，使用鑲嵌/雙鑲嵌製程所形成的通孔的大小亦更小，從而允許更高積體密度。另外，藉由例如在另一地方及/或在將重佈線結構140附接至半導體封裝體之前預先形成重佈線結構140，可減少形成最終產品的處理時間，從而提高生產量。
根據一些實施例，在將重佈線結構140附接至導電柱119/晶粒連接件128之前，對晶粒120執行測試以確認晶粒120為良裸晶粒(known good die；KGD)。預先成形的重佈線結構140僅附接至KGD，且功能測試不合格的晶粒不與重佈線結構140附接。此節約生產成本且改良製造製程的積體良率。
隨後，如圖5A中所示，執行回焊製程以將重佈線結構140的第二側140L上的導電襯墊147接合至導電柱119且接合至 晶粒連接件128。焊料區域148在導電襯墊147與導電柱119之間以及導電襯墊147與晶粒連接件128之間形成。在接合之後，重佈線結構140電性耦接至晶粒120且電性耦接至重佈線結構110。如圖5A中所示，半導體封裝體100現在包含重佈線結構140。歸因於焊料區域148及導電襯墊147，重佈線結構140與模製材料130之間存在間隙。換言之，重佈線結構140的第二側140L與模製材料130面向重佈線結構140的表面間隔開，所述第二側為重佈線結構140最接近於模製材料130的表面。
圖5B示出圖5A的半導體封裝體100的平面視圖，且圖5A為沿圖5B中的線A-A的橫截面視圖。在圖5A及圖5B的實例中，每一載體133上形成有單一重佈線結構(例如，重佈線結構140)。載體133及重佈線結構140在圖5B的平面視圖中可具有相同大小，因此如圖5B中所示，載體133的邊界與重佈線結構140的邊界重疊。另外，模製材料130及重佈線結構110在圖5B的平面視圖中可具有相同大小，且因此，模製材料130的邊界與重佈線結構110的邊界重疊。在一些實施例中，多個半導體封裝體100同時在載體101上形成且將在後續處理中經單體化(例如，藉由切割製程單體化)以形成多個獨立的半導體封裝體，在所述情況下，模製材料130的邊界及重佈線結構110的邊界在切割製程之後對應於獨立半導體封裝體100的各別邊界。
在一些實施例中，重佈線結構140的寬度W1小於模製材料130的寬度W2。在一些實施例中，重佈線結構140的深度D1小於模製材料130的深度D2。如圖5B中所示，重佈線結構140設置於模製材料130的邊界內(且在重佈線結構110的邊界內)。
隨後，在圖6中，載體133藉由合適的製程自重佈線結構140剝離，所述製程諸如蝕刻、研磨或機械剝離。在黏著層(例如，LTHC膜)形成於載體133與重佈線結構140之間的一實施例中，藉由將雷射或UV光照射在載體133的表面上來剝離載體133。雷射或UV光破壞黏合至載體133的黏著層的化學鍵，且隨後可容易地剝離載體133。
在剝離載體133之後，暴露重佈線結構140的第一側140U。隨後，鈍化層153在第一側140U上方形成。鈍化層153可由一或多種合適的介電材料(諸如，PBO)形成，但可替代地利用任何合適的材料，諸如聚醯亞胺或聚醯亞胺衍生物。鈍化層153可使用例如旋塗製程形成，但可替代地使用任何合適的方法。
隨後，在鈍化層153中形成開口以暴露重佈線結構140的第一側140U處的導電特徵146。在開口形成之後，凸塊下金屬化物(under bump metallization；UBM)結構151可形成為與導電特徵146電性接觸。在一實施例中，UBM結構151包括三個導電材料層，諸如鈦層、銅層以及鎳層。然而，存在許多合適的材料及層配置，諸如鉻/鉻銅合金/銅/金配置、鈦/鈦鎢/銅配置或銅/鎳/金配置，所述材料及層配置適用於形成UBM結構151。可用於UBM結構151的任何合適的材料或材料層全部意欲包含於本揭露的範疇內。
UBM結構151可藉由在鈍化層153上方且沿開口的內部穿過鈍化層153到達導電特徵146來形成每一層而產生。可使用諸如電化學鍍覆的鍍覆製程來執行每一層的形成，但取決於所用材料，可替代地使用其他形成製程，諸如濺鍍、蒸鍍或PECVD製 程。一旦已形成UBM結構層，即可執行合適的微影及/或蝕刻製程以移除層的部分且使UBM結構151保留經設計形狀，諸如圓形、八邊形、正方形或矩形，但可替代地形成任何合適的形狀。
隨後，在UBM結構151上形成外部連接件155。在一實施例中，外部連接件155可為諸如受控塌陷晶粒連接(controlled collapse chip connection；C4)凸塊的接觸凸塊，且包括諸如錫的材料或諸如銀或銅的其他合適材料。在外部連接件155為錫焊料凸塊的一實施例中，外部連接件155可藉由以下方式形成：初始地經由諸如蒸鍍、電鍍、印刷、焊料轉移、植球或類似方法的任何合適方法形成錫層。一旦已在所述結構上形成錫層，即執行回焊以便將材料塑形為具有例如約80微米直徑的凸塊形狀。
然而，儘管已在上文將外部連接件155描述為C4凸塊，但此等凸塊僅意欲為說明性的且不意欲限制實施例。更確切地說，可替代地利用任何合適類型的外部接觸件，諸如球柵陣列封裝(ball grid array；BGA)、微凸塊、銅柱、銅層、鎳層、無鉛(lead free；LF)層、化學鍍鎳鈀浸金(electroless nickel electroless palladium immersion gold；ENEPIG)層、Cu/LF層、Sn/Ag層、Sn/Pb、此等之組合或其類似物。任何合適的外部連接件以及用於形成外部連接件的任何合適的製程可用於外部連接件155，且所有此類外部連接件全部意欲包含於實施例的範疇內。
隨後，在圖7中，翻轉半導體封裝體100，且將外部連接件155附接至由支架157支撐的膠帶159。膠帶159可為在後續處理中用於將半導體封裝體100固持在原位的切割膠帶，其可為黏著劑。隨後，經由剝離製程將載體101自半導體封裝體100剝離。 剝離製程可使用諸如蝕刻、研磨以及機械剝落的任何合適的製程來移除載體101。在載體101與重佈線結構110之間使用諸如LTHC膜的黏著層的實施例中，藉由將雷射或UV光照射在載體101的表面上來剝離載體101。雷射或UV光破壞接合至載體101的黏著層的化學鍵，且隨後可容易地剝離載體101。
隨後，在圖8中，在重佈線結構110的介電層中形成開口116以暴露重佈線結構110的導電特徵114(例如，導電襯墊)。雷射鑽孔製程、微影及/或蝕刻製程或類似製程可用以形成開口116。
接下來參考圖9，半導體封裝體160(諸如，包含記憶體裝置的封裝體)附接至圖8中所示的半導體封裝體100以形成圖9中的半導體封裝體100，從而形成具有疊層封裝(package-on-package；PoP)結構的半導體封裝體100。
如圖9中所示，半導體封裝體160具有基底161以及附接至基底161的上部表面的一或多個半導體晶粒162(例如，記憶體晶粒)。在一些實施例中，基底161包含矽、砷化鎵、絕緣層上矽(「SOI」)或其他類似材料。在一些實施例中，基底161為多層電路板。在一些實施例中，基底161包含雙馬來醯亞胺三嗪(bismaleimide triazine；BT)樹脂、FR-4(由編織玻璃纖維布與耐火的環氧樹脂黏合劑形成的複合材料)、陶瓷、玻璃、塑膠、膠帶、膜或其他支撐材料。基底161可包含形成於基底161中/上的導電特徵(例如，導電線及通孔，未圖示)。如圖9中所示，基底161具有形成於基底161的上部表面及下部表面上的導電襯墊163，所述導電襯墊163電性耦接至基底161的導電特徵。一或多個半導 體晶粒162藉由例如接線167電性耦接至導電襯墊163。可包括環氧樹脂、有機聚合物、聚合物或其類似物的模製材料165在基底161上方及半導體晶粒162周圍形成。如圖9中所示，模製材料165與基底161相接。
半導體封裝體160藉由導電接合點168電性耦接及機械耦接至重佈線結構110，所述導電接合點可藉由接合半導體封裝體160的外部連接件與重佈線結構110的導電特徵114而形成。在一些實施例中，導電接合點168包括焊料區域、導電柱(例如，在銅柱的末端表面上具有焊料區域的銅柱)或任何其他合適的導電接合點。
儘管未圖示，但可在形成導電接合點168之後執行切割處理以使半導體封裝體100與在相同處理步驟中形成的其他相鄰半導體封裝體(未圖示)分離，從而形成多個獨立的半導體封裝體100。
圖10示出半導體封裝體100A的橫截面視圖，所述半導體封裝體類似於圖9的半導體封裝體100，且在一些實施例中可使用圖1至圖9中所示的類似處理過程形成，但不具有重佈線結構140與導電柱119/晶粒連接件128之間的焊料區域148(參見圖9)。除非另外指定，否則圖10中的類似標號指代圖1至圖9中的類似部件。舉例而言，具有相同標號的組件可由相同或類似材料形成，且可使用相同或類似形成方法形成。為簡潔起見，不重複細節。
參考圖10，為了將重佈線結構140接合至導電柱119/晶粒連接件128，執行直接接合製程以使得導電襯墊147(例如，銅 襯墊)直接接合至導電柱119(例如，銅柱)且直接接合至晶粒連接件128(例如，銅晶粒連接件)。因此，導電襯墊147與導電柱119/晶粒連接件128之間不存在焊料區域。如圖10中所示，由於設置於其間的導電襯墊147，重佈線結構140與模製材料130之間存在間隙。換言之，重佈線結構140的第二側140L與模製材料130面向重佈線結構140的表面間隔開。
圖11A、圖11B以及圖12示出根據一實施例的各製造階段的半導體封裝體200的各種視圖(例如，橫截面視圖及平面視圖)。除非另外指定，否則圖11A、圖11B以及圖12中的類似標號指代圖1至圖9中的類似部件。舉例而言，具有相同標號的組件可由相同或類似材料形成，且可使用相同或類似形成方法形成。為簡潔起見，可能不會重複細節。
首先參考圖11A，兩個預先成形的重佈線結構140A及預成形重佈線結構140B分別附接至半導體封裝體200的第一區域310及半導體封裝體200的第二區域320。圖11B為圖11A中的半導體封裝體200的平面視圖，且圖11A為沿圖11B的線B-B的橫截面視圖。
如圖11B的平面視圖中所示，重佈線結構140A及重佈線結構140B彼此實體分離，且可具有不同大小(例如，長度、寬度以及面積)。圖11B更繪示第三預先成形重佈線結構140C，其在圖11A的橫截面視圖中不可見。如圖11B中所示，重佈線結構140A/重佈線結構140B/重佈線結構140C中的每一者的大小小於底層模製材料130的大小(或重佈線結構110的大小)。在多個半導體封裝體200形成於載體101上的實施例中，圖11B中的模製 材料130的邊界對應於切割製程後獨立半導體封裝體200的邊界，模製材料130的所述邊界與圖11B中的重佈線結構110的邊界重疊。
仍參考圖11B，重佈線結構140A/重佈線結構140B/重佈線結構140C的面積總和小於模製材料130的面積。圖11B更繪示電子裝置171，諸如表面安裝裝置(surface mount device；SMD)或積體被動裝置(integrated passive device；IPD)，所述電子裝置例如在半導體封裝體200的區域330(參見圖11A)中附接至模製材料130的上部表面。
返回參考圖11A，使用與圖4中的重佈線結構140相同或類似的形成方法在各別載體(未圖示)上預先形成重佈線結構(例如，重佈線結構140A、重佈線結構140B、重佈線結構140C)。詳言之，鑲嵌及/或雙鑲嵌製程可用於形成重佈線結構140A/重佈線結構140B/重佈線結構140C。類似於圖4及圖5A中所示的處理過程，重佈線結構140A/重佈線結構140B/重佈線結構140C接合至半導體封裝體200的各別區域(例如，區域310、區域320或區域330)中的導電特徵(例如，導電柱119、晶粒連接件128)。焊料區域148在重佈線結構140A/重佈線結構140B/重佈線結構140C與各別導電特徵之間形成。由於焊料區域148及導電襯墊147，重佈線結構140A/重佈線結構140B/重佈線結構140C與模製材料130之間存在間隙。換言之，重佈線結構(例如，重佈線結構140A)的第二側140L與模製材料130面向重佈線結構(例如，重佈線結構140A)的表面間隔開。圖11A更示出接合(例如，藉由焊料區域接合)至晶粒連接件128且設置於重佈線結構140A與重佈線結 構140B之間的電子裝置171。
在接合至半導體封裝體100之後，剝離附接至重佈線結構140A/重佈線結構140B/重佈線結構140C的載體。使用與圖6中所示相同或類似的製程來形成鈍化層153、UBM結構151以及外部連接件155。
隨後，如圖12中所示，使用圖7至圖9中所示的相同或類似處理過程，經由導電接合點168將半導體封裝體160附接至重佈線結構110。儘管圖中未示，但可在形成導電接合點168之後執行切割處理以使半導體封裝體200與在相同處理步驟中形成的其他相鄰半導體封裝體(未圖示)分離，從而形成多個獨立的半導體封裝體200。
圖13示出半導體封裝體200A的橫截面視圖，所述半導體封裝體類似於圖12的半導體封裝體200，且可使用圖1至圖9中所示類似的處理程序形成，但在一些實施例中不具有重佈線結構(例如，重佈線結構140A、重佈線結構140B、重佈線結構140C)與導電柱119/晶粒連接件128之間的焊料區域148(參見圖12)。除非另外指定，否則圖13中的類似標號指代圖12中的類似部件。舉例而言，具有相同標號的組件可由相同或類似材料形成，且可使用相同或類似形成方法形成。為簡潔起見，不重複細節。
參考圖13，為了將重佈線結構140A/重佈線結構140B接合至導電柱119/晶粒連接件128，執行直接接合製程以使得導電襯墊147(例如，銅襯墊)直接接合至導電柱119(例如，銅柱)且直接接合至晶粒連接件128(例如，銅晶粒連接件)。因此，導電襯墊147與導電柱119/晶粒連接件128之間不存在焊料區域。在 一些實施例中，電子裝置171可藉由焊料區域接合至各別晶粒連接件128，且在其他實施例中，電子裝置171可在其間不具有焊料區域的情況下直接接合(例如，使用直接接合製程來接合)至晶粒連接件128。由於導電襯墊147，重佈線結構140A/重佈線結構140B與模製材料130之間存在間隙。換言之，重佈線結構(例如，重佈線結構140A)的第二側140L與模製材料130面向重佈線結構(例如，重佈線結構140A)的表面間隔開。
所揭露實施例的變型為可能的且全部意欲包含於本揭露的範疇內。舉例而言，作為非限制性實例，一個半導體晶粒120用於各實施例中，然而，兩個或多於兩個半導體晶粒可附接至重佈線結構110而在不背離本揭露的精神。作為另一實例，作為一實例，在圖11B中三個預製的重佈線結構140A/重佈線結構140B/重佈線結構140C附接至半導體封裝體200，但多於或少於三個預製的重佈線結構可附接至半導體封裝體。儘管圖中未示出，但作為另一實例，底填充材料可在重佈線結構(例如，重佈線結構140、重佈線結構140A、重佈線結構140B)與模製材料130之間的間隙中形成。在一些實施例中，底填充材料可完全填充間隙，且在其他實施例中，底填充材料可在導電襯墊147周圍及焊料區域148(若形成)周圍形成且間隙的其他區域未經填充(例如，空的)。
實施例可達成優點。舉例而言，本發明所揭露的方法允許重佈線結構(例如，重佈線結構140、重佈線結構140A、重佈線結構140B)在附接之前預先成形。此減少處理時間且提高生產率。由於重佈線結構可在載體而非模製材料上方預先成形，因此避免了模製材料的熱限制，且鑲嵌及/或雙鑲嵌製程可用於形成重 佈線結構，此情形得到更精細的線節距及更小的通孔大小，由此獲得電連接可靠性增加的高積體密度。另外，本發明所揭露的方法允許在附接預製的重佈線結構之前對晶粒進行功能測試，由此藉由跳過(例如，不將預製的重佈線結構附接至)功能測試不合格的晶粒而改良積體良率。
圖14示出根據一些實施例的製造半導體元件的方法的流程圖。應理解，圖14中所示的實施例方法1000僅為許多可能實施例方法的一個實例。本領域一般技術人員將認識到許多變型、替代物以及修改。舉例而言，可添加、移除、置換、重新配置以及重複如圖14中所示的各種步驟。
參考圖14，在步驟1010處，用模製材料包圍晶粒及接近所述晶粒的導電柱，其中晶粒及導電柱設置於第一重佈線結構的第一側上方，其中第一重佈線結構的與第一側相對的第二側附接至第一載體。在步驟1020處，將設置於預製的第二重佈線結構的第一表面上方的導電襯墊接合至晶粒且接合至導電柱，其中預製的第二重佈線結構的與第一表面相對的第二表面附接至第二載體。在步驟1030處，在接合導電襯墊之後，移除第二載體以暴露預製的第二重佈線結構的接近第二表面的導電特徵。在步驟1040處，在預製的第二重佈線結構的導電特徵上方形成導電凸塊且所述導電凸塊電性耦接至所述導電特徵。
在一實施例中，一種形成半導體封裝體的方法包含：在第一載體上方形成第一重佈線結構；在第一重佈線結構上方形成導電柱；將第一晶粒的第一側附接至鄰近於導電柱的第一重佈線結構，第一晶粒的第二側背向第一重佈線結構，所述第一晶粒的 第二側上設置有晶粒連接件；在第一重佈線結構上方形成模製材料，所述模製材料包圍第一晶粒及導電柱；將第二重佈線結構的第一側接合至晶粒連接件且接合至導電柱，與第二重佈線結構的第一側相對的第二重佈線結構的第二側附接至第二載體；在接合第二重佈線結構的第一側之後，移除第二載體以暴露第二重佈線結構的第二側上的導電特徵；以及在移除第二載體之後，在第二重佈線結構的第二側上的導電特徵上形成導電凸塊。在一實施例中，第二重佈線結構在接合之前經預製。在一實施例中，在接合之後，模製材料中遠離第一重佈線結構的頂部表面與第二重佈線結構中的最接近模製材料的介電層間隔開。在一實施例中，接合包括將第二重佈線結構的第一側上的導電襯墊接合至晶粒連接件且接合至導電柱。在一實施例中，導電襯墊藉由焊接接頭接合至晶粒連接件且接合至導電柱。在一實施例中，使用直接接合製程將導電襯墊接合至晶粒連接件且接合至導電柱，其中導電襯墊在接合之後實體地接觸晶粒連接件及導電柱。在一實施例中，形成導電凸塊包含：在移除第二載體之後，在第二重佈線結構的第二側上方形成鈍化層；在鈍化層中形成凸塊下金屬化物(UBM)結構，所述凸塊下金屬化物結構電性耦接至第二重佈線結構的第二側上的導電特徵；以及在凸塊下金屬化物結構上方形成導電凸塊。在一實施例中，所述方法更包含：移除第一載體以暴露第一重佈線結構的第一側；在第一重佈線結構的第一側中形成開口，所述開口暴露第一重佈線結構的導電特徵；以及將半導體元件的外部連接件接合至第一重佈線結構的經暴露導電特徵。在一實施例中，在平面視圖中，第二重佈線結構的第一面積小於模製材料 的第二面積，其中所述方法更包含：將第三重佈線結構的第一側接合至晶粒連接件且接合至導電柱，與第三重佈線結構的第一側相對的第三重佈線結構的第二側附接至第三載體；以及在接合第三重佈線結構的第一側之後，移除第三載體以暴露第三重佈線結構的第二側上的導電特徵。在一實施例中，在平面視圖中，第三重佈線結構的第三面積小於模製材料的第二面積，其中第一面積及第三面積的總和小於第二面積。在一實施例中，所述方法更包含將電子裝置接合至第一晶粒的晶粒連接件，其中所述電子裝置在第二重佈線結構與第三重佈線結構之間。
在一實施例中，一種形成半導體封裝體的方法包含：用模製材料包圍晶粒及接近所述晶粒的導電柱，其中晶粒及導電柱設置於第一重佈線結構的第一側上方，其中第一重佈線結構的與第一側相反的第二側附接至第一載體；將設置於預製的第二重佈線結構的第一表面上的導電襯墊接合至晶粒且接合至導電柱，其中預製的第二重佈線結構的與第一表面相對的第二表面附接至第二載體；在接合導電襯墊之後，移除第二載體以暴露預製的第二重佈線結構的接近第二表面的導電特徵；以及在預製的第二重佈線結構的導電特徵上方形成導電凸塊且所述導電凸塊電性耦接至所述導電特徵。在一實施例中，第一重佈線結構的第一寬度等於模製材料的第二寬度，且其中預製的第二重佈線結構的第三寬度小於第一寬度。在一實施例中，所述方法更包含在接合導電襯墊之後且在形成導電凸塊之前：在預製的第二重佈線結構上方形成鈍化層；以及形成延伸至鈍化層中且電性耦接至預製的第二重佈線結構的導電特徵的金屬特徵。在一實施例中，在接合之後，預 製的第二重佈線結構中面向晶粒的最下部表面與模製材料中面向預製的第二重佈線結構的上部表面實體分離。在一實施例中，所述方法更包含：移除第一載體；在第一重佈線結構中形成開口以暴露第一重佈線結構的導電特徵；以及將半導體元件接合至第一重佈線結構的導電特徵。
在一實施例中，一種半導體封裝體包含：晶粒及導電柱，嵌入於模製材料中；第一重佈線結構，在晶粒的第一側上且電性耦接至導電柱；以及第二重佈線結構，在晶粒的與第一側相對的第二側上，其中所述晶粒在晶粒的第二側上具有晶粒連接件，其中第二重佈線結構電性耦接至晶粒連接件及導電柱，且其中第二重佈線結構的第二寬度不同於第一重佈線結構的第一寬度。在一實施例中，所述半導體封裝體更包含晶粒連接件與第二重佈線結構之間的焊料區域。在一實施例中，第一重佈線結構與模製材料相接，其中第二重佈線結構的寬度小於模製材料的寬度。在一實施例中，第二重佈線結構中最接近於晶粒的介電層與模製材料間隔開。
前文概述若干實施例的特徵以使得本領域技術人員可較佳地理解本揭露的態樣。本領域技術人員應瞭解，其可易於使用本揭露內容作為設計或修改用於實現本文中所引入實施例的相同目的及/或達成相同優點的其他方法及結構的基礎。本領域技術人員亦應認識到，此類等效構造並不脫離本揭露內容的精神及範疇，且本領域技術人員可在不脫離本揭露內容的精神及範疇的情況下在本文中作出改變、替代及更改。
1000‧‧‧方法
1010、1020、1030、1040‧‧‧步驟

Claims (11)

  1. 一種形成半導體封裝體的方法，包括：在第一載體上方形成第一重佈線結構；在所述第一重佈線結構上方形成導電柱；將第一晶粒的第一側附接至鄰近於所述導電柱的所述第一重佈線結構，所述第一晶粒的第二側背向所述第一重佈線結構，所述第一晶粒的所述第二側上設置有晶粒連接件；在所述第一重佈線結構上方形成模製材料，所述模製材料包圍所述第一晶粒及所述導電柱；將第二重佈線結構的第一側接合至所述晶粒連接件且接合至所述導電柱，與所述第二重佈線結構的所述第一側相對的所述第二重佈線結構的第二側附接至第二載體；在接合所述第二重佈線結構的所述第一側之後，移除所述第二載體以暴露所述第二重佈線結構的所述第二側上的導電特徵；以及在移除所述第二載體之後，在所述第二重佈線結構的所述第二側上的所述導電特徵上形成導電凸塊，其中形成所述導電凸塊包括：在所述第二重佈線結構的所述第二側上方形成鈍化層；在所述鈍化層中形成凸塊下金屬化物結構，所述凸塊下金屬化物結構電性耦接至所述第二重佈線結構的所述第二側上的所述導電特徵；以及在所述凸塊下金屬化物結構上方形成所述導電凸塊。
  2. 如申請專利範圍第1項所述的方法，其中所述第二重佈 線結構在所述接合步驟之前經預製。
  3. 如申請專利範圍第1項所述的方法，其中所述接合步驟包括將所述第二重佈線結構的所述第一側上的導電襯墊接合至所述晶粒連接件且接合至所述導電柱。
  4. 如申請專利範圍第1項所述的方法，更包括：移除所述第一載體以暴露所述第一重佈線結構的第一側；在所述第一重佈線結構的所述第一側中形成開口，所述開口暴露所述第一重佈線結構的導電特徵；以及將半導體元件的外部連接件接合至所述第一重佈線結構的所述經暴露導電特徵。
  5. 一種形成半導體封裝體的方法，包括：在第一載體上方形成第一重佈線結構；在所述第一重佈線結構上方形成導電柱；將第一晶粒的第一側附接至鄰近於所述導電柱的所述第一重佈線結構，所述第一晶粒的第二側背向所述第一重佈線結構，所述第一晶粒的所述第二側上設置有晶粒連接件；在所述第一重佈線結構上方形成模製材料，所述模製材料包圍所述第一晶粒及所述導電柱；將第二重佈線結構的第一側接合至所述晶粒連接件且接合至所述導電柱，與所述第二重佈線結構的所述第一側相對的所述第二重佈線結構的第二側附接至第二載體，其中在平面視圖中，所述第二重佈線結構的第一面積小於所述模製材料的第二面積；在接合所述第二重佈線結構的所述第一側之後，移除所述第二載體以暴露所述第二重佈線結構的所述第二側上的導電特徵； 在移除所述第二載體之後，在所述第二重佈線結構的所述第二側上的所述導電特徵上形成導電凸塊；將第三重佈線結構的第一側接合至所述晶粒連接件且接合至所述導電柱，與所述第三重佈線結構的所述第一側相對的所述第三重佈線結構的第二側附接至第三載體；以及在所述接合所述第三重佈線結構的所述第一側之後，移除所述第三載體以暴露所述第三重佈線結構的所述第二側上的導電特徵。
  6. 一種形成半導體封裝體的方法，包括：用模製材料包圍晶粒及接近所述晶粒的導電柱，其中所述晶粒及所述導電柱設置於第一重佈線結構的第一側上方，其中所述第一重佈線結構的與所述第一側相對的第二側附接至第一載體；將設置於預製的第二重佈線結構的第一表面上的導電襯墊接合至所述晶粒且接合至所述導電柱，其中所述預製的第二重佈線結構的與所述第一表面相對的第二表面附接至第二載體；在接合所述導電襯墊之後，移除所述第二載體以暴露所述預製的第二重佈線結構的接近所述第二表面的導電特徵；在移除所述第二載體後，在所述預製的第二重佈線結構的所述第二表面上方形成鈍化層；形成延伸至所述鈍化層中且電性耦接至所述預製的第二重佈線結構的所述導電特徵的金屬特徵；以及在所述金屬特徵上方形成導電凸塊且所述導電凸塊電性耦接至所述金屬特徵。
  7. 如申請專利範圍第6項所述的方法，其中所述第一重佈 線結構的第一寬度等於所述模製材料的第二寬度，且其中所述預製的第二重佈線結構的第三寬度小於所述第一寬度。
  8. 如申請專利範圍第6項所述的方法，更包括：移除所述第一載體；在所述第一重佈線結構中形成開口以暴露所述第一重佈線結構的導電特徵；以及將半導體元件接合至所述第一重佈線結構的所述導電特徵。
  9. 一種半導體封裝體，包括：晶粒及導電柱，嵌入於模製材料中；第一重佈線結構，在所述晶粒的第一側上且電性耦接至所述導電柱；以及第二重佈線結構，在所述晶粒的與所述第一側相對的第二側上，其中所述晶粒在所述晶粒的所述第二側上具有晶粒連接件，其中所述第二重佈線結構電性耦接至所述晶粒連接件及所述導電柱，所述第二重佈線結構的第二寬度不同於所述第一重佈線結構的第一寬度，且所述第二重佈線結構的第二線節距小於所述第一重佈線結構的第一線節距。
  10. 如申請專利範圍第9項所述的半導體封裝體，更包括所述晶粒連接件與所述第二重佈線結構之間的焊料區域。
  11. 如申請專利範圍第9項所述的半導體封裝體，其中所述第一重佈線結構與所述模製材料相接，其中所述第二重佈線結構的寬度小於所述模製材料的寬度。
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