CN109786260A - 多芯片集成扇出封装件 - Google Patents

多芯片集成扇出封装件 Download PDF

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Publication number
CN109786260A
CN109786260A CN201811355127.XA CN201811355127A CN109786260A CN 109786260 A CN109786260 A CN 109786260A CN 201811355127 A CN201811355127 A CN 201811355127A CN 109786260 A CN109786260 A CN 109786260A
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Prior art keywords
redistribution structure
conductive
tube core
molding material
redistribution
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CN201811355127.XA
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CN109786260B (zh
Inventor
陈洁
陈宪伟
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

方法包括用模制材料包围管芯和接近管芯的导电柱，其中，管芯和导电柱设置在第一再分布结构的第一侧上方，其中，第一再分布结构的与第一侧相对的第二侧附接至第一载体；将设置在预制第二再分布结构的第一表面上的导电焊盘接合至管芯和导电柱，其中，预制第二再分布结构的与第一表面相对的第二表面附接至第二载体；在接合导电焊盘之后，去除第二载体以暴露预制第二再分布结构的接近第二表面的导电部件；并且在预制第二再分布结构的导电部件上方形成电连接至预制第二再分布结构的导电部件的导电凸块。本发明的实施例还涉及多芯片集成扇出封装件。

Description

多芯片集成扇出封装件
技术领域
本发明的实施例涉及多芯片集成扇出封装件。
背景技术
由于各个电组件(例如，晶体管、二极管、电阻器、电容器等)的集成密度的持续改进，半导体工业已经经历了快速增长。对于大部分而言，这种集成密度的改进来自于最小部件尺寸的连续减小，这使得更多的组件集成到给定的区域。随着近来对更小的电子器件的需求的增长，对于半导体管芯的更小且更具创造性的封装技术的需求也已增长。
这些封装技术的实例是叠层封装(POP)技术。在PoP封装件中，顶部半导体封装件堆叠在底部半导体封装件的顶部上，以允许高水平的集成和组件密度。另一实例是多芯片模块(MCM)技术，其中，多个半导体管芯封装在一个半导体封装件中以为半导体器件提供集成功能。
先进的封装技术的高度集成使得能够生产具有增强功能和较小的覆盖区的半导体器件，这对于诸如手机、平板电脑和数字音乐播放器的小型器件是有利的。另一优势是缩短连接半导体封装件内的互操作部分的导电路径的长度。这改进了半导体器件的电性能，因为电路之间的互连的较短路由产生了更快的信号传播并且减少了噪声和串扰。
发明内容
本发明的实施例提供了一种形成半导体封装件的方法，包括：在第一载体上方形成第一再分布结构；在所述第一再分布结构上方形成导电柱；将第一管芯的第一侧附接至邻近所述导电柱的所述第一再分布结构，所述第一管芯的第二侧远离所述第一再分结构，所述第一管芯的第二侧上设置有管芯连接件；在所述第一再分布结构上方形成模制材料，所述模制材料包围所述第一管芯和所述导电柱；将第二再分布结构的第一侧接合至所述管芯连接件和所述导电柱，将与所述第二再分布结构的第一侧相对的所述第二再分布结构的第二侧附接至第二载体；在接合所述第二再分布结构的第一侧之后去除所述第二载体以暴露所述第二再分布结构的第二侧上的导电部件；以及在去除所述第二载体之后，在所述第二再分布结构的第二侧上的所述导电部件上形成导电凸块。
本发明的另一实施例提供了一种形成半导体封装件的方法，包括：用模制材料包围管芯和接近所述管芯的导电柱，其中，所述管芯和所述导电柱设置在第一再分布结构的第一侧上方，其中，所述第一再分布结构的与第一侧相对的第二侧附接至第一载体；将设置在预制第二再分布结构的第一表面上的导电焊盘接合至所述管芯和所述导电柱，其中，所述预制第二再分布结构的与所述第一表面相对的第二表面附接至第二载体；在接合所述导电焊盘之后，去除所述第二载体以暴露所述预制第二再分布结构的接近所述第二表面的导电部件；以及在所述预制第二再分布结构的导电部件上方形成导电凸块，所述导电凸块电连接至所述预制第二再分布结构的导电部件。
本发明的又一实施例提供了一种半导体封装件，包括：管芯和导电柱，嵌入在模制材料内；第一再分布结构，位于所述管芯的第一侧上并且电连接至所述导电柱；以及第二再分布结构，位于所述管芯的与所述第一侧相对的第二侧上，其中，所述管芯在所述管芯的第二侧上具有管芯连接件，其中，所述第二再分布结构电连接至所述管芯连接件和所述导电柱，并且其中，所述第二再分布结构的第二宽度与所述第一再分布结构的第一宽度不同。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各个方面。应该指出，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1至图4、图5A、图5B和图6至图9示出了根据实施例的处于各个制造阶段的半导体封装件的各个视图。
图10示出了根据实施例的半导体封装件的截面图。
图11A、图11B和图12示出了根据实施例的处于各个制造阶段的半导体封装件的各个视图。
图13示出了根据实施例的半导体封装件的截面图。
图14示出了根据一些实施例的用于形成半导体封装件的方法的流程图。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。
而且，为便于描述，在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等空间相对术语，以描述如图所示的一个元件或部件与另一个(或另一些)原件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其它方式定向(旋转90度或在其它方位上)，而本文使用的空间相对描述符可以同样地作出相应的解释。
各个实施例中提供了半导体封装件和形成半导体封装件的方法。在一些实施例中，半导体封装件具有嵌入在模制材料内的管芯，以及位于管芯的相对侧上的再分布结构(例如，背侧再分布结构和前侧再分布结构)。在一些实施例中，前侧再分布结构在附接至管芯之前预形成。在一些实施例中，至少使用镶嵌工艺形成前侧再分布结构，并且因此，实现了导线之间的更精细间距和再分布结构的更高可靠性。
图1至图4、图5A、图5B和图6至图9示出了根据实施例的处于各个制造阶段的半导体封装件100的各个视图(例如，截面图、平面图)。在图1中，在载体101上方形成再分布结构110。再分布结构110包括形成在一个或多个介电层中的导电部件(例如，导线和通孔)。导电柱119形成在再分布结构110的上表面上方并且电连接至再分布结构110。
载体101可以由诸如玻璃的材料制成，但是也可以使用其它合适的材料，诸如硅、聚合物、聚合物复合材料、金属箔、陶瓷、玻璃环氧树脂、氧化铍或带。在载体101上方形成再分布结构110。再分布结构110包括导电部件，诸如导线(例如，115)和通孔(例如，117)的一层或多层，以及一个或多个介电层(例如，113)。为了简单起见，介电层113在图1中示出为一层，然而，如本领域技术人员容易理解的，介电层113可以包括多个介电层。
在一些实施例中，一个或多个介电层113由诸如聚苯并恶唑(PBO)、聚酰亚胺、苯并环丁烯(BCB)等的聚合物形成。在其它实施例中，一个或多个介电层113由诸如氮化硅的氮化物、诸如氧化硅、磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、硼掺杂的磷硅酸盐玻璃(BPSG)等的氧化物形成。可以通过诸如旋涂、化学汽相沉积(CVD)、层压等或它们的组合的任何可接受的沉积工艺形成一个或多个介电层113。
在一些实施例中，再分布结构110的导电部件包括由合适的导电材料(诸如铜、钛、钨、铝等)形成的导线(例如，115)、导电通孔(例如，117)。在一些实施例中，通过在再分布结构110的介电层中形成开口以暴露下面的导电部件，在介电层上方和开口中形成晶种层(未示出)，在晶种层上方形成具有设计的图案的图案化光刻胶，在设计的图案中和晶种层上方镀(例如，电镀或化学镀)导电材料，以及去除光刻胶和晶种层的其上未形成导电材料的部分来形成导电部件。
在一些实施例中，在形成再分布结构110之前，在载体101上方沉积或层压粘合层(未示出)。粘合层可以是光敏的，并且可以通过例如在随后的载体脱粘工艺中对载体101照射紫外(UV)光而容易地从载体101脱离。例如，粘合层可以是由明尼苏达州圣保罗的3M公司制造的光热转换(LTHC)涂层。
仍参照图1，在再分布结构110上方形成导电柱119。可以通过以下方法形成导电柱119：在再分布结构110上方形成晶种层；在晶种层上方形成图案化的光刻胶，其中，图案化的光刻胶中的每个开口均对应于待形成的导电柱119的位置；使用例如电镀或化学镀用诸如铜的导电材料填充开口；使用例如灰化或剥离工艺去除光刻胶；并且去除晶种层的其上未形成导电柱119的部分。
接下来，在图2中，将半导体管芯120(也可以称为管芯或集成电路(IC)管芯)附接至再分布结构110的上表面。诸如管芯附接膜(DAF)的粘合膜118可以用于将管芯120附接至再分布结构110。由于管芯120的背侧附接至再分布结构110，因此再分布结构110也可以被称为背侧再分布结构。
在粘合至再分布结构110之前，可以根据适用的制造工艺处理管芯120，以在管芯120中形成集成电路。例如，管芯120可以包括半导体衬底121，诸如掺杂或未掺杂的硅，或绝缘体上半导体(SOI)衬底的有源层。半导体衬底121可以包括其它半导体材料，例如锗；化合物半导体，包括碳化硅、砷化镓、磷化镓、氮化镓、磷化铟、砷化铟和/或锑化铟；合金半导体，包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP；或它们的组合。也可以使用诸如多层或梯度衬底的其它衬底。诸如晶体管、二极管、电容器、电阻器等的器件(未示出)可以形成在半导体衬底121中和/或上，并且可以通过互连结构122互连以形成集成电路，互连结构122包括例如位于半导体衬底121上的一个或多个介电层125中的金属化图案(例如，导线123和通孔124)。在一些实施例中，使用镶嵌和/或双镶嵌工艺形成互连结构122。
管芯120还包括制成外部连接的焊盘126，诸如铝焊盘。焊盘126位于可以称为管芯120的有源侧或前侧的位置上。钝化膜127形成在管芯120上并且位于焊盘126的部分上。开口穿过钝化膜127至焊盘126。诸如导电柱(例如，包括诸如铜的金属)的管芯连接件128延伸至钝化膜127的开口内并且机械和电连接至相应的焊盘126。可以通过例如镀等形成管芯连接件128。管芯连接件128电连接至管芯120的集成电路。
介电材料129形成在管芯120的有源侧上，诸如位于钝化膜127和管芯连接件128上。介电材料129横向密封管芯连接件128，并且介电材料129与管芯120横向共末端。介电材料129可以是聚合物，诸如聚苯并恶唑(PBO)、聚酰亚胺、苯并环丁烯(BCB)等；氮化物，诸如氮化硅等；氧化物，诸如氧化硅、磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、硼掺杂的磷硅酸盐玻璃(BPSG)等；或它们的组合，并且可以例如通过旋涂、层压、CVD等形成。
接下来，在图3中，在再分布结构110上方、管芯120周围和导电柱119周围形成模制材料130。例如，模制材料130可以包括添加或不添加硅基或玻璃填料的环氧树脂、有机聚合物、聚合物或其它材料。在一些实施例中，模制材料130包括施加时为凝胶型液体的液态模制材料(LMC)。当施加时，模制材料130也可以包括液体或固体。可选地，模制材料130可以包括其它绝缘和/或密封材料。在一些实施例中，使用晶圆级模塑工艺施加模制材料130。模制材料130可以使用例如压缩模塑、传递模塑或其它方法模塑。
接下来，在一些实施例中，使用固化工艺来固化模制材料130。固化工艺可以包括使用退火工艺或其它加热工艺将模制材料130加热至预定温度预定时间段。固化工艺也可以包括紫外(UV)曝光工艺、红外(IR)能量曝光工艺、它们的组合或它们与加热工艺的组合。可选地，可以使用其它方法来固化模制材料130。在一些实施例中，不包括固化工艺。
接下来，可以实施诸如化学和机械抛光(CMP)的平坦化工艺，以去除模制材料130的位于管芯120的正面上方的过量部分。在一些实施例中，在平坦化工艺之后，模制材料130、导电柱119和管芯连接件128具有共面的上表面。
接下来，参照图4，预形成的再分布结构140附接至图3所示的半导体封装件100。在图4示出的实例中，再分布结构140在附接至半导体封装件100之前形成在载体133上。再分布结构140包括形成在一个或多个介电层141中的导电部件(例如，导线143、通孔145)的一层或多层。载体133可以由硅(例如，块状硅)形成，但是其它合适的材料也可以适用于载体133。虽然未示出，但是在形成再分布结构140之前，可以在载体133上形成诸如LTHC膜的粘合层。
如图4示出的，再分布结构140的第一侧140U附接至载体133，并且在再分布结构140的与第一侧140U相对的第二侧140L上形成导电焊盘147(例如，铜焊盘)，其中，导电焊盘147电连接至再分布结构140的导电部件。可以在导电焊盘147上方形成焊料区域149(例如，焊膏)。虽然未在图4中示出，但是也可以在导电柱119的上表面上方和管芯连接件128的上表面上方形成焊料区域(例如，焊膏)。在各个实施例中，在随后的回流工艺中，焊料区域将用于形成再分布结构140和导电柱119/管芯连接件128之间的焊料接头。由于再分布结构140接合至管芯120的前侧，因此再分布结构140也可以称为前侧再分布结构。
在一些实施例中，使用与在半导体管芯中形成互连结构(例如，图2中的122)相同或类似的形成方法在载体133上方形成再分布结构140。具体地，使用镶嵌工艺和/或双镶嵌工艺形成再分布结构140。在镶嵌工艺的实施例中，使用诸如化学汽相沉积(CVD)的合适的沉积方法在载体133上方形成介电层。一旦形成介电层，则使用例如光刻和蚀刻工艺在介电层中形成诸如沟槽的开口。接下来，通过溅射、物理汽相沉积(PVD)等在开口中沉积可以包括钛(Ti)、钽(Ta)、氮化钛(TiN)、氮化钽(TaN)等或它们的组合的阻挡层。然后在阻挡层上方形成可以包括铜(Cu)、Ti、Ta、TiN、TaN或它们的组合的晶种层。接下来，通过例如电镀工艺或化学镀工艺在开口中和晶种层上方形成诸如铜的填充金属。填充金属可以过填充开口，并且可以形成在介电层的上表面上方。然后实施诸如CMP的平坦化工艺，以去除开口外部的填充金属的过量部分、阻挡层的过量部分以及晶种层的过量部分。开口内的剩余导电材料形成再分布结构140的导电部件(例如，一个导电部件层)。在双镶嵌工艺中，每个沟槽均可以具有上沟槽和下沟槽，其中，上沟槽对应于导线的位置，并且下沟槽对应于通孔的位置。然后在相同的工艺步骤中通过填充金属填充上沟槽和下沟槽，其中，填充的上沟槽形成导线，并且填充的下沟槽形成通孔。可以在上沟槽和下沟槽中形成阻挡层和晶种层，与镶嵌工艺的处理类似。
通过在载体133上方形成再分布结构140，可以使用镶嵌工艺和/或双镶嵌工艺来形成前侧再分布结构140。相比之下，在没有目前公开的方法的情况下，可能无法使用镶嵌工艺或双镶嵌工艺来形成前侧再分布结构140。例如，考虑在图3示出的工艺之后，在模制材料130上方和管芯120上方逐层形成前侧再分布结构的情况。可以包括诸如聚合物的有机化合物的模制材料130可能无法承受与镶嵌/双镶嵌工艺中使用的CVD沉积工艺相关的高温(例如，超过400℃)。因此，镶嵌/双镶嵌工艺可能不是用于在模制材料130上方形成前侧再分布结构的选择。本发明通过在载体133上方形成比模制材料130更耐高温的再分布结构140，克服了模制材料130的热预算限制，从而允许镶嵌/双镶嵌工艺适用于形成再分布结构140。
在一些实施例中，使用镶嵌/双镶嵌工艺形成的再分布结构140在导线之间实现比在模制材料130上方形成再分布结构而不使用镶嵌/双镶嵌工艺的形成方法所实现的更精细的间距。此外，使用镶嵌/双镶嵌工艺形成的通孔的尺寸也更小，允许更高的集成密度。此外，通过例如在不同位置处预先形成再分布结构140和/或在再分布结构140附接至半导体封装件之前，可以减少用于形成最终产品的工艺时间，从而增加生产量。
根据一些实施例，在将再分布结构140附接至导电柱119/管芯连接件128之前，实施管芯120的测试以确认管芯120是已知良好管芯(KGD)。预形成的再分布结构140仅附接至KGD，并且未通过功能测试的管芯未附接有再分布结构140。这节省了生产成本并且改进了制造工艺的集成良率。
接下来，如图5A示出的，实施回流工艺以将再分布结构140的第二侧140L上的导电焊盘147接合至导电柱119和管芯连接件128。在导电焊盘147和导电柱119之间，以及导电焊盘147和管芯连接件128之间形成焊料区域148。在接合之后，再分布结构140电连接至管芯120和再分布结构110。如图5A示出的，半导体封装件100现在包括再分布结构140。由于焊料区域148和导电焊盘147，在再分布结构140和模制材料130之间存在间隙。换句话说，再分布结构140的第二侧140L(再分布结构140的最靠近模制材料130的表面)与模制材料130的面向再分布结构140的表面间隔开。
图5B示出了图5A的半导体封装件100的平面图，并且图5A是沿着图5B中的线A-A的截面图。在图5A和图5B的实例中，每个载体133均具有形成在其上的单个再分布结构(例如，140)。载体133和再分布结构140在图5B的平面图中可以具有相同的尺寸，因此，如图5B示出的，载体133的边界与再分布结构140的边界重叠。此外，模制材料130和再分布结构110在图5B的平面图中可以具有相同的尺寸，并且因此，模制材料130的边界与再分布结构110的边界重叠。在一些实施例中，多个半导体封装件100同时形成在载体101上并且将在随后的工艺中被分割(例如，通过切割工艺)，以形成多个单独的半导体封装件，在这种情况下，模制材料130的边界和再分布结构110的边界对应于切割工艺之后的单独半导体封装件100的相应边界。
在一些实施例中，再分布结构140的宽度W1小于模制材料130的宽度W2。在一些实施例中，再分布结构140的深度D1小于模制材料130的深度D2。如图5B示出的，再分布结构140设置在模制材料130的边界内(并且在再分布结构110的边界内)。
接下来，在图6中，通过诸如蚀刻、研磨或机械剥离的合适的工艺使载体133从再分布结构140脱粘。在载体133和再分布结构140之间形成粘合层(例如，LTHC膜)的实施例中，通过在载体133的表面上方照射激光或UV光使载体133脱粘。激光或UV光破坏粘合层与载体133接合的化学键，并且然后可以容易地使载体133脱离。
在载体133脱粘之后，再分布结构140的第一侧140U暴露。接下来，在第一侧140U上方形成钝化层153。钝化层153可以由诸如PBO的一种或多种合适的介电材料制成，但是也可以可选地利用诸如聚酰亚胺或聚酰亚胺衍生物的任何合适的材料。可以使用例如旋涂工艺来形成钝化层153，但是可以可选地使用任何合适的方法。
接下来，在钝化层153中形成开口以暴露再分布结构140的第一侧140U处的导电部件146。在形成开口之后，可以形成与导电部件146电接触的凸块下金属(UBM)结构151。在实施例中，UBM结构151包括三个导电材料层，诸如钛层、铜层和镍层。然而，存在适合于形成UBM结构151的许多合适的材料和层的布置，诸如铬/铬-铜合金/铜/金的布置、钛/钛钨/铜的布置或铜/镍/金的布置。可以用于UBM结构151的任何合适的材料或材料层均完全旨在包括在本发明的范围内。
可以通过在钝化层153上方并且沿着开口的内部穿过钝化层153至导电部件146形成每个层来创建UBM结构151。可以使用诸如电化学镀的镀工艺来实施每层的形成，可以根据所使用的材料可选地使用诸如溅射、蒸发或PECVD工艺的其它形成工艺。一旦形成UBM结构的层，则可以实施合适的光刻和/或蚀刻工艺以去除部分层并且使UBM结构151保留为设计的形状，诸如圆形、八边形、正方形或矩形，但是可以可选地形成任何合适的形状。
接下来，在UBM结构151上形成外部连接件155。在实施例中，外部连接件155是诸如可控塌陷芯片连接(C4)凸块的接触凸块并且包括诸如锡的材料或诸如银或铜的其它合适的材料。在外部连接件155是锡焊料凸块的实施例中，可以通过首先由诸如蒸发、电镀、印刷、焊料转移、球植等任何合适的方法形成锡层来形成外部连接件155。一旦已经在结构上形成锡层，则可以实施回流以将材料成形为例如约80μm的直径的凸块形状。
然而，上面已经将外部连接件155描述为C4凸块，但是这些仅仅是说明性的，并且不旨在限制实施例。相反地，可以可选地利用任何合适类型的外部接触件，诸如球栅阵列(BGA)、微凸块、铜柱、铜层、镍层、无铅(LF)层、化学镀镍化学镀钯浸金(ENEPIG)层、Cu/LF层、Sn/Ag层、Sn/Pb、这些的组合等。任何合适的外部连接件和用于形成外部连接件的任何合适的工艺均可以用于外部连接件155，并且所有这些外部连接件均完全旨在包括在实施例的范围内。
接下来，在图7中，翻转半导体封装件100，并且将外部连接件155附接至由框架157支撑的带159。带159可以是切割带，其可以是粘合剂，用于随后的工艺中保持半导体封装件100位于适当的位置。接下来，通过脱粘工艺使载体101从半导体封装件100脱粘。脱粘工艺可以使用诸如蚀刻、研磨和机械剥离的任何合适的工艺去除载体101。在载体101和再分布结构110之间使用诸如LTHC膜的粘合层的实施例中，通过在载体101的表面上方照射激光或UV光来使载体101脱粘。激光或UV光破坏粘合层与载体101接合的化学键，并且然后可以容易地使载体101脱离。
接下来，在图8中，在再分布结构110的介电层中形成开口116以暴露再分布结构110的导电部件114(例如，导电焊盘)。可以使用激光钻孔工艺、光刻和/或蚀刻工艺等来形成开口116。
接下来参照图9，将诸如包括存储器器件的封装件的半导体封装件160附接至图8所示的半导体封装件100以形成图9中的半导体封装件100，从而形成具有叠层封装(PoP)结构的半导体封装件100。
如图9示出的，半导体封装件160具有衬底161和附接至衬底161的上表面的一个或多个半导体管芯162(例如，存储器管芯)。在一些实施例中，衬底161包括硅、砷化镓、绝缘体上硅(“SOI”)或其它类似的材料。在一些实施例中，衬底161是多层电路板。在一些实施例中，衬底161包括双马来酰亚胺三嗪(BT)树脂、FR-4(由编织玻璃纤维布和具有阻燃性的环氧树脂粘合剂组成的复合材料)、陶瓷、玻璃、塑料、带、膜或其它支撑材料。衬底161可以包括形成在衬底161中/上的导电部件(例如，导线和通孔，未示出)。如图9示出的，衬底161具有形成在衬底161的上表面和下表面上的导电焊盘163，导电焊盘163电连接至衬底161的导电部件。一个或多个半导体管芯162通过例如接合线167电连接至导电焊盘163。在衬底161上方和半导体管芯162周围形成可以包括环氧树脂、有机聚合物、聚合物等的模制材料165。如图9示出的，模制材料165与衬底161共末端。
半导体封装件160通过导电接头168电和机械连接至再分布结构110，导电接头168可以通过将半导体封装件160的外部连接件与再分布结构110的导电部件114接合而形成。在一些实施例中，导电接头168包括焊料区域、导电柱(例如，铜柱的端面上具有焊料区域的铜柱)或任何其它合适的导电接头。
虽然未示出，但是可以在形成导电接头168之后实施切割工艺以将半导体封装件100与在相同工艺步骤中形成的其它相邻半导体封装件(未示出)分离，从而形成多个单独的半导体封装件100。
图10示出了半导体封装件100A的截面图，该半导体封装件100A与图9的半导体封装件100类似，并且可以使用与在图1至图9示出的类似工艺形成，但是在再分布结构140和导电柱119/管芯连接件128之间没有焊料区域148(见图9)，在一些实施例中。除非另有说明，否则图10中的相同的标号表示图1至图9中的相同部分。例如，具有相同标号的组件可以由相同或类似的材料形成，并且可以使用相同或类似的形成方法形成。为了简单起见，不再重复细节。
参照图10，为了将再分布结构140接合至导电柱119/管芯连接件128，实施直接接合工艺，使得导电焊盘147(例如，铜焊盘)直接接合至导电柱119(例如，铜柱)并且直接接合至管芯连接件128(例如，铜管芯连接件)。因此，在导电焊盘147和导电柱119/管芯连接件128之间没有焊料区域。如图10示出的，由于导电焊盘147设置在其间，因此在再分布结构140和模制材料130之间存在间隙。换句话说，再分布结构140的第二侧140L与模制材料130的面向再分布结构140的表面间隔开。
图11A、图11B和图12示出了根据实施例的处于各个制造阶段的半导体封装件200的各个视图(例如，截面图和平面图)。除非另有说明，否则图11A、图11B和图12中的相同的标号表示图1至图9中的相同部分。例如，具有相同标号的组件可以由相同或类似的材料形成，并且可以使用相同或类似的形成方法形成。为了简单起见，可能不再重复细节。
首先参照图11A，分别将两个预形成的再分布结构140A和140B附接至半导体封装件200的第一区域310和半导体封装件200的第二区域320。图11B是图11A中的半导体封装件200的平面图，并且图11A是沿着图11B的线B-B的截面图。
如图11B的平面图示出的，再分布结构140A和140B的位置彼此物理分隔开，并且可以具有不同的尺寸(例如，长度、宽度和面积)。图11B还示出了第三预形成的再分布结构140C，其在图11A的截面图中不可见。如图11B示出的，每个再分布结构140A/140B/140C的尺寸均小于下面的模制材料130的尺寸(或再分布结构110的尺寸)。在载体101上形成多个半导体封装件200的实施例中，图11B中的模制材料130的边界(其与图11B中的再分布结构110的边界重叠)对应于切割工艺之后的单独半导体封装件200的边界。
仍参照图11B，再分布结构140A/140B/140C的面积的总和小于模制材料130的面积。图11B还示出了电子器件171，诸如表面安装器件(SMD)或集成无源器件(IPD)，其附接至模制材料130的上表面，例如，附接至半导体封装件200的区域330(见图11A)。
返回参照图11A，使用与图4中的再分布结构140相同或类似的形成方法，在相应的载体(未示出)上预形成再分布结构(例如，140A、140B、140C)。具体地，镶嵌和/或双镶嵌工艺可以用于形成再分布结构140A/140B/140C。再分布结构140A/140B/140C接合至半导体封装件200的相应区域(例如，区域310、320或330)中的导电部件(例如，导电柱119、管芯连接件128)，与图4和图5A中示出的工艺类似。在再分布结构140A/140B/140C和相应的导电部件之间形成焊料区域148。由于焊料区域148和导电焊盘147，在再分布结构140A/140B/140C和模制材料130之间存在间隙。换句话说，再分布结构(例如，140A)的第二侧140L与模制材料130的面向再分布结构(例如，140A)的表面间隔开。图11A还示出了接合至(例如，通过焊料区域)管芯连接件128并且设置在再分布结构140A和140B之间的电子器件171。
在接合至半导体封装件100之后，使附接至再分布结构140A/140B/140C的载体脱粘。使用与图6中示出的相同或类似的工艺形成钝化层153、UBM结构151和外部连接件155。
接下来，如图12中示出的，使用图7至图9中示出的相同或类似的工艺，通过导电接头168将半导体封装件160附接至再分布结构110。虽然未示出，但是可以在形成导电接头168之后实施切割工艺以将半导体封装件200与在相同工艺步骤中形成的其它相邻半导体封装件(未示出)分离，从而形成多个单独的半导体封装件200。
图13示出了半导体封装件200A的截面图，该半导体封装件200A与图12的半导体封装件200类似，并且可以使用与图1至图9中示出的类似的工艺形成，但是在再分布结构(例如，140A、140B、140C)和导电柱119/管芯连接件128之间没有焊料区域148(见图12)，在一些实施例中。除非另有说明，否则图13中的相同的标号表示图12中的相同部分。例如，具有相同标号的组件可以由相同或类似的材料形成，并且可以使用相同或类似的形成方法形成。为了简单起见，不再重复细节。
参照图13，为了将再分布结构140A/140B接合至导电柱119/管芯连接件128，实施直接接合工艺，使得导电焊盘147(例如，铜焊盘)直接接合至导电柱119(例如，铜柱)并且直接接合至管芯连接件128(例如，铜管芯连接件)。因此，在导电焊盘147和导电柱119/管芯连接件128之间没有焊料区域。在一些实施例中，电子器件171可以通过焊料区域接合至相应的管芯连接件128，并且在其它实施例中，电子器件171可以直接接合至(例如，使用直接接合工艺)管芯连接件128而其间没有焊料区域。由于导电焊盘147，在再分布结构140A/140B和模制材料130之间存在间隙。换句话说，再分布结构(例如，140A)的第二侧140L与模制材料130的面向再分布结构(例如，140A)的表面间隔开。
所公开的实施例的变型是可能的，并且均完全旨在包括在本发明的范围内。例如，在各个实施例中使用一个半导体管芯120作为非限制性实例，然而，在不背离本发明的精神的情况下，可以将两个或多个半导体管芯附接至再分布结构110。又例如，将三个预制再分布结构140A/140B/140C附接至图11B中的半导体封装件200，可以将多于或少于三个预制再分布结构附接至半导体封装件。又例如，虽然未示出，但是可以在再分布结构(例如，140、140A、140B)和模制材料130之间的间隙中形成底部填充材料。在一些实施例中，底部填充材料可以完全填充间隙，并且在其它实施例中，底部填充材料可以形成在导电焊盘147周围和焊料区域148(如果形成的话)周围，并且留下间隙的其它区域未被填充(例如，空的)。
实施例可以实现优势。例如，当前公开的方法允许再分布结构(例如，140、140A、140B)在附接之前预形成。这减少了工艺时间并且增加了生产量。由于再分布结构可以预形成在载体上方而不是模制材料上方，因此避免了模制材料的热限制，并且可以使用镶嵌和/或双镶嵌工艺来形成再分布结构，这产生了更精细线间距和更小的通孔尺寸，从而允许高集成密度和增加的电连接可靠性。此外，本发明公开的方法允许在附接预制再分布结构之前对管芯进行功能测试，因此通过跳过未通过功能测试的管芯(例如，不将预制再分布结构附接至未通过功能测试的管芯)来改进集成良率。
图14示出了根据一些实施例的制造半导体器件的方法的流程图。应该理解，图14所示的实施例方法仅仅是许多可能的实施例方法的示例。本领域普通技术人员将意识到许多变化、替换和修改。例如，可以添加、去除、替换、重新布置和重复图14中示出的各个步骤。
参照图14，在步骤1010中，由模制材料包围管芯和接近管芯的导电柱，其中，管芯和导电柱设置在第一再分布结构的第一侧上方，其中，第一再分布结构的与第一侧相对的第二侧附接至第一载体。在步骤1020中，将设置在预制第二再分布结构的第一表面上的导电焊盘接合至管芯和导电柱，其中，预制第二再分布结构的与第一表面相对的第二表面附接至第二载体。在步骤1030中，在接合导电焊盘之后，去除第二载体以暴露预制第二再分布结构的接近第二表面的导电部件。在步骤1040中，在预制第二再分布结构的导电部件上方形成电连接至预制第二再分布结构的导电部件的导电凸块。
在实施例中，方法包括在第一载体上方形成第一再分布结构；在第一再分布结构上方形成导电柱；将第一管芯的第一侧附接至邻近导电柱的第一再分布结构，第一管芯的第二侧远离第一再分结构，第一管芯的第二侧上设置有管芯连接件；在第一再分布结构上方形成模制材料，模制材料包围第一管芯和导电柱；将第二再分布结构的第一侧接合至管芯连接件和导电柱，将与第二再分布结构的第一侧相对的第二再分布结构的第二侧附接至第二载体；在接合第二再分布结构的第一侧之后去除第二载体以暴露第二再分布结构的第二侧上的导电部件；以及在去除第二载体之后，在第二再分布结构的第二侧上的导电部件上形成导电凸块。在实施例中，在接合之前预制第二再分布结构。在实施例中，在接合之后，模制材料的远离第一再分布结构的顶面与第二再分布结构的最靠近模制材料的介电层间隔开。在实施例中，接合包括将第二再分布结构的第一侧上的导电焊盘接合至管芯连接件和导电柱。在实施例中，导电焊盘通过焊料接头接合至管芯连接件和导电柱。在实施例中，使用直接接合工艺将导电焊盘接合至管芯连接件和导电柱，其中，导电焊盘在接合之后物理接触管芯连接件和导电柱。在实施例中，形成导电凸块包括在去除第二载体之后，在第二再分布结构的第二侧上方形成钝化层；在钝化层中形成凸块下金属(UBM)结构，UBM结构电连接至第二再分布结构的第二侧上的导电部件；以及在UBM结构上方形成导电凸块。在实施例中，该方法还包括去除第一载体以暴露第一再分布结构的第一侧；在第一再分布结构的第一侧中形成开口，开口暴露第一再分布结构的导电部件；以及将半导体器件的外部连接件接合至第一再分布结构的暴露的导电部件。在实施例中，在平面图中，第二再分布结构的第一面积小于模制材料的第二面积，其中，该方法还包括将第三再分布结构的第一侧接合至管芯连接件和导电柱，与第三再分布结构的第一侧相对的第三再分布结构的第二侧附接至第三载体；在接合第三再分布结构的第一侧之后去除第三载体，以暴露第三再分布结构的第二侧上的导电部件。在实施例中，在平面图中，第三再分布结构的第三面积小于模制材料的第二面积，其中，第一面积和第三面积的总和小于第二面积。在实施例中，该方法还包括将电子器件接合至第一管芯的管芯连接件，其中，电子器件位于第二再分布结构和第三再分布结构之间。
在实施例中，方法包括用模制材料包围管芯和接近管芯的导电柱，其中，管芯和导电柱设置在第一再分布结构的第一侧上方，其中，第一再分布结构的与第一侧相对的第二侧附接至第一载体；将设置在预制第二再分布结构的第一表面上的导电焊盘接合至管芯和导电柱，其中，预制第二再分布结构的与第一表面相对的第二表面附接至第二载体；在接合导电焊盘之后，去除第二载体以暴露预制第二再分布结构的接近第二表面的导电部件；并且在预制第二再分布结构的导电部件上方形成电连接至预制第二再分布结构的导电部件的导电凸块。在实施例中，第一再分布结构的第一宽度等于模制材料的第二宽度，并且其中，预制第二再分布结构的第三宽度小于第一宽度。在实施例中，该方法还包括：在接合导电焊盘之后并且在形成导电凸块之前：在预制第二再分布结构上方形成钝化层；以及形成延伸至钝化层内并且电连接至预制第二再分布结构的导电部件的金属部件。在实施例中，在接合之后，预制第二再分布结构的面向管芯的最下表面与模制材料的面向预制第二再分布结构的上表面物理分隔开。在实施例中，该方法还包括去除第一载体；在第一再分布结构中形成开口以暴露第一再分布结构的导电部件；以及将半导体器件接合至第一再分布结构的导电部件。
在实施例中，半导体封装件包括嵌入在模制材料内的管芯和导电柱；位于管芯的第一侧上并且电连接至导电柱的第一再分布结构；以及位于管芯的与第一侧相对的第二侧上的第二再分布结构，其中，管芯在管芯的第二侧上具有管芯连接件，其中，第二再分布结构电连接至管芯连接件和导电柱，并且其中，第二再分布结构的第二宽度与第一再分布结构的第一宽度不同。在实施例中，半导体封装件还包括位于管芯连接件和第二再分布结构之间的焊料区域。在实施例中，第一再分布结构与模制材料共末端，其中，第二再分布结构的宽度小于模制材料的宽度。在实施例中，第二再分布结构的最靠近管芯的介电层与模制材料间隔开。
上面概述了若干实施例的特征，使得本领域人员可以更好地理解本发明的方面。本领域人员应该理解，它们可以容易地使用本发明作为基础来设计或修改用于实施与本文所介绍实施例相同的目的和/或实现相同优势的其它工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中它们可以做出多种变化、替换以及改变。

Claims (10)

1.一种形成半导体封装件的方法，包括：
在第一载体上方形成第一再分布结构；
在所述第一再分布结构上方形成导电柱；
将第一管芯的第一侧附接至邻近所述导电柱的所述第一再分布结构，所述第一管芯的第二侧远离所述第一再分结构，所述第一管芯的第二侧上设置有管芯连接件；
在所述第一再分布结构上方形成模制材料，所述模制材料包围所述第一管芯和所述导电柱；
将第二再分布结构的第一侧接合至所述管芯连接件和所述导电柱，将与所述第二再分布结构的第一侧相对的所述第二再分布结构的第二侧附接至第二载体；
在接合所述第二再分布结构的第一侧之后去除所述第二载体以暴露所述第二再分布结构的第二侧上的导电部件；以及
在去除所述第二载体之后，在所述第二再分布结构的第二侧上的所述导电部件上形成导电凸块。
2.根据权利要求1所述的方法，其中，在所述接合之前预制所述第二再分布结构。
3.根据权利要求1所述的方法，其中，在所述接合之后，所述模制材料的远离所述第一再分布结构的顶面与所述第二再分布结构的最靠近所述模制材料的介电层间隔开。
4.根据权利要求1所述的方法，其中，所述接合包括将所述第二再分布结构的第一侧上的导电焊盘接合至所述管芯连接件和所述导电柱。
5.根据权利要求4所述的方法，其中，所述导电焊盘通过焊料接头接合至所述管芯连接件和所述导电柱。
6.根据权利要求4所述的方法，其中，使用直接接合工艺将所述导电焊盘接合至所述管芯连接件和所述导电柱，其中，所述导电焊盘在所述接合之后物理接触所述管芯连接件和所述导电柱。
7.根据权利要求1所述的方法，其中，形成所述导电凸块包括：
在去除所述第二载体之后，在所述第二再分布结构的第二侧上方形成钝化层；
在所述钝化层中形成凸块下金属(UBM)结构，所述凸块下金属结构电连接至所述第二再分布结构的第二侧上的所述导电部件；以及
在所述凸块下金属结构上方形成所述导电凸块。
8.根据权利要求1所述的方法，还包括：
去除所述第一载体以暴露所述第一再分布结构的第一侧；
在所述第一再分布结构的第一侧中形成开口，所述开口暴露所述第一再分布结构的导电部件；以及
将半导体器件的外部连接件接合至所述第一再分布结构的暴露的导电部件。
9.一种形成半导体封装件的方法，包括：
用模制材料包围管芯和接近所述管芯的导电柱，其中，所述管芯和所述导电柱设置在第一再分布结构的第一侧上方，其中，所述第一再分布结构的与第一侧相对的第二侧附接至第一载体；
将设置在预制第二再分布结构的第一表面上的导电焊盘接合至所述管芯和所述导电柱，其中，所述预制第二再分布结构的与所述第一表面相对的第二表面附接至第二载体；
在接合所述导电焊盘之后，去除所述第二载体以暴露所述预制第二再分布结构的接近所述第二表面的导电部件；以及
在所述预制第二再分布结构的导电部件上方形成导电凸块，所述导电凸块电连接至所述预制第二再分布结构的导电部件。
10.一种半导体封装件，包括：
管芯和导电柱，嵌入在模制材料内；
第一再分布结构，位于所述管芯的第一侧上并且电连接至所述导电柱；以及
第二再分布结构，位于所述管芯的与所述第一侧相对的第二侧上，其中，所述管芯在所述管芯的第二侧上具有管芯连接件，其中，所述第二再分布结构电连接至所述管芯连接件和所述导电柱，并且其中，所述第二再分布结构的第二宽度与所述第一再分布结构的第一宽度不同。
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