CN109786266A - 半导体封装件及其形成方法 - Google Patents

半导体封装件及其形成方法 Download PDF

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Publication number
CN109786266A
CN109786266A CN201810460994.3A CN201810460994A CN109786266A CN 109786266 A CN109786266 A CN 109786266A CN 201810460994 A CN201810460994 A CN 201810460994A CN 109786266 A CN109786266 A CN 109786266A
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China
Prior art keywords
tube core
integrated circuit
circuit die
connector
wiring
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CN201810460994.3A
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CN109786266B (zh
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陈洁
陈英儒
陈宪伟
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

在实施例中，封装件包括第一封装结构，该第一封装结构包括：具有有源侧和背侧的第一集成电路管芯，有源侧包括管芯连接件；邻近第一集成电路管芯的第二集成电路管芯，第二集成电路管芯具有有源侧和背侧，有源侧包括管芯连接件；布线管芯，布线管芯包括接合至第一集成电路管芯和第二集成电路管芯的有源侧的管芯连接件，布线管芯将第一集成电路管芯电连接至第二集成电路管芯；密封第一集成电路管芯、第二集成电路管芯和布线管芯的密封剂；以及位于第一集成电路管芯和第二集成电路管芯的管芯连接件上并且电连接至第一集成电路管芯和第二集成电路管芯的管芯连接件的第一再分布结构。本发明的实施例还涉及半导体封装件及其形成方法。

Description

半导体封装件及其形成方法
技术领域
本发明的实施例涉及半导体封装件及其形成方法。
背景技术
由于各个电组件(例如，晶体管、二极管、电阻器、电容器等)的集成密度的持续改进，半导体工业已经经历了快速增长。对于大部分而言，这种集成密度的改进来自于最小部件尺寸的连续减小，这允许更多的组件集成到给定的区域。随着对电子器件缩小的需求不断增长，对半导体管芯的更小且更具创造性的封装技术的需求也已经出现。这种封装系统的实例是堆叠式封装(PoP)技术。在PoP器件中，顶部半导体封装件堆叠在底部半导体封装件的顶部以提供高集成度和组件密度。PoP技术一般能够在印刷电路板(PCB)上产生具有增强的功能和较小的覆盖区的半导体器件。
发明内容
本发明的实施例提供了一种封装件，包括：第一封装结构，包括：第一集成电路管芯，具有有源侧和背侧，所述有源侧包括管芯连接件；第二集成电路管芯，邻近所述第一集成电路管芯，所述第二集成电路管芯具有有源侧和背侧，所述有源侧包括管芯连接件；布线管芯，接合至所述第一集成电路管芯和所述第二集成电路管芯，所述布线管芯具有前侧和背侧，所述布线管芯的前侧包括管芯连接件，所述布线管芯的所述管芯连接件接合至所述第一集成电路管芯和所述第二集成电路管芯的有源侧，所述布线管芯将所述第一集成电路管芯电连接至所述第二集成电路管芯；密封剂，密封所述第一集成电路管芯、所述第二集成电路管芯和所述布线管芯；以及第一再分布结构，位于所述第一集成电路管芯和所述第二集成电路管芯的管芯连接件上并且电连接至所述第一集成电路管芯和所述第二集成电路管芯的管芯连接件，所述布线管芯位于所述第一再分布结构与所述第一集成电路管芯和所述第二集成电路管芯之间。
本发明的另一实施例提供了一种形成半导体封装件的方法，包括：形成第一封装件，包括：在载体衬底上方形成电连接件；使用粘合层将第一管芯的背侧附接至所述载体衬底，所述第一管芯邻近所述电连接件；使用粘合层将第二管芯的背侧附接至所述载体衬底，所述第二管芯邻近所述第一管芯；使用布线管芯上的管芯连接件将所述布线管芯接合至所述第一管芯和所述第二管芯的有源侧，所述布线管芯电连接所述第一管芯和所述第二管芯；用模塑料密封所述第一管芯、所述第二管芯、所述布线管芯和所述电连接件；在所述第一管芯、所述第二管芯、所述布线管芯、所述模塑料和所述电连接件上方形成第一再分布结构；和去除所述载体衬底；以及使用第一组导电连接件将第二封装件接合至所述第一封装件，所述第二封装件靠近所述第一管芯和所述第二管芯的背侧。
本发明的又一实施例提供了一种形成半导体封装件的方法，包括：形成第一封装件，包括：在载体衬底上方形成电连接件；将第一管芯粘合至所述载体衬底，所述第一管芯的有源侧包括第一组管芯连接件和第二组管芯连接件，所述有源侧与背侧相对，所述第一管芯邻近所述电连接件；将第二管芯粘合至所述载体衬底，所述第二管芯的有源侧包括第三组管芯连接件和第四组管芯连接件，所述有源侧与背侧相对，所述第二管芯邻近所述第一管芯；使用所述第一组管芯连接件和所述第三组管芯连接件将布线管芯接合至所述第一管芯和所述第二管芯；用模塑料密封所述第一管芯、所述第二管芯、所述布线管芯和所述电连接件；在所述第一管芯的有源侧、所述模塑料和所述电连接件上面形成再分布结构，所述再分布结构电连接至所述第二组管芯连接件和所述第四组管芯连接件和所述电连接件；和去除所述载体衬底；以及使用所述第一组导电连接件将所述第二封装件接合至所述第一封装件，所述第二封装件靠近所述布线管芯的背侧。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各个方面。应该指出，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1至图15示出了根据一些实施例的在用于形成封装结构的工艺期间的中间步骤的截面图和平面图。
图16至图19示出了根据一些实施例的在用于形成封装结构的工艺期间的中间步骤的截面图。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实施例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为便于描述，在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等空间相对术语，以描述如图所示的一个元件或部件与另一个(或另一些)原件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其它方式定向(旋转90度或在其它方位上)，而本文使用的空间相对描述符可以同样地作出相应的解释。
本文讨论的实施例可以在特定的上下文中讨论，即，封装结构(例如，堆叠式封装(PoP)结构)，封装结构包括连接封装结构中的一个或多个管芯的布线管芯。在一些实施例中，布线管芯是精细间距布线管芯，从而使得布线的间距(例如，线宽和间隔)小于典型的再分布结构的间距。布线管芯可以是集成无源器件(IPD)、表面安装器件(SMD)、没有有源和无源器件的布线管芯、集成电路管芯等。布线管芯可以与一个或多个管芯面对面接合。此外，布线管芯可以与一个或多个管芯密封在相同的密封剂中。在一些实施例中，用于封装件(包括一个或多个管芯和布线管芯)的前侧再分布结构可以位于布线管芯上面，从而使得布线管芯位于一个或多个管芯和前侧再分布结构之间。本发明的实施例可以包括布线管芯，其具有比典型的再分布结构的布线密度大五倍的布线密度。
此外，本发明的教导适用于包括一个或多个半导体管芯的任何封装结构。其它实施例预期其它应用，诸如不同的封装类型或不同的配置对阅读本发明的本领域普通技术人员而言将是显而易见的。应该注意，本文讨论的实施例可以不必示出可能存在于结构中的每个组件或部件。例如，诸如当一个组件的讨论可能足以表达实施例的各个方面时，可以从附图中省略多个组件。此外，本文讨论的方法实施例可以以特定顺序实施；然而，可以以任何逻辑顺序实施其它方法实施例。
图1至图15示出了根据一些实施例的在用于形成第一封装结构的工艺期间的中间步骤的截面图和平面图。图1示出了载体衬底100以及形成在载体衬底100上的释放层102。示出了分别用于形成第一封装件和第二封装件的第一封装区域600和第二封装区域602。
载体衬底100可以是玻璃载体衬底、陶瓷载体衬底等。载体衬底100可以是晶圆，从而使得可以同时在载体衬底100上形成多个封装件。释放层102可以由基于聚合物的材料形成，其可以与载体衬底100一起从在随后的步骤中形成的上面的结构去除。在一些实施例中，释放层102是诸如光热转换(LTHC)释放涂层的基于环氧树脂的热释放材料，该材料在加热时失去其粘合性。在其它实施例中，释放层102可以是紫外(UV)胶，当暴露于UV光时失去其粘合性。释放层102可以以液体形式分配并且被固化，可以是层压在载体衬底100上的层压膜，或者可以是类似的。释放层102的顶面可以是齐平的并且可以具有高度的共面性。
在图2中，形成介电层104和金属化图案106(有时称为再分布层或再分布线)。介电层104形成在释放层102上。介电层104的底面可以与释放层102的顶面接触。在一些实施例中，介电层104由诸如聚苯并恶唑(PBO)、聚酰亚胺、苯并环丁烯(BCB)等的聚合物形成。在其它实施例中，介电层104由氮化物，诸如氮化硅；氧化物，诸如氧化硅、磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、硼掺杂的磷硅酸盐玻璃(BPSG)等；等形成。可以通过诸如旋涂、化学汽相沉积(CVD)、层压等或它们的组合的任何可接受的沉积工艺形成介电层104。
在介电层104上形成金属化图案106。作为形成金属化图案106的实例，在介电层104上方形成晶种层(未示出)。在一些实施例中，晶种层是金属层，其可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层包括钛层和位于钛层上方的铜层。可以使用例如PVD等形成晶种层。之后，在晶种层上形成光刻胶并且图案化光刻胶。光刻胶可以通过旋涂等形成，并且可以暴露于光以用于图案化。光刻胶的图案对应于金属化图案106。图案化形成穿过光刻胶的开口以暴露晶种层。在光刻胶的开口中和晶种层的暴露部分上形成导电材料。可以通过诸如电镀或化学镀等的镀形成导电材料。导电材料可以包括如铜、钛、钨、铝等的金属。之后，去除光刻胶和晶种层的其上未形成导电材料的部分。可以通过可接受的灰化或剥离工艺(诸如使用氧等离子体等)去除光刻胶。一旦去除光刻胶，则诸如通过使用可接受的蚀刻工艺(诸如湿或干蚀刻)去除晶种层的暴露部分。晶种层的剩余部分和导电材料形成金属化图案106。
在图3中，在金属化图案106和介电层104上形成介电层108。在一些实施例中，介电层108由聚合物形成，聚合物可以是可以使用光刻掩模图案化的诸如PBO、聚酰亚胺、BCB等的光敏材料。在其它实施例中，介电层108由氮化物，诸如氮化硅；氧化物，诸如氧化硅、PSG、BSG、BPSG；等形成。可以通过旋涂、层压、CVD等或它们的组合形成介电层108。之后，图案化介电层108以形成暴露金属化图案106的部分的开口。可以通过可接受的工艺进行图案化，诸如当介电层是光敏材料时通过将介电层108暴露于光或通过例如使用各向异性蚀刻的蚀刻。
介电层104和108以及金属化图案106可以称为背侧再分布结构110。在所示的实施例中，背侧再分布结构110包括两个介电层104和108以及一个金属化图案106。在其它实施例中，背侧再分布结构110可以包括任何数量的介电层、金属化图案和导电通孔。通过重复用于形成金属化图案106和介电层108的工艺，可以在背侧再分布结构110中形成一个或多个额外的金属化图案和介电层。可以在通过在下面的介电层的开口中形成金属化图案的晶种层和导电材料的金属化图案的形成期间形成导电通孔(未示出)。因此，导电通孔可以互连并且电连接各个金属化图案。
在图4中，形成电连接件112。电连接件112将延伸穿过随后形成的密封剂130(见图9)并且在下文中可称为通孔112。作为形成通孔112的实例，在背侧再分布结构110上方(例如，在如图所示的介电层108和金属化图案106的暴露部分上方)形成晶种层。在一些实施例中，晶种层是金属层，其可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层包括钛层和位于钛层上方的铜层。可以使用例如PVD等形成晶种层。在晶种层上形成光刻胶并且图案化光刻胶。光刻胶可以通过旋涂等形成，并且可以暴露于光以用于图案化。光刻胶的图案对应于通孔。图案化形成穿过光刻胶的开口以暴露晶种层。在光刻胶的开口中和晶种层的暴露部分上形成导电材料。可以通过诸如电镀或化学镀等的镀形成导电材料。导电材料可以包括如铜、钛、钨、铝等的金属。去除光刻胶和晶种层的其上未形成导电材料的部分。可以通过可接受的灰化或剥离工艺(诸如使用氧等离子体等)去除光刻胶。一旦去除光刻胶，则诸如通过使用可接受的蚀刻工艺(诸如湿或干蚀刻)去除晶种层的暴露部分。晶种层的剩余部分和导电材料形成通孔112。
在图5中，通过粘合剂116将集成电路管芯114粘合至释放层102。虽然两个集成电路管芯114示出为粘合在第一封装区域600和第二封装区域602的每个中，但是应该理解，可以在每个封装区域中粘合更多或更少的集成电路管芯114。例如，可以在每个区域中仅粘合一个集成电路管芯114。集成电路管芯114可以是逻辑管芯(例如，中央处理单元、微控制器等)、存储器管芯(例如，动态随机存取存储器(DRAM)管芯、静态随机存取存储器(SRAM)管芯等)、电源管理管芯(例如，电源管理集成电路(PMIC)管芯)、射频(RF)管芯、传感器管芯、微电子机械系统(MEMS)管芯、信号处理管芯(例如，数字信号处理(DSP)管芯)、前端管芯(例如，模拟前端(AFE)管芯)等或它们的组合。而且，在一些实施例中，集成电路管芯114可以具有不同的尺寸(例如，不同的高度和/或表面积)，并且在其它实施例中，集成电路管芯114可以具有相同的尺寸(例如，相同的高度和/或表面积)。
在粘合至释放层102之前，可以根据可应用的制造工艺处理集成电路管芯114以在集成电路管芯114中形成集成电路。例如，集成电路管芯114每个均包括半导体衬底118，半导体衬底118诸如掺杂或未掺杂的硅或绝缘体上半导体(SOI)衬底的有源层。半导体衬底可以包括其它半导体材料，诸如锗；化合物半导体，包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟；合金半导体，包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP；或它们的组合。也可以使用诸如多层衬底或梯度衬底的其它衬底。诸如晶体管、二极管、电容器、电阻器等的器件可以形成在半导体衬底118中和/或上，并且可以通过互连结构120互连以形成集成电路，互连结构120由半导体衬底118上的一个或多个介电层中的金属化图案形成。在一些实施例中，使用镶嵌和/或双镶嵌工艺形成互连结构120。
集成电路管芯114还包括制成外部连接的焊盘122，诸如铜焊盘或铝焊盘。焊盘122位于可以称为集成电路管芯114的相应的有源侧的位置上。钝化膜124位于集成电路管芯114上并且可以位于焊盘122的部分上。开口穿过钝化膜124至焊盘122。诸如导电柱(例如，包括诸如铜的金属)的管芯连接件126位于穿过钝化膜124的开口中并且机械地和电连接至相应的焊盘122。可以通过例如镀等形成管芯连接件126。管芯连接件126电连接集成电路管芯114的相应集成电路。
如图5所示，集成电路管芯114可以具有不同配置的管芯连接件126(例如，管芯连接件126A和126B)。在一些实施例中，集成电路管芯114包括低管芯连接件126B和高管芯连接件126A。低管芯连接件126B允许为随后附接的布线管芯(例如，见图7A)提供空间，同时也将封装结构的厚度保持最小。高管芯连接件126A允许利用集成电路管芯114和前侧再分布结构131之间的布线管芯将集成电路管芯114电连接至随后形成的前侧再分布结构131(例如，见图10)。在一些实施例中，这些低和高管芯连接件可以通过与经历额外的工艺(例如，蚀刻工艺)的低管芯连接件126B类似的工艺来形成，以使它们更低。在一些实施例中，高管芯连接件126A与低管芯连接件126B在单独的形成工艺中形成。例如，可以使用第一形成工艺(例如，第一镀工艺)形成高管芯连接件126A，并且之后，可以用掩模覆盖高管芯连接件126A同时使用第二形成工艺(例如，第二镀工艺)形成低管芯连接件126B。
粘合剂116位于集成电路管芯114的背侧上并且将集成电路管芯114粘合至释放层102。粘合剂116可以是任何合适的粘合剂、环氧树脂、管芯附着膜(DAF)等。在一些实施例中，粘合剂具有在从约5μm至约30μm范围内的厚度，其中，厚度在垂直于相应的集成电路管芯114的背侧的方向上测量。粘合剂116可以施加至集成电路管芯114的背侧(诸如相应的半导体晶圆的背侧)或可以施加在载体衬底100的表面上方。集成电路管芯114可以诸如通过锯切或切割被分割并且使用例如拾取和放置工具通过粘合剂116粘合至释放层102。
在图6中，示出了布线管芯160。布线管芯160可以是集成无源器件(IPD)、表面安装器件(SMD)、没有有源和无源器件的布线管芯、集成电路管芯等。布线管芯160可以使用与以上对集成电路管芯114描述的类似工艺来处理。例如，布线管芯160每个均包括衬底162、互连结构163和布线焊盘164。衬底162可以由半导体材料形成，半导体材料诸如掺杂或未掺杂的硅或绝缘体上半导体(SOI)衬底的有源层。衬底可以包括其它半导体材料，诸如锗；化合物半导体，包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟；合金半导体，包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP；或它们的组合。也可以使用诸如多层衬底或梯度衬底的其它衬底。
互连结构163由例如衬底162上的一个或多个介电层中的金属化图案161形成。在一些实施例中，使用镶嵌和/或双镶嵌工艺形成互连结构163。在一些实施例中，互连结构163的金属化图案161是精细间距金属化图案，从而使得金属化图案的间距(例如，线宽和间隔)小于典型的再分布结构的间距。在一些实施例中，精细间距金属化图案的线宽在从0.03μm至约12μm的范围内，诸如约0.4μm，并且精细间距金属化图案的线之间的间隔在从0.03μm至约12μm的范围内，诸如约0.4μm。
在一些实施例中，布线管芯160没有有源和无源器件，并且用于在集成电路管芯114之间路由信号。在一些实施例中，诸如晶体管、二极管、电容器、电阻器等器件可以形成在衬底162中和/或上，并且可以通过互连结构163互连以形成集成电路。
布线管芯160还包括制成外部连接的焊盘164，诸如铜焊盘或铝焊盘。钝化膜166位于布线管芯160上并且可以位于焊盘164的部分上。开口穿过钝化膜166至焊盘164。管芯连接件168(诸如导电柱(例如，包括具有或不具有焊帽层的诸如铜的金属))位于穿过钝化膜166的开口中并且机械和电连接至相应的焊盘164。可以通过例如镀等形成管芯连接件168。管芯连接件168电连接至布线管芯160的相应金属化图案161。
在图7A和图7B中，将布线管芯160接合至集成电路管芯114。在一些实施例中，将布线管芯160的管芯连接件168接合至集成电路管芯114的低管芯连接件126B。在一些其它实施例中，将管芯连接件168接合至金属焊盘122，从而使得低管芯连接件126B不存在于那些金属焊盘122上方。在一些实施例中，布线管芯160将邻近的集成电路管芯114彼此电连接并且允许增加仅包括前侧再分布结构(诸如图10中的前侧再分布结构131)的结构上方的布线密度。
布线管芯160和集成电路管芯114之间的接合可以是焊料接合或直接金属至金属(诸如铜至铜或锡至锡)接合。在实施例中，可以通过回流工艺将布线管芯160接合至集成电路管芯114。在该回流工艺期间，管芯连接件168与管芯连接件126B接触以将布线管芯160物理和电连接至集成电路管芯114。在接合工艺之后，可以在管芯连接件126B和管芯连接件168的界面处形成金属间化合物(IMC)(未示出)。
在将布线管芯160接合至集成电路管芯114之后，布线管芯160与最近邻的高管芯连接件126A分隔开距离D1。在一些实施例中，距离D1大于或等于约2μm，诸如3μm。接合的布线管芯也具有从金属焊盘122至布线管芯160的背侧测量的高度H2。该高度H2小于高管芯连接件126A的高度H1。高管芯连接件126A的高度H1从金属焊盘122至管芯连接件126A的顶面测量。在一些实施例中，高度H1比高度H2大至少约3μm，诸如高度H1比高度H2大4μm。
图7B示出了图7A中的结构的平面图。如图7B所示，可以存在连接至一对集成电路管芯114并且连接在一对集成电路管芯114之间的多个布线管芯160。图7A的截面图可以沿着图7B的线A-A或者线B-B。图7B进一步示出了每个布线管芯160均可以具有不同数量和配置的管芯连接件168，诸如两个、四个、六个、十个、二十个或数百个管芯连接件168。
在图8中，在各种组件上形成密封剂130。密封剂130可以是模塑料、环氧树脂等，并且可以通过压缩模塑、转移模塑等施加。密封剂130可以形成在载体衬底100上方，从而掩埋或覆盖电连接件112、高管芯连接件126A和布线管芯160。密封剂130在布线管芯160和它们所接合的集成电路管芯114之间延伸。在一些实施例中，密封剂围绕布线管芯160的管芯连接件168以及集成电路管芯114的高和低管芯连接件126A/126B。之后，可以固化密封剂130。
在图9中，密封剂130可以经历研磨工艺以暴露电连接件112和高管芯连接件126A。在研磨工艺之后，电连接件112、高管芯连接件126A和密封剂130的顶面齐平。在一些实施例中，例如，如果已经暴露电连接件112和高管芯连接件126A，则可以省略研磨。下文中电连接件112可以称为通孔112。在一些实施例中，在研磨工艺之后，覆盖布线管芯160的背侧。在一些实施例中，在研磨工艺之后，暴露布线管芯160的背侧的至少部分。
在图10中，形成前侧再分布结构131。前侧再分布结构131包括介电层132、136、140和144以及金属化图案134、138和142。
前侧再分布结构131的形成可以通过在密封剂130、通孔112和管芯连接件126A上沉积介电层132开始。在一些实施例中，介电层132由聚合物形成，聚合物可以是可以使用光刻掩模图案化的诸如PBO、聚酰亚胺、BCB等的光敏材料。在其它实施例中，介电层132由氮化物，诸如氮化硅；氧化物，诸如氧化硅、PSG、BSG、BPSG；等形成。可以通过旋涂、层压、CVD等或它们的组合形成介电层132。
下一步，图案化介电层132。图案化形成暴露通孔112和高管芯连接件126A的部分的开口。可以通过可接受的工艺进行图案化，诸如当介电层132是光敏材料时通过将介电层132暴露于光或通过例如使用各向异性蚀刻的蚀刻。如果介电层132是光敏材料，则可以在曝光之后显影介电层132。
下一步，在介电层132上形成具有通孔的金属化图案134。作为形成金属化图案134的实例，在介电层132上方和穿过介电层132的开口中形成晶种层(未示出)。在一些实施例中，晶种层是金属层，其可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层包括钛层和位于钛层上方的铜层。可以使用例如PVD等形成晶种层。之后，在晶种层上形成光刻胶并且图案化光刻胶。光刻胶可以通过旋涂等形成，并且可以暴露于光以用于图案化。光刻胶的图案对应于金属化图案134。图案化形成穿过光刻胶的开口以暴露晶种层。在光刻胶的开口中和晶种层的暴露部分上形成导电材料。可以通过诸如电镀或化学镀等的镀形成导电材料。导电材料可以包括如铜、钛、钨、铝等的金属。之后，去除光刻胶和晶种层的其上未形成导电材料的部分。可以通过可接受的灰化或剥离工艺(诸如使用氧等离子体等)去除光刻胶。一旦去除光刻胶，则诸如通过使用可接受的蚀刻工艺(诸如湿或干蚀刻)去除晶种层的暴露部分。晶种层的剩余部分和导电材料形成金属化图案134和通孔。在穿过介电层132至例如通孔112和/或高管芯连接件126A的开口中形成通孔。
可以对介电层136和140以及金属化图案和通孔138和142重复该工艺，以继续形成再分布结构131。用于形成再分布结构131的这些层的材料和工艺可以与介电层132和金属化图案和通孔134的类似，并且此处不再重复描述。
在形成金属化图案和通孔142之后，在金属化图案142和介电层140上沉积介电层144。在一些实施例中，介电层144由聚合物形成，聚合物可以是可以使用光刻掩模图案化的诸如PBO、聚酰亚胺、BCB等的光敏材料。在其它实施例中，介电层144由氮化物，诸如氮化硅；氧化物，诸如氧化硅、PSG、BSG、BPSG；等形成。可以通过旋涂、层压、CVD等或它们的组合形成介电层144。
在图11中，图案化介电层144。图案化形成暴露金属化图案142的部分的开口。可以通过可接受的工艺进行图案化，诸如当介电层144是光敏材料时通过将介电层144暴露于光或通过例如使用各向异性蚀刻的蚀刻。如果介电层144是光敏材料，则可以在曝光之后显影介电层144。
前侧再分布结构131示出为实例。可以在前侧再分布结构131中形成更多或更少的介电层和金属化图案。如果要形成更少的介电层和金属化图案，则可以省略以上讨论的步骤和工艺。如果要形成更多的介电层和金属化图案，则可以重复以上讨论的步骤和工艺。本领域普通技术人员将容易理解，可以省略或重复哪些步骤和工艺。
在一些实施例中，布线管芯160的布线密度可以比前侧再分布结构131可能的布线密度大五倍。例如，前侧再分布结构131的金属化图案可以具有在从约2μm至约15μm的范围内的线宽，并且前侧再分布结构131的金属化图案的线之间的间隔可以在从约2μm至约15μm的范围内。如上所讨论的，布线管芯160可以具有在从约0.03μm/0.03μm至约12μm/12μm的范围内(诸如约0.4μm/0.4μm)的线宽/间隔。
因此，在布线管芯的线宽和间隔为约0.03μm/0.03μm的实施例中，布线管芯的布线密度可以比前侧再分布结构131的最小布线的密度大约66倍和/或比前侧再分布结构131的最大布线的密度大约500倍。在布线管芯的线宽和间隔为约0.4μm/0.4μm的实施例中，布线管芯的布线密度可以比前侧再分布结构131的最小布线的密度大约5倍和/或比前侧再分布结构131的最大布线的密度大约375倍。在布线管芯的线宽和间隔为约12μm/12μm的实施例中，布线管芯的布线密度可以比前侧再分布结构131的最小布线的密度小约6倍和/或比前侧再分布结构131的最大布线的密度大约1.25倍。
此外，在图11中，在前侧再分布结构131的外侧上形成焊盘150。焊盘150用于连接至导电连接件152(见图12)并且可以称为凸块下金属(UBM)150。在示出的实施例中，通过穿过介电层144至金属化图案142的开口形成焊盘150。作为形成焊盘150的示例，在介电层144上方形成晶种层(未示出)。在一些实施例中，晶种层是金属层，其可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层包括钛层和位于钛层上方的铜层。可以使用例如PVD等形成晶种层。之后，在晶种层上形成光刻胶并且图案化光刻胶。光刻胶可以通过旋涂等形成，并且可以暴露于光以用于图案化。光刻胶的图案对应于焊盘150。图案化形成穿过光刻胶的开口以暴露晶种层。在光刻胶的开口中和晶种层的暴露部分上形成导电材料。可以通过诸如电镀或化学镀等的镀形成导电材料。导电材料可以包括如铜、钛、钨、铝等的金属。之后，去除光刻胶和晶种层的其上未形成导电材料的部分。可以通过可接受的灰化或剥离工艺(诸如使用氧等离子体等)去除光刻胶。一旦去除光刻胶，则诸如通过使用可接受的蚀刻工艺(诸如湿或干蚀刻)去除晶种层的暴露部分。晶种层的剩余部分和导电材料形成焊盘150。在实施例中，在不同地形成焊盘150的情况下，可以利用更多的光刻胶和图案化步骤。
在图12中，在UBM 150上形成导电连接件152。导电连接件152可以是球栅阵列(BGA)连接件、焊球、金属柱、可控塌陷芯片连接(C4)凸块、微凸块、化学镀镍-化学镀钯浸金技术(ENEPIG)形成的凸块等。导电连接件152可以包括诸如焊料、铜、铝、金、镍、银、钯、锡等或它们的组合的导电材料。在一些实施例中，可以通过首先由诸如蒸发、电镀、印刷、焊料转移、球植等常用的方法形成焊料层来形成导电连接件152。一旦已经在结构上形成焊料层，则可以实施回流以将材料成形为期望的凸块形状。在另一实施例中，导电连接件152是通过溅射、印刷、电镀、化学镀、CVD等形成的金属柱(诸如铜柱)。金属柱可以是无焊料的并且具有基本垂直的侧壁。在一些实施例中，在金属柱连接件152的顶部上形成金属帽层(未示出)。金属帽层可以包括镍、锡、锡铅、金、银、钯、铟、镍-钯-金、镍-金等或它们的组合，并且可以通过镀工艺形成。
在图13中，实施载体衬底脱粘以将载体衬底100从背侧再分布结构110(例如，介电层104)分离(脱粘)。从而在第一封装区域600和第二封装区域602的每个中形成第一封装件200。根据一些实施例，脱粘包括将诸如激光或UV光的光投射到释放层102上，使得释放层102在光的热量下分解，并且可以去除载体衬底100。之后，翻转该结构并且放置在带176上。此外，穿过介电层104形成暴露金属化图案106的部分的开口178。可以例如使用激光钻孔、蚀刻等形成开口178。
图14和图15示出了根据一些实施例的在用于形成封装结构500的工艺期间的中间步骤的截面图。封装结构500可以称为堆叠式封装(PoP)结构。
在图14中，将第二封装件300附接至第一封装件200。第二封装件300包括衬底302和连接至衬底302的一个或多个堆叠管芯308(308A和308B)。虽然示出了管芯308(308A和308B)的单个堆叠件，但是在其它实施例中，多个堆叠管芯308(每个均具有一个或多个堆叠管芯)可以并排设置为连接至衬底302的同一表面。衬底302可以由诸如硅、锗、金刚石等的半导体材料制成。在一些实施例中，也可以使用诸如硅锗、碳化硅、砷化镓、砷化铟、磷化铟、碳化硅锗、磷砷化镓、磷化镓铟、这些的组合等的化合物材料。此外，衬底302可以是绝缘体上硅(SOI)衬底。通常，SOI衬底包括诸如外延硅、锗、硅锗、SOI、绝缘体上硅锗(SGOI)或它们的组合的半导体材料层。在一个可选实施例中，衬底302是基于诸如玻璃纤维增强树脂芯的绝缘芯。芯材料的一个实例是诸如FR4的玻璃纤维树脂。芯材料的可选物质包括双马来酰亚胺-三嗪(BT)树脂或者其它印刷电路板(PCB)材料或薄膜。对于衬底302，可以使用诸如味之素积聚膜(ABF)或其它层压材料的积聚膜。
衬底302可以包括有源和无源器件(未示出)。如本领域普通技术人员将意识到，诸如晶体管、电容器、电阻器、这些的组合等的多种器件可以用于生成用于第二封装件300的设计的结构和功能需求。可以使用任何合适的方法形成该器件。
衬底302也可以包括金属化层(未示出)和通孔306。金属化层可以形成在有源和无源器件上方并且被设计为连接各个器件以形成功能电路。金属化层可以由电介质(例如，低k介电材料)和导电材料(例如，铜)(其具有互连导电材料层的通孔)的交替层形成，并且可以通过任何合适的工艺(诸如沉积、镶嵌、双镶嵌等)形成。在一些实施例中，衬底302基本没有有源和无源器件。
衬底302可以具有位于衬底302的第一侧上以连接至堆叠管芯308的接合焊盘303，以及位于衬底302的第二侧上的接合焊盘304，第二侧与衬底302的第一侧相对。在一些实施例中，通过在衬底302的第一侧和第二侧上的介电层(未示出)中形成凹槽(未示出)来形成接合焊盘303和304。凹槽可以形成为允许接合焊盘303和304嵌入至介电层内。在其它实施例中，由于接合焊盘303和304可以形成在介电层上，因此省略了凹槽。在一些实施例中，接合焊盘303和304包括由铜、钛、镍、金、钯等或它们的组合制成的薄晶种层(未示出)。可以在薄晶种层上方沉积接合焊盘303和304的导电材料。可以通过电化学镀工艺、化学镀工艺、CVD、ALD、PVD等或它们的组合来形成导电材料。在实施例中，接合焊盘303和304的导电材料是铜、钨、铝、银、金等或它们的组合。
在实施例中，接合焊盘303和304是UBM，其包括三个导电材料层，诸如钛层、铜层和镍层。然而，本领域普通技术人员将意识到，存在适合于形成接合焊盘303和304的许多合适的材料和层布置，诸如铬/铬-铜合金/铜/金的布置、钛/钛钨/铜的布置或铜/镍/金的布置。可以用于接合焊盘303和304的任何合适的材料或材料层均完全旨在包括在本申请的范围内。在一些实施例中，通孔306延伸穿过衬底302并且将至少一个接合焊盘303连接至至少一个接合焊盘304。
在示出的实施例中，通过引线接合310将堆叠管芯308连接至衬底302，但是也可以使用其它连接，诸如导电凸块。在实施例中，堆叠管芯308是堆叠的存储器管芯。例如，堆叠管芯308可以是诸如低功率(LP)双数据率(DDR)存储器模块(诸如LPDDR1、LPDDR2、LPDDR3、LPDDR4等存储器模块)的存储器管芯。
堆叠管芯308和引线接合310可以由模塑材料312密封。可以例如使用压缩模塑将模塑材料312模塑在堆叠管芯308和引线接合310上。在一些实施例中，模塑材料312是模塑料、聚合物、环氧树脂、氧化硅填充材料等或它们的组合。可以实施固化步骤以固化模塑材料312，其中，固化可以是热固化、UV固化等或它们的组合。
在一些实施例中，将堆叠管芯308和引线接合310埋在模塑材料312中，并且在模塑材料312的固化之后，实施诸如研磨的平坦化步骤以去除模塑材料312的过量部分并且为第二封装件300提供基本平坦的表面。
在形成第二封装件300之后，通过导电连接件314、接合焊盘304和金属化图案106将第二封装件300机械和电接合至第一封装件200。在一些实施例中，可以通过引线接合310、接合焊盘303和304、通孔306、导电连接件314和通孔112将堆叠管芯308连接至集成电路管芯114。
导电连接件314可以与以上描述的导电连接件152类似，并且此处不再重复描述，但是导电连接件314和导电连接件152不需要是相同的。导电连接件314可以在开口178中设置在衬底302的与堆叠管芯308相对的侧上。在一些实施例中，阻焊剂(未单独标记)也可以形成在衬底的与堆叠管芯308相对的侧上。导电连接件314可以设置在阻焊剂中的开口中以电和机械连接至衬底302中的导电部件(例如，接合焊盘304)。阻焊剂可以用于保护衬底302的区免受外部损坏。
在一些实施例中，在接合导电连接件314之前，导电连接件314涂覆有焊剂(未示出)，诸如免洗焊剂。导电连接件314可以浸入焊剂中，或可以将焊剂喷射到导电连接件314上。在另一实施例中，可以将焊剂施加至金属化图案106的表面。
在一些实施例中，导电连接件314可以具有在其上形成的可选环氧树脂焊剂(未示出)，然后回流在将第二封装件300附接至第一封装件200之后剩余的环氧树脂焊剂的至少一些环氧树脂部分。
可以在第一封装件200和第二封装件300之间以及围绕导电连接件314形成底部填充物(未示出)。底部填充物可以减小应力并且保护由导电连接件314的回流产生的接头。底部填充物可以在附接第一封装件200之后通过毛细管流动工艺形成，或可以在附接第一封装件200之前通过合适的沉积方法形成。在形成环氧树脂焊剂的实施例中，环氧树脂焊剂可以用作底部填充物。
第二封装件300和第一封装件200之间的接合可以是焊料接合。在实施例中，通过回流工艺将第二封装件300接合至第一封装件200。在该回流工艺期间，导电连接件314与接合焊盘304和金属化图案106接触，以将第二封装件300物理和电连接至第一封装件200。在接合工艺之后，金属间化合物(IMC，未示出)可以形成在金属化图案106和导电连接件314的界面处并且也形成在导电连接件314和接合焊盘304之间的界面(未示出)处。
通过沿着划线区域(例如，在第一封装区域600和第二封装区域602之间)锯切来实施分割工艺。锯切分割第二封装区域602与第一封装区域600。产生来自第一封装区域600或第二封装区域602的一个的分割的第一封装件200和第二封装件300。在一些实施例中，在第二封装件300附接至第一封装件200之后实施分割工艺。在其它实施例(未示出)中，在将第二封装件300附接至第一封装件200之前，诸如在将载体衬底100脱粘并且形成开口178之后，实施分割工艺。
在图15中，使用导电连接件152将第一封装件200安装至封装衬底400。封装衬底400可以由诸如硅、锗、金刚石等的半导体材料制成。可选地，也可以使用诸如硅锗、碳化硅、砷化镓、砷化铟、磷化铟、碳化硅锗、磷砷化镓、磷化镓铟、这些的组合等的化合物材料。此外，封装衬底400可以是SOI衬底。通常，SOI衬底包括诸如外延硅、锗、硅锗、SOI、SGOI或它们的组合的半导体材料层。在一个可选实施例中，封装衬底400是基于诸如玻璃纤维增强树脂芯的绝缘芯。芯材料的一个实例是诸如FR4的玻璃纤维树脂。芯材料的可选物质包括双马来酰亚胺-三嗪(BT)树脂或者其PCB材料或薄膜。对于封装衬底400可以使用诸如ABF或其它层压材料的积聚膜。
封装衬底400可以包括有源和无源器件(未示出)。如本领域普通技术人员将意识到，诸如晶体管、电容器、电阻器、这些的组合等的多种器件可以用于生成用于封装结构500的设计的结构和功能需求。可以使用任何合适的方法形成该器件。
封装衬底400也可以包括金属化层和通孔(未示出)以及位于金属化层和通孔上方的接合焊盘402。金属化层可以形成在有源和无源器件上方并且被设计为连接各个器件以形成功能电路。金属化层可以由电介质(例如，低k介电材料)和导电材料(例如，铜)(其具有互连导电材料层的通孔)的交替层形成，并且可以通过任何合适的工艺(诸如沉积、镶嵌、双镶嵌等)形成。在一些实施例中，封装衬底400基本没有有源和无源器件。
在一些实施例中，回流导电连接件152以将第一封装件200附接至接合焊盘402。导电连接件152将包括封装衬底400中的金属化层的封装衬底400电和/或物理连接至第一封装件200。在一些实施例中，在安装在封装衬底400上之前，可以将无源器件(例如，未示出的表面安装器件(SMD))附接至第一封装件200(例如，接合至接合焊盘402)。在这种实施例中，无源器件可以与导电连接件152接合至第一封装件200的同一表面。
在一些实施例中，导电连接件152可以具有在其上形成的可选环氧树脂焊剂(未示出)，然后回流在将第一封装件200附接至封装衬底400之后剩余的环氧树脂焊剂的至少一些环氧树脂部分。该剩余的环氧树脂部分可以用作底部填充物以减小应力并且保护由导电连接件152的回流产生的接头。在一些实施例中，底部填充物(未示出)可以形成在第一封装件200和封装衬底400之间并且围绕导电连接件152。底部填充物可以在附接第一封装件200之后通过毛细管流动工艺形成，或可以在附接第一封装件200之前通过合适的沉积方法形成。
图16至图19示出了根据一些实施例的另一封装结构的截面图。图16至19中的实施例与图1至15中示出的实施例类似，除了该实施例包括布线管芯160，布线管芯160具有延伸穿过布线管芯160的衬底162的通孔170之外。此处将不再重复关于该实施例的与先前描述的实施例的那些类似的细节。
在图16中，示出包括通孔170的布线管芯160。此处将不再重复关于该实施例的布线管芯160的与先前描述的布线管芯160的那些类似的细节。
在该实施例中，通孔170从互连结构163的金属化图案161穿过衬底162延伸至衬底162的背侧。通孔170可以在衬底162的背侧暴露，并且暴露部分可以电连接至上面的导电部件(例如，上面的再分布结构内的金属化图案)。
虽然在布线管芯160中示出了两个通孔170，但是应该理解，在每个布线管芯160中可以存在更多或更少的通孔170。
图17示出了与上述图7A和图7B的处理等效的中间阶段，并且此处不再重复描述。在图17中，将布线管芯160接合至集成电路管芯114。在一些实施例中，将布线管芯160的管芯连接件168接合至集成电路管芯114的低管芯连接件126B。在一些其它实施例中，将管芯连接件168接合至金属焊盘122，从而在那些金属焊盘122上方不存在低管芯连接件126B。在一些实施例中，布线管芯160将邻近的集成电路管芯114彼此电连接并且将集成电路管芯114电连接至上面的导电部件并且允许增加仅包括前侧再分布结构(诸如图10中的前侧再分布结构131)的结构上方的布线密度。
与先前的实施例类似，布线管芯160的高度H2最初可以小于高管芯连接件126A的高度H1。在该实施例中，在随后的平坦化工艺(例如，研磨密封剂130)中将消除H1和H2之间的高度差，从而使得布线管芯160的通孔170的顶面与高管芯连接件126A和通孔112的顶面齐平(例如，见图18)。在一些实施例中，布线管芯160的高度H2最初可以与高管芯连接件126A的高度H1大致相同，并且不需要调平来使它们达到相同的高度。
图18示出了对图17的结构的进一步处理。这两个图之间的工艺与以上参照图8至图12示出和描述的工艺类似，其中，图12是与图18等效的中间阶段并且此处不再重复描述。
在图18中，布线管芯160的通孔170物理和电连接至前侧再分布结构131的金属化图案和通孔132。通孔170可以简化前侧再分布结构131中的布线和信号的路由。
图19示出了对图18的结构的进一步处理。这两个图之间的工艺与以上参照图13至图15示出和描述的工艺类似，其中，图14是与图19等效的中间阶段并且此处不再重复描述。
在图19中，包括布线管芯160(具有通孔170)的封装结构200包括在封装结构500中。此处将不再重复关于该实施例的与先前描述的实施例那些类似的细节。
通过在封装结构中包括连接一个或多个管芯的布线管芯，可以增加封装结构的布线密度。在一些实施例中，布线管芯是精细间距布线管芯，使得布线的间距(例如，线宽和间隔)小于典型的再分布结构的间距。布线管芯可以是集成无源器件(IPD)、表面安装器件(SMD)、没有有源和无源器件的布线管芯、集成电路管芯等。布线管芯可以与一个或多个管芯面对面接合。此外，布线管芯可以与一个或多个管芯密封在相同的密封剂中。在一些实施例中，用于封装件(包括一个或多个管芯和布线管芯)的前侧再分布结构可以位于布线管芯上面，从而使得布线管芯位于一个或多个管芯和前侧再分布结构之间。本发明的实施例可以包括布线管芯，其具有比典型的再分布结构的布线密度大66倍的布线密度。此外，包括布线管芯的封装结构可以具有较小的翘曲并且与试图在再分布结构中实现类似的布线密度的另一封装结构相比，节省制造时间。
在实施例中，封装件包括第一封装结构，该第一封装结构包括具有有源侧和背侧的第一集成电路管芯(有源侧包括管芯连接件)、邻近第一集成电路管芯的第二集成电路管芯(第二集成电路管芯具有有源侧和背侧，有源侧包括管芯连接件)、接合至第一集成电路管芯和第二集成电路管芯的布线管芯(布线管芯具有前侧和背侧，布线管芯的前侧包括管芯连接件，布线管芯的管芯连接件接合至第一集成电路管芯和第二集成电路管芯的有源侧，布线管芯将第一集成电路管芯电连接至第二集成电路管芯)、密封第一集成电路管芯、第二集成电路管芯和布线管芯的密封剂以及位于第一集成电路管芯和第二集成电路管芯的管芯连接件上并且电连接至第一集成电路管芯和第二集成电路管芯的管芯连接件的第一再分布结构，布线管芯位于第一再分布结构与第一集成电路管芯和第二集成电路管芯之间。
实施例可以包括一个或多个以下特征。在该封装件中，第一封装结构还包括邻近第一集成电路管芯的第一通孔，第一通孔延伸穿过密封剂。封装件还包括第二封装结构，第二封装结构通过第一组导电连接件接合至第一通孔。在该封装件中，第一封装结构还包括位于第一通孔上方并且电连接至第一通孔的第二再分布结构，第二再分布结构位于第一集成电路管芯和第二封装结构之间。封装件还包括通过第二组导电连接件接合至第一封装结构的第一再分布结构的封装衬底。在该封装件中，密封剂在布线管芯与第一集成电路管芯和第二集成电路管芯之间延伸，密封剂围绕布线管芯的管芯连接件。在该封装件中，密封剂在布线管芯和第一再分布结构之间延伸。在该封装件中，布线管芯包括衬底、位于衬底上的互连结构(互连结构包括一个或多个介电层中的金属化图案)以及电连接至互连结构的金属化图案的管芯连接件。在该封装件中，布线管芯还包括延伸穿过衬底的通孔，该通孔物理和电连接至第一再分布结构。在该封装件中，布线管芯包括有源或无源器件。在该封装件中，布线管芯基本没有有源和无源器件。
在实施例中，方法包括形成第一封装件，形成第一封装件包括：在载体衬底上方形成电连接件，使用粘合层将第一管芯的背侧附接至载体衬底，第一管芯邻近电连接件，使用粘合层将第二管芯的背侧附接至载体衬底，第二管芯邻近第一管芯，使用布线管芯上的管芯连接件将布线管芯接合至第一管芯和第二管芯的有源侧，布线管芯电连接第一管芯和第二管芯，用模塑料密封第一管芯、第二管芯、布线管芯和电连接件，第一管芯、第二管芯、布线管芯、模塑料和电连接件上方形成第一再分布结构，并且去除载体衬底，并且使用第一组导电连接件将第二封装件接合至第一封装件，第二封装件靠近第一管芯和第二管芯的背侧。
实施例可以包括一个或多个以下特征。该方法进一步包括在第一管芯和第二管芯的背侧上方以及电连接件的第一端上方形成第二再分布结构，第二再分布结构电连接至电连接件，第二封装件接合至第二再分布结构。在该方法中，模塑料在布线管芯与第一管芯和第二管芯之间延伸，模塑料围绕布线管芯的管芯连接件。在该方法中，模塑料在布线管芯和第一再分布结构之间延伸。该方法进一步包括平坦化模塑料，使第一管芯和第二管芯的有源侧上的管芯连接件以及电连接件具有水平表面。在该方法中，布线管芯包括衬底、位于衬底上的互连结构(互连结构包括一个或多个介电层中的金属化图案)、延伸穿过衬底的通孔(通孔物理和电连接至第一再分布结构)以及电连接至互连结构的金属化图案的管芯连接件。在该方法中，第一管芯的第二组管芯连接件和第二管芯的第四组管芯连接件邻近布线管芯并且从布线管芯的前侧延伸至布线管芯的背侧。在该方法中，第二和第四组管芯连接件具有第一高度并且其中，布线管芯具有第二高度，第一高度大于第二高度。
在实施例中，方法包括形成第一封装件，形成第一封装件包括：在载体衬底上方形成电连接件，将第一管芯粘合至载体衬底，第一管芯的有源侧包括第一组和第二组管芯连接件，有源侧与背侧相对，第一管芯邻近电连接件，将第二管芯粘合至载体衬底，第二管芯的有源侧包括第三组和第四组管芯连接件，有源侧与背侧相对，第二管芯邻近第一管芯，使用第一和第三组管芯连接件将布线管芯接合至第一和第二管芯，用模塑料密封第一管芯、第二管芯、布线管芯和电连接件，在第一管芯的有源侧、模塑料和电连接件上面形成再分布结构，再分布结构电连接至第二和第四组管芯连接件和电连接件，并且去除载体衬底，并且使用第一组导电连接件将第二封装件接合至第一封装件，第二封装件靠近布线管芯的背侧。
上面概述了若干实施例的特征，使得本领域人员可以更好地理解本发明的方面。本领域人员应该理解，它们可以容易地使用本发明作为基础来设计或修改用于实施与本人所介绍实施例相同的目的和/或实现相同优势的其它工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中它们可以做出多种变化、替换以及改变。

Claims (10)

1.一种封装件，包括：
第一封装结构，包括：
第一集成电路管芯，具有有源侧和背侧，所述有源侧包括管芯连接件；
第二集成电路管芯，邻近所述第一集成电路管芯，所述第二集成电路管芯具有有源侧和背侧，所述有源侧包括管芯连接件；
布线管芯，接合至所述第一集成电路管芯和所述第二集成电路管芯，所述布线管芯具有前侧和背侧，所述布线管芯的前侧包括管芯连接件，所述布线管芯的所述管芯连接件接合至所述第一集成电路管芯和所述第二集成电路管芯的有源侧，所述布线管芯将所述第一集成电路管芯电连接至所述第二集成电路管芯；
密封剂，密封所述第一集成电路管芯、所述第二集成电路管芯和所述布线管芯；以及
第一再分布结构，位于所述第一集成电路管芯和所述第二集成电路管芯的管芯连接件上并且电连接至所述第一集成电路管芯和所述第二集成电路管芯的管芯连接件，所述布线管芯位于所述第一再分布结构与所述第一集成电路管芯和所述第二集成电路管芯之间。
2.根据权利要求1所述的封装件，其中，所述第一封装结构还包括：
第一通孔，邻近所述第一集成电路管芯，所述第一通孔延伸穿过所述密封剂。
3.根据权利要求2所述的封装件，还包括：
第二封装结构，通过第一组导电连接件接合至所述第一通孔。
4.根据权利要求3所述的封装件，其中，所述第一封装结构还包括：
第二再分布结构，位于所述第一通孔上方并且电连接至所述第一通孔，所述第二再分布结构位于所述第一集成电路管芯和所述第二封装结构之间。
5.根据权利要求3所述的封装件，还包括：
封装衬底，通过第二组导电连接件接合至所述第一封装结构的所述第一再分布结构。
6.根据权利要求1所述的封装件，其中，所述密封剂在所述布线管芯与所述第一集成电路管芯和所述第二集成电路管芯之间延伸，所述密封剂围绕所述布线管芯的管芯连接件。
7.根据权利要求1所述的封装件，其中，所述密封剂在所述布线管芯和所述第一再分布结构之间延伸。
8.根据权利要求1所述的封装件，其中，所述布线管芯包括：
衬底；
互连结构，位于所述衬底上，所述互连结构包括一个或多个介电层中的金属化图案；以及
管芯连接件，电连接至所述互连结构的金属化图案。
9.一种形成半导体封装件的方法，包括：
形成第一封装件，包括：
在载体衬底上方形成电连接件；
使用粘合层将第一管芯的背侧附接至所述载体衬底，所述第一管芯邻近所述电连接件；
使用粘合层将第二管芯的背侧附接至所述载体衬底，所述第二管芯邻近所述第一管芯；
使用布线管芯上的管芯连接件将所述布线管芯接合至所述第一管芯和所述第二管芯的有源侧，所述布线管芯电连接所述第一管芯和所述第二管芯；
用模塑料密封所述第一管芯、所述第二管芯、所述布线管芯和所述电连接件；
在所述第一管芯、所述第二管芯、所述布线管芯、所述模塑料和所述电连接件上方形成第一再分布结构；和
去除所述载体衬底；以及
使用第一组导电连接件将第二封装件接合至所述第一封装件，所述第二封装件靠近所述第一管芯和所述第二管芯的背侧。
10.一种形成半导体封装件的方法，包括：
形成第一封装件，包括：
在载体衬底上方形成电连接件；
将第一管芯粘合至所述载体衬底，所述第一管芯的有源侧包括第一组管芯连接件和第二组管芯连接件，所述有源侧与背侧相对，所述第一管芯邻近所述电连接件；
将第二管芯粘合至所述载体衬底，所述第二管芯的有源侧包括第三组管芯连接件和第四组管芯连接件，所述有源侧与背侧相对，所述第二管芯邻近所述第一管芯；
使用所述第一组管芯连接件和所述第三组管芯连接件将布线管芯接合至所述第一管芯和所述第二管芯；
用模塑料密封所述第一管芯、所述第二管芯、所述布线管芯和所述电连接件；
在所述第一管芯的有源侧、所述模塑料和所述电连接件上面形成再分布结构，所述再分布结构电连接至所述第二组管芯连接件和所述第四组管芯连接件和所述电连接件；和
去除所述载体衬底；以及
使用所述第一组导电连接件将所述第二封装件接合至所述第一封装件，所述第二封装件靠近所述布线管芯的背侧。
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