TW201814850A - 封裝結構及其形成方法 - Google Patents

封裝結構及其形成方法 Download PDF

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TW201814850A
TW201814850A TW106113308A TW106113308A TW201814850A TW 201814850 A TW201814850 A TW 201814850A TW 106113308 A TW106113308 A TW 106113308A TW 106113308 A TW106113308 A TW 106113308A TW 201814850 A TW201814850 A TW 201814850A
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Taiwan
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package
packages
die
layer
underfill
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TW106113308A
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TWI685927B (zh
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鄭錫圭
張兢夫
韓至剛
黃信傑
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台灣積體電路製造股份有限公司
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Abstract

一實施例係一種結構，其包含：一第一封裝，其包含一第一晶粒及至少側向囊封該第一晶粒之一模塑料；一第二封裝，其使用一第一組導電連接器接合至該第一封裝，該第二封裝包括一第二晶粒；及一底膠填充，其在該第一封裝與該第二封裝之間且圍繞該第一組導電連接器，該底膠填充具有沿著該第二封裝之一側壁向上延伸之一第一部分，該第一部分具有一第一側壁，該第一側壁具有一彎曲部分及一平坦部分。

Description

封裝結構及其形成方法
本發明實施例係關於一種封裝結構及其形成方法。
歸因於各種電子組件(例如，電晶體、二極體、電阻器、電容器等)之整合密度的持續改良，半導體行業已經歷飛速發展。很大程度上，整合密度之改良源自最小構件大小之反復減小，此容許更多組件整合至一給定區域中。隨著對縮小電子裝置之需要增大，出現對半導體晶粒之更小且更為創造性之封裝技術之需要。此等封裝系統之一實例係封裝疊層(PoP)技術。在一PoP裝置中，一頂部半導體封裝堆疊在一底部半導體封裝之頂部上以提供一高整合度及組件密度。PoP技術一般實現具有增強功能性及一印刷電路板(PCB)上之小覆蓋區之半導體裝置之生產。
根據本發明一實施例，一種結構，其包括：一第一封裝，其包括：一第一晶粒；及一模塑料，其至少側向囊封該第一晶粒；一第二封裝，其使用一第一組導電連接器接合至該第一封裝，該第二封裝包括一第二晶粒；及一底膠填充，其在該第一封裝與該第二封裝之間且圍繞該第一組導電連接器，該底膠填充具有沿著該第二封裝之一側壁向上延伸之一第一部分，該第一部分具有一第一側壁，該第一側壁具有一彎曲部分及一平坦部分。 根據本發明一實施例，一種方法，其包括：形成複數個第一封裝，該複數個第一封裝之各者包括藉由一模塑料圍繞之一第一晶粒及上覆該第一晶粒之一第一側及該模塑料之一重佈結構，該重佈結構包括金屬化圖案；將包括凸塊下金屬化層之一第一組導電連接器耦合至該重佈結構之一第一金屬化圖案；使用一第二組導電連接器將複數個第二封裝接合至該複數個第一封裝，該第二封裝靠近該第一晶粒之一第二側，該第二側與該第一側相對；及在相鄰第二封裝之間且在該等第一封裝與該等第二封裝之間之切割道區中且圍繞該第二組導電連接器施配一底膠填充，該底膠填充沿著該複數個第二封裝之側壁向上延伸，該底膠填充具有該等相鄰第二封裝之間的彎曲、凹頂部表面。 根據本發明一實施例，一種方法，其包括：形成複數個第一封裝，形成該等第一封裝之各者包括：在一載體基板上方形成一電連接器；將一第一晶粒附接至該載體基板，該電連接器從該第一晶粒之一第二側延伸至該第一晶粒之一第一側，該第二側與該第一側相對；使用一模塑料囊封該第一晶粒及該電連接器，該電連接器延伸穿過該模塑料；形成上覆該第一晶粒之該第一側及該模塑料之一重佈結構；將一第一組導電連接器耦合至該重佈結構；鄰近於該第一組導電連接器將一被動組件耦合至該重佈結構；及移除該載體基板；使用一第二組導電連接器將複數個第二封裝接合至該複數個第一封裝，該第二封裝靠近該第一晶粒之該第二側；在該等第一封裝與該等第二封裝之間及圍繞該第二組導電連接器施配底膠填充，該底膠填充沿著該複數個第二封裝之側壁向上延伸，該底膠填充具有相鄰第二封裝之間的凹頂部表面；且使該複數個第一封裝及第二封裝單粒化以形成封裝結構，該單粒化在該等凹頂部表面處切割穿過該底膠填充以形成具有一凹部分及一平坦部分之底膠填充之一側壁。
本申請案主張2016年9月16日申請之題為「Package Structure and Method of Forming the Same」之美國臨時申請案第62/396,055號之權利，該等專利申請案以引用的方式併入本文中。 下列揭露提供用於實施本揭露之不同特徵之許多不同實施例或實例。下文描述組件及配置之特定實例以簡化本揭露。當然，此等僅為實例且並不意欲為限制性的。例如，在以下描述中，在一第二構件上方或上形成一第一構件可包含其中該第一構件及該第二構件經形成而直接接觸之實施例，且亦可包含其中額外構件可形成於該第一構件與該第二構件之間，使得該第一構件及該第二構件可未直接接觸之實施例。另外，本揭露可在各種實例中重複元件符號及/或字母。此重複係用於簡單及清楚之目的，且本身並不指示所論述之各種實施例及/或組態之間的一關係。 此外，為便於描述，諸如「底下」、「下方」、「下」、「上方」、「上」及類似者之空間相對術語可在本文中用來描述如圖中繪示之一個元件或構件與另一(些)元件或構件之關係。除圖中描繪之定向外，空間相對術語亦意欲涵蓋裝置在使用或操作中之不同定向。設備可以其他方式定向(旋轉90度或成其他定向)且可相應地同樣解釋本文中使用之空間相對描述詞。 本文論述之實施例可在一具體內容背景中論述，即，包含一全覆蓋底膠填充程序之一封裝結構，該程序改良封裝之側壁之保護，其改良封裝結構之可靠性及良率。所揭示之全覆蓋底膠填充程序亦增大底膠填充流速且可簡化封裝單粒化程序。底膠填充可按高於其他底膠填充程序之一壓力固化。此壓力增大可加速固化程序期間之底膠填充中之空隙的移動，此可增大封裝處理之處理量。封裝結構可包含一扇出或扇入封裝且可包含一或多個重佈層(RDL)。 此外，本揭露之教示可適用於包含一底膠填充程序之任何封裝結構。其他實施例考慮其他應用，諸如將為一般技術者在閱讀本揭露之後輕易瞭解之不同封裝類型或不同組態。應注意，本文論述之實施例可不必繪示可存在於一結構中之每一組件或構件。例如，複數個組件可自一圖省略，諸如當組件之一者的論述可足以傳達實施例之態樣時。此外，本文論述之方法實施例可被論述為按一特定順序執行；然而，其他方法實施例可按任何邏輯順序執行。 圖1至圖28繪示根據一些實施例之在用於形成一封裝結構之一程序期間之中間步驟之剖面圖。圖1繪示一載體基板100及在載體基板100上形成之一離型層102。繪示分別用於形成一第一封裝及一第二封裝之一第一封裝區600及一第二封裝區602。 載體基板100可係一玻璃載體基板、一陶瓷載體基板或類似物。載體基板100可係一晶圓，使得可在載體基板100上同時形成多個封裝。離型層102可由一基於聚合物的材料形成，其可連同載體基板100一起自將在後續步驟中形成之上覆結構移除。在一些實施例中，離型層102係一基於環氧樹脂的熱離型材料，其在被加熱時損失其黏合性質，諸如一光熱轉換(LTHC)離型塗層。在其他實施例中，離型層102可係一紫外線(UV)膠，其在曝露於UV光時損失其黏合性質。離型層102可作為一液體施配且固化，可係層壓至載體基板100上之一層壓薄膜，或可係類似物。離型層102之頂部表面可經整平且可具有一高度共面性。 在圖2中，形成一介電層104及一金屬化圖案106。如在圖2中繪示，在離型層102上形成一介電層104。介電層104之底部表面可與離型層102之頂部表面接觸。在一些實施例中，介電層104由一聚合物形成，諸如聚苯并㗁唑(PBO)、聚醯亞胺、苯并環丁烯(BCB)或類似物。在其他實施例中，介電層104由氮化物，諸如氮化矽；氧化物，諸如氧化矽、磷矽酸鹽玻璃(PSG)、硼矽酸玻璃(BSG)、摻雜硼之磷矽酸鹽玻璃(BPSG)或類似物；或類似物形成。介電層104可由任何可接受之沉積程序形成，諸如旋塗、化學氣相沉積(CVD)、層壓、類似物或其等之一組合形成。 在介電層104上形成金屬化圖案106。如形成金屬化圖案106之一實例，在介電層104上方形成一晶種層(未展示)。在一些實施例中，晶種層係一金屬層，其可係一單一層或包括由不同材料形成之複數個子層之一複合層。在一些實施例中，晶種層包括一鈦層及鈦層上方之一銅層。晶種層可使用(例如) PVD或類似物形成。接著，在晶種層上形成且圖案化一光阻。光阻可藉由旋塗或類似物形成且可曝露於光以用於圖案化。光阻之圖案對應於金屬化圖案106。圖案化形成穿過光阻之開口以曝露晶種層。在光阻之開口中及晶種層之曝露部分上形成一導電材料。導電材料可藉由鍍覆形成，諸如電鍍或無電式電鍍或類似物。導電材料可包括一金屬，諸如銅、鈦、鎢、鋁或類似物。接著，移除光阻及其上未形成導電材料之晶種層之部分。光阻可藉由一可接受之灰化或剝離程序移除，諸如使用一氧電漿或類似物。一旦移除光阻，即移除晶種層之曝露部分，諸如藉由使用一可接受之蝕刻程序(諸如藉由濕式或乾式蝕刻)。晶種層之剩餘部分及導電材料形成金屬化圖案106。 在圖3中，在金屬化圖案106及介電層104上形成一介電層108。在一些實施例中，介電層108由一聚合物形成，其可係可使用一微影遮罩圖案化之一光敏材料，諸如PBO、聚醯亞胺、BCB或類似物。在其他實施例中，介電層108由氮化物，諸如氮化矽；氧化物，諸如氧化矽、PSG、BSG、BPSG；或類似物形成。介電層108可藉由旋塗、層壓、CVD、類似物或其等之一組合形成。接著，鈍化層108經圖案化以形成開口以曝露金屬化圖案106之部分。圖案化可藉由一可接受程序，諸如藉由當介電層係一光敏材料時將介電層108曝露於光或藉由使用(例如)一各向異性蝕刻蝕刻。 介電層104及108及金屬化圖案106可稱為一背側重佈結構110。如繪示，背側重佈結構110包含兩個介電層104及108及一個金屬化圖案106。在其他實施例中，背側重佈結構110可包含任何數目之介電層、金屬化圖案及通路。可藉由重複用於形成一金屬化圖案106及介電層108之程序而在背側重佈結構110中形成一或多個額外金屬化圖案及介電層。可在一金屬化圖案之形成期間藉由在下方介電層之開口中形成晶種層及金屬化圖案之導電材料形成通路。因此，通路可互連且電耦合各種金屬化圖案。 進一步在圖3中，形成貫穿通路112。如形成貫穿通路112之一實例，在背側重佈結構110上方形成一晶種層，例如，所繪示之介電層108及金屬化圖案106之曝露部分。在一些實施例中，晶種層係一金屬層，其可係一單一層或包括由不同材料形成之複數個子層之一複合層。在一些實施例中，晶種層包括一鈦層及鈦層上方之一銅層。晶種層可使用(例如) PVD或類似物形成。在晶種層上形成且圖案化一光阻。光阻可藉由旋塗或類似物形成且可曝露於光以用於圖案化。光阻之圖案對應於貫穿通路。圖案化形成穿過光阻之開口以曝露晶種層。在光阻之開口中及晶種層之曝露部分上形成一導電材料。導電材料可藉由鍍覆形成，諸如電鍍或無電式電鍍或類似物。導電材料可包括一金屬，諸如銅、鈦、鎢、鋁或類似物。移除光阻及其上未形成導電材料之晶種層之部分。光阻可藉由一可接受之灰化或剝離程序移除，諸如使用一氧電漿或類似物。一旦移除光阻，即移除晶種層之曝露部分，諸如藉由使用一可接受之蝕刻程序(諸如藉由濕式或乾式蝕刻)。晶種層之剩餘部分及導電材料形成貫穿通路112。 在圖4中，積體電路晶粒114藉由一黏合劑116黏附至介電層108。如在圖4中繪示，兩個積體電路晶粒114經黏附於第一封裝區600及第二封裝區602之各者中，且在其他實施例中，更多或更少之積體電路晶粒114可經黏附於各區中。積體電路晶粒114可係邏輯晶粒(例如，中央處理單元、微控制器等)、記憶體晶粒(例如，動態隨機存取記憶體(DRAM)晶粒、靜態隨機存取記憶體(SRAM)晶粒等)、電力管理晶粒(例如，電力管理積體電路(PMIC)晶粒)、射頻(RF)晶粒、感測器晶粒、微機電系統(MEMS)晶粒、信號處理晶粒(例如，數位信號處理(DSP)晶粒)、前端晶粒(例如，類比前端(AFE)晶粒)、類似物或其等之一組合。同樣地，在一些實施例中，積體電路晶粒114可係不同大小(例如，不同高度及/或表面積)，且在其他實施例中，積體電路晶粒114可係相同大小(例如，相同高度及/或表面積)。 在黏附至介電層108之前，可根據可適用製程處理積體電路晶粒114以在積體電路晶粒114中形成積體電路。例如，積體電路晶粒114各包含一半導體基板118 (諸如摻雜或未摻雜矽)或一絕緣體上半導體(SOI)基板之一主動層。半導體基板可包含其他半導體材料，諸如鍺；一化合物半導體，其包含碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦及/或銻化銦；一合金半導體，其包含SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP；或其等之組合。亦可使用其他基板，諸如多層或梯度基板。裝置(諸如電晶體、二極體、電容器、電阻器等)可在半導體基板118中及/或其上形成且可藉由由(例如)半導體基板118上之一或多個介電層中之金屬化圖案形成之互連結構120互連以形成一積體電路。 積體電路晶粒114進一步包括墊122 (諸如鋁墊)，製作至該等墊122之外部連接。墊122在可被稱為積體電路晶粒114之各自主動側之位置上。鈍化薄膜124在積體電路晶粒114上且在墊122之部分上。開口穿過鈍化薄膜124至墊122。晶粒連接器126 (諸如導電柱(例如，包括一金屬，諸如銅))在穿過鈍化薄膜124之開口中且經機械且電耦合至各自墊122。晶粒連接器126可藉由(例如)鍍覆或類似物形成。晶粒連接器126電耦合積體電路晶粒114之各自積體電路。 一介電材料128在積體電路晶粒114之主動側上，諸如在鈍化薄膜124及晶粒連接器126上。介電材料128側向囊封晶粒連接器126，且介電材料128與各自積體電路晶粒114側向相連。介電材料128可係：一聚合物，諸如PBO、聚醯亞胺、BCB或類似物；氮化物，諸如氮化矽或類似物；氧化物，諸如氧化矽、PSG、BSG、BPSG或類似物；類似物，或其等之一組合，且可(例如)藉由旋塗、層壓、CVD或類似物形成。 黏合劑116在積體電路晶粒114之背側上且將積體電路晶粒114黏附至背側重佈結構110，諸如繪示中之介電層108。黏合劑116可係任何適當黏合劑、環氧樹脂、晶粒附接膜(DAF)或類似物。黏合劑116可經塗覆至積體電路晶粒114之一背側，諸如塗覆至各自半導體晶圓之一背側或可塗覆於載體基板100之表面上方。積體電路晶粒114可諸如藉由鋸切或切割而單粒化且藉由黏合劑116使用(例如)一取置工具黏附至介電層108。 在圖5中，在各種組件上形成一囊封物130。囊封物130可係一模塑料、環氧樹脂或類似物，且可藉由壓縮成型、轉移成型或類似物塗覆。在固化之後，囊封物130可經歷一研磨程序以曝露貫穿通路112及晶粒連接器126。貫穿通路112、晶粒連接器126及囊封物130之頂部表面在研磨程序之後係共面的。在一些實施例中，例如，若貫穿通路112及晶粒連接器126已曝露，則可省略研磨。 在圖6至圖16中，形成一前側重佈結構160。如將在圖16中繪示，前側重佈結構160包含介電層132、140、148及156及金屬化圖案138、146及154。 在圖6中，介電層132經沉積於囊封物130、貫穿通路112及晶粒連接器126上。在一些實施例中，介電層132由一聚合物形成，其可係可使用一微影遮罩圖案化之一光敏材料，諸如PBO、聚醯亞胺、BCB或類似物。在其他實施例中，介電層132由氮化物，諸如氮化矽；氧化物，諸如氧化矽、PSG、BSG、BPSG；或類似物形成。介電層132可藉由旋塗、層壓、CVD、類似物或其等之一組合形成。 在圖7中，接著圖案化介電層132。圖案化形成開口以曝露貫穿通路112及晶粒連接器126之部分。圖案化可藉由一可接受程序，諸如當介電層132係一光敏材料時藉由將介電層132曝露於光或藉由使用(例如)一各向異性蝕刻蝕刻。若介電層132係一光敏材料，則介電層132可在曝露之後顯影。 在圖8中，在介電層132上形成具有通路之金屬化圖案138。如形成金屬化圖案138之一實例，在介電層132上方及穿過介電層132之開口中形成一晶種層(未展示)。在一些實施例中，晶種層係一金屬層，其可係一單一層或包括由不同材料形成之複數個子層之一複合層。在一些實施例中，晶種層包括一鈦層及鈦層上方之一銅層。晶種層可使用(例如) PVD或類似物形成。接著，在晶種層上形成且圖案化一光阻。光阻可藉由旋塗或類似物形成且可曝露於光以用於圖案化。光阻之圖案對應於金屬化圖案138。圖案化形成穿過光阻之開口以曝露晶種層。在光阻之開口中及晶種層之曝露部分上形成一導電材料。導電材料可藉由鍍覆形成，諸如電鍍或無電式電鍍或類似物。導電材料可包括一金屬，諸如銅、鈦、鎢、鋁或類似物。接著，移除光阻及其上未形成導電材料之晶種層之部分。光阻可藉由一可接受之灰化或剝離程序移除，諸如使用一氧電漿或類似物。一旦移除光阻，即移除晶種層之曝露部分，諸如藉由使用一可接受之蝕刻程序(諸如藉由濕式或乾式蝕刻)。晶種層之剩餘部分及導電材料形成金屬化圖案138及通路。通路形成在穿過介電層132至(例如)貫穿通路112及/晶粒連接器126之開口中。 在圖9中，在金屬化圖案138及介電層132上沉積介電層140。在一些實施例中，介電層140由一聚合物形成，其可係可使用一微影遮罩圖案化之一光敏材料，諸如PBO、聚醯亞胺、BCB或類似物。在其他實施例中，介電層140由氮化物，諸如氮化矽；氧化物，諸如氧化矽、PSG、BSG、BPSG；或類似物形成。介電層140可藉由旋塗、層壓、CVD、類似物或其等之一組合形成。 在圖10中，接著圖案化介電層140。圖案化形成開口以曝露金屬化圖案138之部分。圖案化可藉由一可接受程序，諸如當介電層係一光敏材料時藉由將介電層140曝露於光或藉由使用(例如)一各向異性蝕刻蝕刻。若介電層140係一光敏材料，則介電層140可在曝露之後顯影。 在圖11中，在介電層140上形成具有通路之金屬化圖案146。如形成金屬化圖案146之一實例，在介電層140上方及穿過介電層140之開口中形成一晶種層(未展示)。在一些實施例中，晶種層係一金屬層，其可係一單一層或包括由不同材料形成之複數個子層之一複合層。在一些實施例中，晶種層包括一鈦層及鈦層上方之一銅層。晶種層可使用(例如) PVD或類似物形成。接著，在晶種層上形成且圖案化一光阻。光阻可藉由旋塗或類似物形成且可曝露於光以用於圖案化。光阻之圖案對應於金屬化圖案146。圖案化形成穿過光阻之開口以曝露晶種層。在光阻之開口中及晶種層之曝露部分上形成一導電材料。導電材料可藉由鍍覆形成，諸如電鍍或無電式電鍍或類似物。導電材料可包括一金屬，諸如銅、鈦、鎢、鋁或類似物。接著，移除光阻及其上未形成導電材料之晶種層之部分。光阻可藉由一可接受之灰化或剝離程序移除，諸如使用一氧電漿或類似物。一旦移除光阻，即移除晶種層之曝露部分，諸如藉由使用一可接受之蝕刻程序(諸如藉由濕式或乾式蝕刻)。晶種層之剩餘部分及導電材料形成金屬化圖案146及通路。通路形成在穿過介電層140至(例如)金屬化圖案138之部分之開口中。 在圖12中，在金屬化圖案146及介電層140上沉積介電層148。在一些實施例中，介電層148由一聚合物形成，其可係可使用一微影遮罩圖案化之一光敏材料，諸如PBO、聚醯亞胺、BCB或類似物。在其他實施例中，介電層148由氮化物，諸如氮化矽；氧化物，諸如氧化矽、PSG、BSG、BPSG；或類似物形成。介電層148可藉由旋塗、層壓、CVD、類似物或其等之一組合形成。 在圖13中，接著圖案化介電層148。圖案化形成開口以曝露金屬化圖案146之部分。圖案化可藉由一可接受程序，諸如當介電層係一光敏材料時藉由將介電層148曝露於光或藉由使用(例如)一各向異性蝕刻蝕刻。若介電層148係一光敏材料，則介電層148可在曝露之後顯影。 在圖14中，在介電層148上形成具有通路之金屬化圖案154。如形成金屬化圖案154之一實例，在介電層148上方及穿過介電層148之開口中形成一晶種層(未展示)。在一些實施例中，晶種層係一金屬層，其可係一單一層或包括由不同材料形成之複數個子層之一複合層。在一些實施例中，晶種層包括一鈦層及鈦層上方之一銅層。晶種層可使用(例如) PVD或類似物形成。接著，在晶種層上形成且圖案化一光阻。光阻可藉由旋塗或類似物形成且可曝露於光以用於圖案化。光阻之圖案對應於金屬化圖案154。圖案化形成穿過光阻之開口以曝露晶種層。在光阻之開口中及晶種層之曝露部分上形成一導電材料。導電材料可藉由鍍覆形成，諸如電鍍或無電式電鍍或類似物。導電材料可包括一金屬，諸如銅、鈦、鎢、鋁或類似物。接著，移除光阻及其上未形成導電材料之晶種層之部分。光阻可藉由一可接受之灰化或剝離程序移除，諸如使用一氧電漿或類似物。一旦移除光阻，即移除晶種層之曝露部分，諸如藉由使用一可接受之蝕刻程序(諸如藉由濕式或乾式蝕刻)。晶種層之剩餘部分及導電材料形成金屬化圖案154及通路。通路形成在穿過介電層148至(例如)金屬化圖案146之部分之開口中。 在圖15中，在金屬化圖案154及介電層148上沉積介電層156。在一些實施例中，介電層156由一聚合物形成，其可係可使用一微影遮罩圖案化之一光敏材料，諸如PBO、聚醯亞胺、BCB或類似物。在其他實施例中，介電層156由氮化物，諸如氮化矽；氧化物，諸如氧化矽、PSG、BSG、BPSG；或類似物形成。介電層156可藉由旋塗、層壓、CVD、類似物或其等之一組合形成。 在圖16中，接著圖案化介電層156。圖案化形成開口以曝露金屬化圖案154之部分以用於墊162之後續形成。圖案化可藉由一可接受程序，諸如當介電層係一光敏材料時藉由將介電層156曝露於光或藉由使用(例如)一各向異性蝕刻蝕刻。若介電層156係一光敏材料，則介電層156可在曝露之後顯影。 展示前側重佈結構160作為一實例。可在前側重佈結構160中形成更多或更少之介電層及金屬化圖案。若將形成更少之介電層及金屬化圖案，則可省略上文論述之步驟及程序。若將形成更多之介電層及金屬化圖案，則可重複上文論述之步驟及程序。一般技術者將輕易理解將省略或重複哪些步驟及程序。 在圖17中，在前側重佈結構160之一外側上形成墊162。墊162用於耦合至導電連接器166及整合式被動裝置170 (見圖18)且可稱為凸塊下金屬化層(UBM) 162。在繪示之實施例中，墊162透過穿過介電層156至金屬化圖案154之開口形成。如形成墊162之一實例，在介電層156上方形成一晶種層(未展示)。在一些實施例中，晶種層係一金屬層，其可係一單一層或包括由不同材料形成之複數個子層之一複合層。在一些實施例中，晶種層包括一鈦層及鈦層上方之一銅層。晶種層可使用(例如) PVD或類似物形成。接著，在晶種層上形成且圖案化一光阻。光阻可藉由旋塗或類似物形成且可曝露於光以用於圖案化。光阻之圖案對應於墊162。圖案化形成穿過光阻之開口以曝露晶種層。在光阻之開口中及晶種層之曝露部分上形成一導電材料。導電材料可藉由鍍覆形成，諸如電鍍或無電式電鍍或類似物。導電材料可包括一金屬，諸如銅、鈦、鎢、鋁或類似物。接著，移除光阻及其上未形成導電材料之晶種層之部分。光阻可藉由一可接受之灰化或剝離程序移除，諸如使用一氧電漿或類似物。一旦移除光阻，即移除晶種層之曝露部分，諸如藉由使用一可接受之蝕刻程序(諸如藉由濕式或乾式蝕刻)。晶種層之剩餘部分及導電材料形成墊162。在其中墊162不同地形成的實施例中，可利用更多光阻及圖案化步驟。 在圖18中，在墊162上形成導電連接器166且將IPD組件170接合至金屬化圖案墊162。IPD組件可使用具有一焊料層之微凸塊接合至UBM 162。在一些實施例中，可在將IPD組件接合且安裝至墊162之前，將導電連接器166安裝於墊162上。在一些實施例中，可在將IPD組件接合且安裝至墊162之後，將導電連接器166安裝於墊162上。 在接合至墊162之前，可根據可適用製程處理IPD組件170以在IPD組件170中形成被動裝置。例如，IPD組件各包括IPD組件170之主結構172中之一或多個被動裝置。主結構172可包含一基板及/或囊封物。在包含一基板之實施例中，基板可係一半導體基板(諸如摻雜或未摻雜矽)或一SOI基板之一主動層。半導體基板可包含其他半導體材料，諸如鍺；一化合物半導體，其包含碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦及/或銻化銦；一合金半導體，其包含SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP；或其等之組合。亦可使用其他基板，諸如多層或梯度基板。被動裝置可包含一電容器、電阻器、電感器、類似物或其等之一組合。被動裝置可在半導體基板中及/或其上及/或在囊封物內形成且可藉由(例如)由主結構172上之一或多個介電層中之金屬化圖案形成之互連結構174互連以形成一整合式被動裝置170。 IPD組件170進一步包括形成且耦合至互連件174之微凸塊176，製作至該等凸塊之外部連接。微凸塊176具有在微凸塊176之一端上形成之一焊料層或凸塊178，該焊料層或凸塊178在前側重佈結構160與IPD組件170之間形成一焊料接頭。與習知焊球(諸如用於一球柵陣列(BGA)連接器(見導電連接器166)中之該等焊球，其等可具有在從(例如)約150 µm至約300 µm之範圍中之一直徑)相比，微凸塊176具有在從(例如)約10 µm至約40 µm之範圍中之小得多之直徑。在一些實施例中，微凸塊176可具有約40 µm或更大之一節距。 在一些實施例中，IPD組件170在接合程序期間無法被壓迫至前側重佈結構160上。在此等實施例中，IPD組件170之接合可藉由使用(例如)一取置工具將IPD組件170定位於導電連接器166之高度而開始。接著，取置工具將IPD組件170下放於前側重佈結構160之開口164及曝露金屬化圖案154上。在一後續接合程序期間，微凸塊176藉由(例如)一回銲程序接合至金屬化圖案154，且由於該接合程序，形成焊料接頭，該等焊料接頭將IPD組件170之微凸塊176與封裝之墊162電連接且機械連接。微凸塊176之小大小容許微凸塊176之間的細小節距且實現高密度連接。 導電連接器166可係BGA連接器、焊球、金屬柱、受控倒疊晶片連接(C4)凸塊、微凸塊、無電鎳無電鈀浸金技術(ENEPIG)形成之凸塊或類似物。導電連接器166可包含一導電材料，諸如焊料、銅、鋁、金、鎳、銀、鈀、錫、類似物或其等之一組合。在一些實施例中，首先藉由透過此等常用方法(諸如蒸鍍、電鍍、印刷、焊料轉移、焊球放置或類似物)形成一焊料層而形成導電連接器166。一旦已在結構上形成一焊料層，即可執行一回銲以便將材料塑形為所需凸塊形狀。在另一實施例中，導電連接器166係藉由一濺鍍、印刷、電鍍、無電式電鍍、CVD或類似物形成之金屬柱(諸如一銅柱)。金屬柱可不含焊料且具有大體上垂直之側壁。在一些實施例中，在金屬柱連接器166之頂部上形成一金屬罩層(未展示)。金屬罩層可包含鎳、錫、錫鉛、金、銀、鈀、銦、鎳鈀金、鎳金、類似物或其等之一組合且可藉由一鍍覆程序形成。 圖19及圖20繪示用於封裝結構之單粒化程序之一預切割程序。一切割設備182在第一區600與第二區602之間的一切割道區域中部分切割至重佈結構160中以在重佈結構160中形成凹槽184。在一些實施例中，用於預切割程序之切割設備182係一雷射。預切割程序可在後續單粒化程序期間防止重佈結構及其層之分層(見例如圖24)。 在圖21中，執行一載體基板去接合以將載體基板100與背側重佈結構(例如，介電層104)脫離(去接合)。根據一些實施例，去接合包含將一光(諸如一雷射光或一UV光)投影於離型層102上，使得離型層102在光之加熱下分解且可移除載體基板100。接著，結構經倒置且放置於一膠帶190上。 如在圖21中進一步繪示，形成穿過介電層104之開口以曝露金屬化圖案106之部分。(例如)使用雷射鑽孔、蝕刻或類似物來形成開口。 在圖22中，使用延伸穿過介電層104中之開口之導電連接器314將第二封裝300接合至形成之第一封裝200。第二封裝300與第一封裝200之間的接合可係一焊料接合或一直接金屬至金屬(諸如一銅至銅或錫至錫)接合。在一實施例中，藉由一回銲程序將第二封裝300接合至第一封裝200。在此回銲程序期間，導電連接器314與接墊304及金屬化圖案106接觸以將第二封裝300實體且電耦合至第一封裝200。在接合程序後，一IMC (未展示)可在金屬化圖案106及導電連接器314之介面處形成且亦在導電連接器314與接墊304之介面(未展示)處形成。 在接合至第一封裝200之前，可根據可適用製程處理第二封裝300以形成第二封裝300。例如，第二封裝300各包含一基板302及耦合至基板302之一或多個堆疊晶粒308 (308A及308B)。基板302可由一半導體材料製成，諸如矽、鍺、鑽石或類似物。在一些實施例中，亦可使用化合物材料，諸如矽鍺、碳化矽、砷化鎵、砷化銦、磷化銦、碳化矽鍺、磷化鎵砷、磷化鎵銦、此等之組合及類似物。另外，基板302可為一SOI基板。一般言之，一SOI基板包含一半導體材料層，諸如磊晶矽、鍺、矽鍺、SOI、絕緣體上矽鍺(SGOI)或其等之組合。在一項替代實施例中，基板302係基於一絕緣核心，諸如一玻璃纖維增強樹脂核心。一個例示性核心材料係諸如FR4之玻璃纖維樹脂。核心材料之替代例包含雙馬來醯亞胺三嗪(BT)樹脂或替代性地其他印刷電路板(PCB)材料或薄膜。諸如Ajinomoto增層薄膜(ABF)之增層薄膜或其他層壓材料可用於基板302。 基板302可包含主動裝置及被動裝置(未展示)。如一般技術者將認識到，諸如電晶體、電容器、電阻器、此等之組合及類似物之多種裝置可用於產生半導體封裝300之設計之結構及功能要求。可使用任何合適方法形成裝置。 基板302亦可包含金屬化層(未展示)及貫穿通路306。金屬化層可形成在主動裝置及被動裝置上方且經設計以連接各種裝置以形成功能電路。金屬化層可由介電材料(例如，低介電係數介電材料)與導電材料(例如，銅)之交替層形成(其中通路互連導電材料層)且可透過任何合適程序(諸如沉積、鑲嵌、雙鑲嵌或類似物)而形成。在一些實施例中，基板302大體上不含主動裝置及被動裝置。 基板302可具有在基板302之一第一側上用以耦合至堆疊晶粒308之接墊303，及在基板302之一第二側(該第二側與基板302之第一側相對)上用以耦合至導電連接器314之接墊304。在一些實施例中，藉由形成凹槽(未展示)至基板302之第一側及第二側上之介電層(未展示)中而形成接墊303及304。可形成凹槽以容許接墊303及304嵌入介電層中。在其他實施例中，由於可在介電層上形成接墊303及304，故省略凹槽。在一些實施例中，接墊303及304包含由銅、鈦、鎳、金、鈀、類似物或其等之一組合製成之一薄晶種層(未展示)。可在薄晶種層上方沉積接墊303及304之導電材料。可藉由一電化學電鍍程序、一無電式電鍍程序、CVD、ALD、PVD、類似物或其等之一組合形成導電材料。在一實施例中，接墊303及304之導電材料係銅、鎢、鋁、銀、金、類似物或其等之一組合。 在一實施例中，接墊303及304係包含三個導電材料層(諸如一鈦層、一銅層及一鎳層)之UBM。然而，一般技術者將認識到，存在材料及層之許多合適配置，諸如鉻/鉻銅合金/銅/金之一配置、鈦/鈦鎢/銅之一配置或銅/鎳/金之一配置，其等適用於UBM 303及304之形成。可用於UBM 303及304之任何合適材料或材料層完全旨在包含於當前申請案之範疇內。在一些實施例中，貫穿通路306延伸穿過基板302且將至少一個接墊303耦合至至少一個接墊304。 在所繪示之實施例中，可藉由導線接合310將堆疊晶粒308耦合至基板302，儘管可使用其他連接，諸如導電凸塊。在一實施例中，堆疊晶粒308係堆疊記憶體晶粒。例如，堆疊記憶體晶粒308可包含低功率(LP)雙倍資料速率(DDR)記憶體模組，諸如LPDDR1、LPDDR2、LPDDR3、LPDDR4或類似記憶體模組。 在一些實施例中，可藉由一模塑料312囊封堆疊晶粒308及導線接合310。例如，可使用壓縮成型使模塑料312在堆疊晶粒308及導線接合310上成型。在一些實施例中，模塑料312係一模塑料、一聚合物、一環氧樹脂、氧化矽填充材料、類似物或其等之一組合。可執行一固化步驟以使模塑料312固化，其中固化可係一熱固化、一UV固化、類似物或其等之一組合。 在一些實施例中，堆疊晶粒308及導線接合310經埋設於模塑料312中，且在模塑料312之固化之後，執行一平坦化步驟(諸如一研磨)以移除模塑料312之過量部分且提供第二封裝300之一實質上平坦表面。 在形成第二封裝300之後，封裝300經由導電連接器314、接墊304及金屬化圖案106接合至第一封裝200。在一些實施例中，堆疊記憶體晶粒308可透過導線接合310、接墊303及304、貫穿通路306、導電連接器314及貫穿通路112耦合至積體電路晶粒114。 導電連接器314可類似於上文描述之導電連接器166且不在本文中重複描述，儘管導電連接器314及166無需相同。在一些實施例中，在接合導電連接器314之前，使用一助焊劑(未展示)(諸如一免清洗助焊劑)塗佈導電連接器314。可將導電連接器314浸漬於助焊劑中或可將助焊劑噴射至導電連接器314上。在另一實施例中，可將助焊劑施覆於金屬化圖案106之表面。 在一些實施例中，在使用在第二封裝300附接至第一封裝200之後剩餘之環氧樹脂助焊劑之環氧樹脂部分之至少一些回銲導電連接器314之前，導電連接器314可具有在其上形成之一環氧樹脂助焊劑(未展示)。 圖23繪示第一封裝200與第二封裝300之間的一底膠填充322之施配。底膠填充322材料可係具有填充物或助焊劑之環氧樹脂或聚合物。底膠填充322使用一噴頭320施配且在相鄰第二封裝300之間施配以在第一封裝200與第二封裝300之間且圍繞導電連接器314流動。如在圖23中繪示，一切割道區中之底膠填充322之一個施配點可在區600與602之兩者之間形成第一封裝200與第二封裝之間的底膠填充322。此增大底膠填充程序之處理量。底膠填充322可藉由一沉積或印刷方法形成，但任何合適程序將係可適用的。在一些實施例中，底膠填充322可藉由一毛細管流動程序在第一封裝200與第二封裝300之間流動。在一些實施例中，底膠填充可按高於環境大氣壓力之一壓力施配/注射於一腔室或爐中。 在圖24中，底膠填充322在兩個區600及602中形成於第一封裝200與第二封裝300之間且亦沿著第二封裝300之側壁向上延伸。此全覆蓋底膠填充程序可藉由在施配步驟期間添加過量底膠填充322且藉由在一更高壓力環境中使底膠填充固化而達成。 在施配之後，底膠填充322在一固化操作中固化。可在一腔室或爐中按高於環境大氣壓力之一壓力執行固化操作。在一些實施例中，在底膠填充固化程序期間之腔室之壓力在從約3 kg/cm2 至約20 kg/cm2 之一範圍中。在固化程序期間之更高壓力可加速底膠填充322中之空隙的移動，此可改良且增加底膠填充322之流速(例如，底膠填充322在第一封裝200與第二封裝300之間流動的速度)。在固化操作之後，可固化底膠填充322之一頂部表面322A。在一些實施例中，彎曲頂部表面322A係一凹表面。在一些實施例中，歸因於所施配之過量底膠填充322，底膠填充322可延伸至第二封裝300之頂部表面(且有時沿著頂部表面的一些延伸)。 在圖25中，藉由沿著(例如)相鄰區600與602之間的切割道區之單粒化186執行一單粒化程序。在一些實施例中，單粒化186包含一鋸切程序、一雷射程序或其等之一組合。單粒化186使第一封裝區600從第二封裝區602且從其他相鄰區(未展示)單粒化。 圖26繪示包含可來自第一封裝區600或第二封裝區602之一者之一第一封裝200及一第二封裝300之一所得單粒化封裝結構。封裝200亦可稱為一整合式扇出(InFO)封裝200。 圖27繪示圖26中展示之封裝結構之一部分之一細節圖。特定言之，圖27繪示在單粒化程序之後之底膠填充322之側壁之一細節圖。底膠填充322具有擁有一彎曲側壁之一部分(經單粒化之先前彎曲頂部表面322A)及擁有一實質上平坦部分之一部分。在一些實施例中，彎曲側壁係一凹表面。 彎曲部分至平坦部分之一轉變點係在垂直於基板302之一主表面之一方向上量測之距第二封裝300之頂部(例如，模塑料312之頂部)之一距離A。在一些實施例中，距離A在從約100 µm至約150 µm之一範圍中。 平坦部分具有距離B+C之一高度，如在圖27中繪示。在垂直於基板302之一主表面之一方向上量測從第二封裝300之底部(例如，基板302之底部)至轉變點之距離B。在一些實施例中，距離B在從約300 µm至約400 µm之一範圍中。 距離C係在垂直於基板302之一主表面之一方向上量測之第一封裝200與第二封裝300之間的間隙高度。在一些實施例中，距離C在從約50 µm至約150 µm之一範圍中。在一些實施例中，C/(B+C)之一比在從約0.14至約0.27之一範圍中。 藉由圖27中之一距離D展示第二封裝300之側壁上之底膠填充322之一厚度。可量測從第二封裝300之一側壁(例如，模塑料312之側壁)至重佈結構160中之一密封環(未在圖27中展示)之一外界限之距離D。在一些實施例中，距離D在從約50 µm至約100 µm之一範圍中。 在彎曲表面至平坦表面之轉變點處之底膠填充322之彎曲表面之角度在圖27中展示為角度α。在一些實施例中，角度α在從約30度至約80度之一範圍中。 圖28繪示包含第一封裝200、第二封裝300及一基板400之一封裝結構500。半導體封裝500包含安裝至一基板400之封裝200及300。基板400可稱為一封裝基板400。使用導電連接器166將封裝200安裝至封裝基板400。在封裝200安裝至基板400的情況下，(諸) IPD組件170插置於封裝200之重佈結構160與基板400之間。 封裝基板400可由一半導體材料製成，諸如矽、鍺、鑽石或類似物。替代地，亦可使用化合物材料，諸如矽鍺、碳化矽、砷化鎵、砷化銦、磷化銦、碳化矽鍺、磷化鎵砷、磷化鎵銦、此等之組合及類似物。另外，封裝基板400可為一SOI基板。一般言之，一SOI基板包含一半導體材料層，諸如磊晶矽、鍺、矽鍺、SOI、SGOI或其等之組合。在一項替代實施例中，封裝基板400係基於一絕緣核心，諸如一玻璃纖維增強樹脂核心。一個例示性核心材料係諸如FR4之玻璃纖維樹脂。用於核心材料之替代例包含雙馬來醯亞胺三嗪BT樹脂或替代性地其他PCB材料或薄膜。諸如ABF之增層薄膜或其他層壓材料可用於封裝基板400。 封裝基板400可包含主動裝置及被動裝置(未在圖22中展示)。如一般技術者將認識到，諸如電晶體、電容器、電阻器、此等之組合及類似物之多種裝置可用於產生半導體封裝500之設計之結構及功能要求。可使用任何合適方法形成裝置。 封裝基板400亦可包含金屬化層及通路(未展示)及金屬化層及通路上方之接墊402。金屬化層可形成在主動裝置及被動裝置上方且經設計以連接各種裝置以形成功能電路。金屬化層可由介電材料(例如，低介電係數介電材料)與導電材料(例如，銅)之交替層形成(其中通路互連導電材料層)且可透過任何合適程序(諸如沉積、鑲嵌、雙鑲嵌或類似物)而形成。在一些實施例中，封裝基板400大體上不含主動裝置及被動裝置。 在一些實施例中，導電連接器166可經回銲以將封裝200附接至接墊402。導電連接器166將基板400 (包含基板400中之金屬化層)電及/或實體耦合至第一封裝200。 在使用在封裝200附接至基板400之後剩餘之環氧樹脂助焊劑之環氧樹脂部分之至少一些回銲導電連接器166之前，導電連接器314可具有在其上形成之一環氧樹脂助焊劑(未展示)。此剩餘環氧樹脂部分可充當一底膠填充以減小應力且保護由回銲導電連接器166所得之接頭。在一些實施例中，可在第一封裝200與基板400之間且圍繞導電連接器166及IPD組件170形成一底膠填充(未展示)。底膠填充可在附接封裝200之後藉由一毛細管流動程序形成或可在附接封裝200之前藉由一合適沉積方法形成。 本揭露之實施例包含一封裝結構，該封裝結構包含一全覆蓋底膠填充程序，該程序改良封裝之側壁之保護，其改良封裝結構之可靠性及良率。所揭示之全覆蓋底膠填充程序亦增大底膠填充流速且可簡化封裝單粒化程序。底膠填充可按高於其他底膠填充程序之一壓力固化。此壓力增大可加速固化程序期間之底膠填充中之空隙的移動。 一實施例係一結構，其包含：一第一封裝，其包含一第一晶粒及至少側向囊封該第一晶粒之一模塑料；一第二封裝，其使用一第一組導電連接器接合至該第一封裝，該第二封裝包括一第二晶粒；及一底膠填充，其在該第一封裝與該第二封裝之間且圍繞該第一組導電連接器，該底膠填充具有沿著該第二封裝之一側壁向上延伸之一第一部分，該第一部分具有一第一側壁，該第一側壁具有一彎曲部分及一平坦部分。 另一實施例係一方法，其包含：形成複數個第一封裝，該複數個第一封裝之各者包括藉由一模塑料圍繞之一第一晶粒及上覆該第一晶粒之一第一側及該模塑料之一重佈結構，該重佈結構包括金屬化圖案；將包括凸塊下金屬化層之一第一組導電連接器耦合至該重佈結構之一第一金屬化圖案；使用一第二組導電連接器將複數個第二封裝接合至該複數個第一封裝，該第二封裝靠近該第一晶粒之一第二側，該第二側與該第一側相對；及在相鄰第二封裝之間及第一封裝與第二封裝之間之切割道區中且圍繞第二組導電連接器施配底膠填充，底膠填充沿著複數個第二封裝之側壁向上延伸，底膠填充具有相鄰第二封裝之間的彎曲、凹頂部表面。 一進一步實施例係一方法，其包含：形成複數個第一封裝，形成第一封裝之各者包含在一載體基板上方形成一電連接器；將一第一晶粒附接至載體基板，該電連接器從第一晶粒之一第二側延伸至第一晶粒之一第一側，第二側與第一側相對；使用一模塑料囊封第一晶粒及電連接器，電連接器延伸穿過模塑料；形成上覆第一晶粒之第一側及模塑料之一重佈結構；將一第一組導電連接器耦合至重佈結構；鄰近於第一組導電連接器將一被動組件接合至重佈結構；且移除載體基板。方法進一步包含：使用一第二組導電連接器將複數個第二封裝接合至複數個第一封裝，該第二封裝靠近該第一晶粒之第二側；在第一封裝與第二封裝之間及圍繞導第二組導電連接器施配底膠填充，底膠填充沿著複數個第二封裝之側壁向上延伸，底膠填充具有相鄰第二封裝之間的凹頂部表面；且單粒化複數個第一封裝以形成封裝結構，單粒化在凹頂部表面處切割穿過底膠填充以形成具有一凹部分及一平坦部分之底膠填充之一側壁。 前文概述數種實施例之特徵，使得熟習此項技術者可更佳理解本揭露之態樣。熟習此項技術者應明白，其等可容易將本揭露用作設計或修改用於實行本文中介紹之實施例之相同目的及/或達成相同優點之其他程序及結構之一基礎。熟習此項技術者亦應認識到，此等等效構造並未脫離本揭露之精神及範疇，且其等可在不脫離本揭露之精神及範疇的情況下在本文中進行各種改變、置換及更改。
100‧‧‧載體基板
102‧‧‧離型層
104‧‧‧介電層
106‧‧‧金屬化圖案
108‧‧‧介電層
110‧‧‧背側重佈結構
112‧‧‧貫穿通路
114‧‧‧積體電路晶粒
116‧‧‧黏合劑
118‧‧‧半導體基板
120‧‧‧互連結構
122‧‧‧墊
124‧‧‧鈍化薄膜
126‧‧‧晶粒連接器
128‧‧‧介電材料
130‧‧‧囊封物
132‧‧‧介電層
138‧‧‧金屬化圖案
140‧‧‧介電層
146‧‧‧金屬化圖案
148‧‧‧介電層
154‧‧‧金屬化圖案
156‧‧‧介電層
160‧‧‧前側重佈結構
162‧‧‧墊
166‧‧‧導電連接器
170‧‧‧IPD組件/整合式被動裝置
172‧‧‧主結構
174‧‧‧互連結構
176‧‧‧微凸塊
178‧‧‧焊料層或凸塊
182‧‧‧切割設備
184‧‧‧凹槽
186‧‧‧單粒化
190‧‧‧膠帶
200‧‧‧第一封裝
300‧‧‧第二封裝
302‧‧‧基板
303‧‧‧接墊
304‧‧‧接墊
306‧‧‧貫穿通路
308A‧‧‧堆疊晶粒
308B‧‧‧堆疊晶粒
310‧‧‧導線接合
312‧‧‧模塑料
314‧‧‧導電連接器
320‧‧‧噴頭
322‧‧‧底膠填充
322A‧‧‧彎曲頂部表面
400‧‧‧封裝基板
402‧‧‧接墊
500‧‧‧半導體封裝
600‧‧‧第一封裝區
602‧‧‧第二封裝區
A‧‧‧距離
B‧‧‧距離
C‧‧‧距離
D‧‧‧距離
α‧‧‧角度
當結合附圖閱讀時，自以下實施方式最佳理解本揭露之態樣。應注意，根據行業中之標準實踐，各種構件未按比例繪製。事實上，為清楚論述，各個構件之大小可任意增大或減小。 圖1至圖28繪示根據一些實施例之在用於形成一封裝結構之一程序期間之中間步驟之剖面圖。

Claims (10)

  1. 一種結構，其包括： 一第一封裝，其包括： 一第一晶粒；及 一模塑料，其至少側向囊封該第一晶粒； 一第二封裝，其使用一第一組導電連接器接合至該第一封裝，該第二封裝包括一第二晶粒；及 一底膠填充，其在該第一封裝與該第二封裝之間且圍繞該第一組導電連接器，該底膠填充具有沿著該第二封裝之一側壁向上延伸之一第一部分，該第一部分具有一第一側壁，該第一側壁具有一彎曲部分及一平坦部分。
  2. 如請求項1之結構，其中該第一側壁之該平坦部分插置於該第一側壁之該彎曲部分與該第一封裝之間。
  3. 如請求項1之結構，其中該底膠填充延伸至該第二封裝之一頂部表面。
  4. 一種方法，其包括： 形成複數個第一封裝，該複數個第一封裝之各者包括藉由一模塑料圍繞之一第一晶粒及上覆該第一晶粒之一第一側及該模塑料之一重佈結構，該重佈結構包括金屬化圖案； 將包括凸塊下金屬化層之一第一組導電連接器耦合至該重佈結構之一第一金屬化圖案； 使用一第二組導電連接器將複數個第二封裝接合至該複數個第一封裝，該第二封裝靠近該第一晶粒之一第二側，該第二側與該第一側相對；及 在相鄰第二封裝之間且在該等第一封裝與該等第二封裝之間之切割道區中且圍繞該第二組導電連接器施配一底膠填充，該底膠填充沿著該複數個第二封裝之側壁向上延伸，該底膠填充具有該等相鄰第二封裝之間的彎曲、凹頂部表面。
  5. 如請求項4之方法，其進一步包括： 使該複數個第一封裝及第二封裝單粒化以形成封裝結構，該單粒化在該等彎曲、凹頂部表面處切割穿過該底膠填充以形成具有一彎曲、凹部分及一平坦部分之底膠填充之一側壁。
  6. 如請求項5之方法，其中使該複數個第一封裝及第二封裝單粒化以形成封裝結構包括： 在將該複數個第二封裝接合至該複數個第一封裝之前，藉由部分切割至該重佈結構中而預切割該複數個第一封裝；及 在將該複數個第二封裝接合至該複數個第一封裝且形成該底膠填充之後，切割穿過該底膠填充及該複數個第一封裝以形成該等封裝結構。
  7. 如請求項4之方法，其進一步包括： 將一整合式被動裝置組件接合至該重佈結構之一第一金屬化圖案上之一凸塊下金屬化層，該IPD組件鄰近於該第一組導電連接器；及 使用該第一組導電連接器將該等封裝結構接合至一基板，該整合式被動裝置組件插置於該基板與該第一封裝之該重佈結構之間。
  8. 如請求項4之方法，其進一步包括 按高於環境大氣壓力之一壓力使該施配底膠填充固化。
  9. 如請求項4之方法，其中形成該複數個第一封裝之各者包括： 在一載體基板上方形成一電連接器； 將一第一晶粒附接至該載體基板，該電連接器從該第一晶粒之一第二側延伸至該第一晶粒之該第一側，該電連接器鄰近於該第一晶粒； 使用一模塑料囊封該第一晶粒及該電連接器；及 形成上覆該第一晶粒之該第一側及該模塑料之該重佈結構。
  10. 一種方法，其包括： 形成複數個第一封裝，形成該等第一封裝之各者包括： 在一載體基板上方形成一電連接器； 將一第一晶粒附接至該載體基板，該電連接器從該第一晶粒之一第二側延伸至該第一晶粒之一第一側，該第二側與該第一側相對； 使用一模塑料囊封該第一晶粒及該電連接器，該電連接器延伸穿過該模塑料； 形成上覆該第一晶粒之該第一側及該模塑料之一重佈結構； 將一第一組導電連接器耦合至該重佈結構； 鄰近於該第一組導電連接器將一被動組件耦合至該重佈結構；及 移除該載體基板； 使用一第二組導電連接器將複數個第二封裝接合至該複數個第一封裝，該第二封裝靠近該第一晶粒之該第二側； 在該等第一封裝與該等第二封裝之間及圍繞該第二組導電連接器施配底膠填充，該底膠填充沿著該複數個第二封裝之側壁向上延伸，該底膠填充具有相鄰第二封裝之間的凹頂部表面；且 使該複數個第一封裝及第二封裝單粒化以形成封裝結構，該單粒化在該等凹頂部表面處切割穿過該底膠填充以形成具有一凹部分及一平坦部分之底膠填充之一側壁。
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Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3314649A4 (en) * 2015-06-25 2019-01-09 Intel Corporation INTEGRATED CIRCUIT STRUCTURES WITH CONDUCTOR CONTACTS IN REMOVAL FOR STRUCTURE HOUSING ON HOUSING
WO2017171738A1 (en) 2016-03-30 2017-10-05 Intel Corporation Hybrid microelectronic substrates
US10438930B2 (en) * 2017-06-30 2019-10-08 Intel Corporation Package on package thermal transfer systems and methods
US10636757B2 (en) * 2017-08-29 2020-04-28 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit component package and method of fabricating the same
JP6892360B2 (ja) * 2017-09-19 2021-06-23 キオクシア株式会社 半導体装置
US10840227B2 (en) 2017-11-02 2020-11-17 Taiwan Semiconductor Manufacturing Company, Ltd. Under-bump-metallization structure and redistribution layer design for integrated fan-out package with integrated passive device
KR102440009B1 (ko) 2018-03-16 2022-09-05 현대모비스 주식회사 차량용 제동장치
US11380616B2 (en) * 2018-05-16 2022-07-05 Intel IP Corporation Fan out package-on-package with adhesive die attach
US10651131B2 (en) * 2018-06-29 2020-05-12 Taiwan Semiconductor Manufacturing Company, Ltd. Supporting InFO packages to reduce warpage
KR102556517B1 (ko) * 2018-08-28 2023-07-18 에스케이하이닉스 주식회사 브리지 다이를 포함하는 스택 패키지
EP3621107A1 (en) * 2018-09-10 2020-03-11 AT & S Austria Technologie & Systemtechnik Aktiengesellschaft Component with dielectric layer for embedding in component carrier
US11121089B2 (en) 2018-11-30 2021-09-14 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method
US11217546B2 (en) 2018-12-14 2022-01-04 Taiwan Semiconductor Manufacturing Company, Ltd. Embedded voltage regulator structure and method forming same
KR102307844B1 (ko) * 2018-12-14 2021-10-06 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 임베디드 전압 조정기 구조물 및 그 형성 방법
US20200227374A1 (en) * 2019-01-14 2020-07-16 Shih-Chi Chen Fowbcsp chip module with packaging structure and manufacturing method of the same
US11600590B2 (en) * 2019-03-22 2023-03-07 Advanced Semiconductor Engineering, Inc. Semiconductor device and semiconductor package
KR20210015071A (ko) * 2019-07-31 2021-02-10 삼성전자주식회사 반도체 패키지
US11594571B2 (en) * 2020-02-27 2023-02-28 Taiwan Semiconductor Manufacturing Co., Ltd. Stacked image sensor device and method of forming same
DE102021107982B4 (de) 2020-04-07 2024-02-22 Mediatek Inc. Halbleiter-packagestruktur
US11830851B2 (en) 2020-04-07 2023-11-28 Mediatek Inc. Semiconductor package structure
KR20220109753A (ko) * 2021-01-29 2022-08-05 삼성전자주식회사 포스트를 포함하는 반도체 패키지
TW202407897A (zh) * 2022-08-04 2024-02-16 創世電股份有限公司 半導體功率元件

Family Cites Families (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6429530B1 (en) * 1998-11-02 2002-08-06 International Business Machines Corporation Miniaturized chip scale ball grid array semiconductor package
US8759964B2 (en) 2007-07-17 2014-06-24 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer level package structure and fabrication methods
US8021930B2 (en) 2009-08-12 2011-09-20 Stats Chippac, Ltd. Semiconductor device and method of forming dam material around periphery of die to reduce warpage
US8391018B2 (en) * 2009-09-28 2013-03-05 Qualcomm Incorporated Semiconductor die-based packaging interconnect
CN102859691B (zh) 2010-04-07 2015-06-10 株式会社岛津制作所 放射线检测器及其制造方法
US9048233B2 (en) 2010-05-26 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Package systems having interposers
US8361842B2 (en) 2010-07-30 2013-01-29 Taiwan Semiconductor Manufacturing Company, Ltd. Embedded wafer-level bonding approaches
US8884431B2 (en) 2011-09-09 2014-11-11 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods and structures for semiconductor devices
US9064879B2 (en) 2010-10-14 2015-06-23 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods and structures using a die attach film
US8829676B2 (en) 2011-06-28 2014-09-09 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structure for wafer level package
US9245773B2 (en) 2011-09-02 2016-01-26 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device packaging methods and structures thereof
JP2013138177A (ja) 2011-11-28 2013-07-11 Elpida Memory Inc 半導体装置の製造方法
US9000584B2 (en) 2011-12-28 2015-04-07 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor device with a molding compound and a method of forming the same
US8680647B2 (en) 2011-12-29 2014-03-25 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with passive devices and methods of forming the same
US9991190B2 (en) 2012-05-18 2018-06-05 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging with interposer frame
US8703542B2 (en) 2012-05-18 2014-04-22 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer-level packaging mechanisms
US8809996B2 (en) 2012-06-29 2014-08-19 Taiwan Semiconductor Manufacturing Company, Ltd. Package with passive devices and method of forming the same
US8872326B2 (en) 2012-08-29 2014-10-28 Taiwan Semiconductor Manufacturing Company, Ltd. Three dimensional (3D) fan-out packaging mechanisms
KR102000678B1 (ko) 2012-10-26 2019-07-16 삼성전자주식회사 반도체 장치 및 이를 제조하는 방법
US8785299B2 (en) 2012-11-30 2014-07-22 Taiwan Semiconductor Manufacturing Company, Ltd. Package with a fan-out structure and method of forming the same
US8928134B2 (en) * 2012-12-28 2015-01-06 Taiwan Semiconductor Manufacturing Company, Ltd. Package on package bonding structure and method for forming the same
US8803306B1 (en) 2013-01-18 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out package structure and methods for forming the same
US8778738B1 (en) 2013-02-19 2014-07-15 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor devices and packaging devices and methods
US9318404B2 (en) * 2013-02-05 2016-04-19 Stats Chippac, Ltd. Semiconductor device and method of forming stress relieving vias for improved fan-out WLCSP package
US9263511B2 (en) 2013-02-11 2016-02-16 Taiwan Semiconductor Manufacturing Co., Ltd. Package with metal-insulator-metal capacitor and method of manufacturing the same
US9048222B2 (en) 2013-03-06 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating interconnect structure for package-on-package devices
US9368460B2 (en) 2013-03-15 2016-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out interconnect structure and method for forming same
US8877554B2 (en) 2013-03-15 2014-11-04 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor devices, methods of packaging semiconductor devices, and PoP devices
US9196586B2 (en) 2014-02-13 2015-11-24 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package including an embedded surface mount device and method of forming the same
US9343434B2 (en) 2014-02-27 2016-05-17 Taiwan Semiconductor Manufacturing Company, Ltd. Laser marking in packages
KR102198858B1 (ko) 2014-07-24 2021-01-05 삼성전자 주식회사 인터포저 기판을 갖는 반도체 패키지 적층 구조체
US9373604B2 (en) * 2014-08-20 2016-06-21 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structures for wafer level package and methods of forming same
US9543170B2 (en) 2014-08-22 2017-01-10 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages and methods of forming the same
US9786519B2 (en) * 2015-04-13 2017-10-10 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor devices and methods of packaging semiconductor devices
KR102503892B1 (ko) * 2015-12-31 2023-02-28 삼성전자주식회사 패키지-온-패키지 타입의 반도체 패키지 및 그 제조방법
US11114407B2 (en) * 2018-06-15 2021-09-07 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out package and manufacturing method thereof
KR20210008957A (ko) * 2019-07-15 2021-01-26 삼성전자주식회사 반도체 패키지
US11605597B2 (en) * 2020-04-17 2023-03-14 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and method for manufacturing the same

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