TW201923984A - 半導體封裝及其形成方法 - Google Patents

半導體封裝及其形成方法 Download PDF

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TW201923984A
TW201923984A TW107120738A TW107120738A TW201923984A TW 201923984 A TW201923984 A TW 201923984A TW 107120738 A TW107120738 A TW 107120738A TW 107120738 A TW107120738 A TW 107120738A TW 201923984 A TW201923984 A TW 201923984A
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Prior art keywords
die
wiring
integrated circuit
semiconductor package
package
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TW107120738A
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TWI690030B (zh
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陳潔
陳憲偉
陳英儒
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台灣積體電路製造股份有限公司
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Abstract

在實施例中，半導體封裝包括第一封裝結構，其包括：具有主動側和背側的第一積體電路晶粒，主動側包括晶粒連接件；第二積體電路晶粒，相鄰於第一積體電路晶粒，且具有主動側和背側，主動側包括晶粒連接件；配線晶粒，包括接合至第一積體電路晶粒和第二積體電路晶粒的主動側的晶粒連接件，配線晶粒將第一積體電路晶粒電耦合至第二積體電路晶粒；包封體，包封第一積體電路晶粒、第二積體電路晶粒以及配線晶粒；以及第一重佈線結構，位於第一積體電路晶粒與第二積體電路晶粒上且電性連接於第一積體電路晶粒及第二積體電路晶粒。

Description

半導體封裝及其形成方法
由於各種電子構件（如電晶體、二極體、電阻器、電容器等）的積體密度不斷提高，半導體產業經歷了快速的發展。大多數情況下，積體密度的提高是由最小特徵尺寸的持續縮減導致的，這允許更多的構件被整合到給定的區域中。隨著對電子元件微縮的需求不斷增長，對半導體晶粒的更小且更具創造性的封裝技術的需求也出現了。這種封裝系統的一個例子是疊層封裝（package-on-package，PoP）技術。在PoP元件中，頂部半導體封裝被堆疊在底部半導體封裝的頂部上，以提供高水平的積集度和構件密度。一般而言，PoP技術能夠在印刷電路板（printed circuit board，PCB）上生產具有增強功能和小覆蓋面積的半導體元件。
本揭露內容提供用於實作此揭露內容的不同特徵的諸多不同實施例或實例。以下闡述組件及排列的具體實例以簡化本發明。當然，該些僅為實例而非旨在進行限制。舉例而言，以下說明中將第一特徵形成於第二特徵「之上」或第二特徵「上」可包括其中第一特徵及第二特徵被形成為直接接觸的實施例，且亦可包括其中第一特徵與第二特徵之間可形成有額外特徵以使得所述第一特徵與所述第二特徵可能不直接接觸的實施例。此外，本發明可在各種實例中重覆使用參考編號及/或字母。此種重覆使用是出於簡潔及清晰的目的，而非自身表示所論述的各種實施例及/或配置之間的關係。
此外，為易於說明，本文中可使用例如「在…之下（beneath）」、「在…下面（below）」、「下方的（lower）」、「在…之上（above）」、「上方的（upper）」等空間相對性用語來闡述圖中所示的一個元件或特徵與另一（其他）元件或特徵的關係。所述空間相對性用語旨在除圖中所繪示定向外亦囊括裝置在使用或操作中的不同定向。設備亦可具有其他定向（旋轉90度或處於其他定向），且本文中所用的空間相對性描述語可同樣相應地進行解釋。
本文所討論的實施例可以在特定的上下文中討論，即封裝結構（例如，疊層封裝（package-on-package，PoP）結構）包括連接封裝結構中的一或多個晶粒的配線晶粒（routing die）。在一些實施例中，配線晶粒是具有精細間距的配線晶粒，以使配線的間距（例如線寬和線間距）小於典型重佈線結構的間距。配線晶粒可以是積體被動元件（integrated passive device，IPD）、表面安裝元件（surface mount device，SMD）、無主動元件和被動元件的配線晶粒、積體電路晶粒或其類似者。配線晶粒可以與一或多個晶粒面對面地接合。另外，配線晶粒可以與一或多個晶粒被包封在相同的包封體中。在一些實施例中，包含一或多個晶粒和配線晶粒的封裝的前側重佈線結構可以覆蓋配線晶粒鰭，使得配線晶粒位於一或多個晶粒與前側重佈線結構之間。本揭露的實施例可以包括配線晶粒，其配線密度比典型重佈線結構的配線密度高5倍。
此外，本揭露的教示適用於包括一或多個半導體晶粒的任何封裝結構。其他實施例考慮了其他應用，例如不同的封裝類型或不同的配置，這對於在閱讀本揭露的所屬領域中具有通常知識者來說是顯而易見的。應指出，此處討論的實施例可能不一定說明結構中可能存在的每個構件或特徵。舉例而言，例如在討論一個構件可能足以表達實施例的態樣時，可能省略說明圖中的其他多個構件。此外，這裡討論的方法實施例可以被討論為以特定順序執行。然而，其他方法實施例可以按照任何邏輯順序執行。
圖1至圖15根據一些實施例繪示在用於形成封裝結構的製程期間的中間步驟的剖視圖和上視圖。圖1繪示載體基底100和形成在載體基底100上的離型層（release layer）102。此外，圖1分別示出了用於形成第一封裝和第二封裝的第一封裝區600和第二封裝區602。
載體基底100可以是玻璃載體基底、陶瓷載體基底或其類似者。載體基底100可以是晶圓，以使可同時在載體基底100上形成多個封裝。離型層102可以由聚合物系的材料形成，該材料可以與載體基底100一起從隨後步驟中形成的上覆結構移除。在一些實施例中，剝離層102為環氧樹脂系熱離型材料（thermal-release material），其在加熱時失去其黏著性，例如光熱轉換（light-to-heat-conversion，LTHC）離型塗佈層。在其他實施例中，離型層102可以是紫外光（UV）膠，當暴露於UV光線時其失去黏著性。離型層102可以液體的形態而被分配並固化、可以是層壓到載體基底100上的層壓膜或者可以是類似物。離型層102的頂部表面可以被平坦化並且可以具有高程度的共面性（coplanarity）。
在圖2中，形成介電層104和金屬化圖案106（有時稱為重佈線層或重佈線）。介電層104形成在離型層102上。介電層104的底面可以與離型層102的頂部表面接觸。在一些實施例中，介電層104由聚合物形成，聚合物例如是聚苯並噁唑（polybenzoxazole，PBO）、聚醯亞胺、苯並環丁烯（benzocyclobutene，BCB）或其類似者。在其他實施例中，介電層104由例如是氮化矽的氮化物；例如是氧化矽、磷矽玻璃（phosphosilicate glass，PSG）、硼矽玻璃（borosilicate glass，BSG）、硼摻雜磷矽玻璃（boron-doped phosphosilicate glass，BPSG）的氧化物；或其類似者形成。介電層104可以通過旋轉塗佈、化學氣相沉積（chemical vapor deposition，CVD）、層壓或其組合等任何可接受的沉積製程來形成。
金屬化圖案106形成在介電層104上。作為形成金屬化圖案106的實例，在介電層104上形成晶種層（未示出）。在一些實施例中，晶種層是金屬層，其可以是單層或包括由不同材料形成的多個子層的複合層。在一些實施例中，晶種層包括鈦層和在鈦層上的銅層。舉例而言，晶種層可藉由物理氣相沉積（physical vapor deposition，PVD）或其類似者形成。接著，在晶種層上形成光阻並將其圖案化。光阻可以藉由旋轉塗佈或其類似者形成，並可將光阻暴露於光線，以對光阻進行圖案化。光阻的圖案對應於金屬化圖案106。圖案化形成穿過光阻的開口，以暴露出晶種層。在光阻的開口處和晶種層的暴露部分上形成導電材料。導電材料可以藉由鍍覆（例如是電鍍或無電鍍）或其類似者形成。導電材料可以包含金屬，如銅、鈦、鎢、鋁或其類似者。之後，去除光阻以及未形成導電材料於其上的晶種層的一部分。光阻可以藉由可接受的灰化或剝離製程來去除，例如使用氧電漿或其類似者。一旦光阻被去除，晶種層的暴露部分也將會被去除。舉例而言，可藉由使用可接受的蝕刻製程（例如濕式蝕刻或乾式蝕刻）去除晶種層的暴露部分。晶種層的剩餘部分和導電材料構成金屬化圖案106。
在圖3中，在金屬化圖案106和介電層104上形成介電層108。在一些實施例中，介電層108由聚合物形成，該聚合物可以是光敏材料，例如聚苯並噁唑、聚醯亞胺、苯並環丁烯或其類似者，且可以使用微影罩幕對光敏材料進行圖案化。在其他實施例中，介電層108由例如是氮化矽的氮化物；例如是氧化矽、磷矽玻璃、硼矽玻璃、硼摻雜磷矽玻璃等氧化物；或其類似者形成。介電層108可以藉由旋轉塗佈、疊層、化學氣相沉積、其類似者或其組合來形成。然後將介電層108圖案化以形成開口，以暴露金屬化圖案106的一部分。可以藉由可接受的製程來對介電層108進行圖案化。舉例而言，當介電層108是光敏材料時，將介電層108暴露於光線，或藉由使用例如是非等向性蝕刻對介電層108進行蝕刻。
介電層104、介電層108以及金屬化圖案106可以稱為背側重佈線結構110。在實施例中，背側重佈線結構110包括兩個介電層（介電層104和介電層108）以及一個金屬化圖案106。在其他實施例中，背側重佈線結構110可以包括任何數量的介電層、金屬化圖案和導電通孔（conductive vias）。藉由重複進行形成金屬化圖案106和介電層108的製程，可以在背側重佈線結構110中形成一或多個額外的金屬化圖案和介電層。導電通孔（未示出）可以在形成金屬化圖案期間藉由在其下方的介電層的開口中形成金屬化圖案的晶種層與導電材料來形成。導電通孔可因此對各種金屬化圖案進行內連線並各種金屬化圖案電耦合。
在圖4中，形成電性連接件112。電性連接件112將延伸穿過隨後形成的包封體130（參見圖9），並且在下文中可以稱為穿孔（through vias）112。作為形成穿孔112的例子，在背側重佈線結構110上（例如是圖中所示的介電層108和金屬化圖案106的暴露部分）形成晶種層。在一些實施例中，晶種層是金屬層，可以是單層或包括由不同材料形成的多個子層的複合層。在一些實施例中，晶種層包括鈦層和在鈦層上的銅層。晶種層可以藉由使用例如是物理氣相沉積或其類似者來形成。在晶種層上形成光阻，並對光阻進行圖案化。光阻可能由旋轉塗佈或其類似者形成，並可暴露於光線，以進行圖案化。光阻的圖案對應於穿孔。對光阻進行圖案化而形成貫穿光阻的開口，以暴露晶種層。在光阻的開口處和晶種層的暴露部分上形成導電材料。導電材料可以藉由鍍覆（例如電鍍或無電鍍）或其類似者來形成。導電材料可以包含金屬，如銅、鈦、鎢、鋁或其類似者。去除光阻和未於其上形成導電材料的晶種層的部分。光阻可以藉由可接受的灰化或剝離製程來去除，例如使用氧電漿或其類似者。一旦光阻被去除，晶種層的暴露部分也將會被去除。舉例而言，例如藉由使用可接受的蝕刻製程（例如藉由濕式蝕刻或乾式蝕刻）來去除晶種層的暴露部分。晶種層的剩餘部分和導電材料形成穿孔112。
在圖5中，積體電路晶粒114通過黏著層116黏合在離型層102上。儘管在圖中第一封裝區600和第二封裝區602中的每一者中黏合兩個積體電路晶粒114。應該認識到，在每個封裝區中可以黏合更多或更少的積體電路晶粒114。舉例而言，每個區域可僅黏合一個積體電路晶粒114。積體電路晶粒114可以是邏輯晶粒（例如中央處理器、微控制器等）、記憶體晶粒（例如動態隨機存取記憶體（dynamic random access memory，DRAM）晶粒、靜態隨機存取記憶體（static random access memory，SRAM）晶粒等）、功率管理晶粒（例如功率管理積體電路（power management integrated circuit，PMIC）晶粒）、射頻（radio frequency，RF）晶粒、感測器晶粒、微機電系統（micro-electro-mechanical-system，MEMS）晶粒、訊號處理晶粒（例如，數位訊號處理（digital signal processing，DSP）晶粒）、前端晶粒（例如類比前端（analog front-end，AFE）晶粒）、其類似者或其組合。另外，在一些實施例中，積體電路晶粒114可以是不同的尺寸（例如不同的高度及/或表面積），而在其他實施例中，積體電路晶粒114可以是相同的尺寸（例如相同的高度及/或表面積）。
在附接於離型層102之前，積體電路晶粒114可根據適用的製造製程進行處理，以在積體電路晶粒114中形成積體電路。舉例而言，積體電路晶粒114各自包括半導體基底118，例如是經摻雜或未經摻雜的矽基底，或半導體上覆絕緣體（semiconductor-on-insulator，SOI）基底的主動層。半導體基底可以包括其他半導體材料，例如鍺；包括碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦及/或銻化銦的化合物半導體；包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP的合金半導體；或其組合。也可以使用其他基底，如多層基底或梯度基底。例如是電晶體、二極體、電容器、電阻器等元件可以形成在半導體基底118中及/或半導體基底118上，並且可以通過內連線結構120相互連接。舉例而言，金屬化圖案在半導體基底118上的一或多個介電層中形成積體電路，以形成內連線結構120。在一些實施例中，內連線結構120是用鑲嵌及/或雙鑲嵌製程形成的。
積體電路晶粒114更包括接墊122，例如銅接墊或鋁接墊。外部連線經製造以連接於接墊122。接墊122位於積體電路晶粒114的所謂相應主動側上。保護膜124在積體電路晶粒114上並且可以在部分的接墊122上。開口貫穿保護膜124到接墊122。晶粒連接件126，例如是導電柱（舉例而言，包括銅等金屬），位於穿過保護膜124的開口中，且機械地和電性地連接到相應的接墊122。晶粒連接件126可由例如是鍍覆或其類似方法形成。晶粒連接件126電性耦合積體電路晶粒114的相應積體電路。
如圖5所示，積體電路晶粒114的晶粒連接件126（例如晶粒連接件126A和晶粒連接件126B）可以具有不同的配置。在一些實施例中，積體電路晶粒114包括短晶粒連接件126B和長晶粒連接件126A。短晶粒連接件126B允許用於隨後附接的配線晶粒（參見例如圖7A）空間，同時還將封裝結構的厚度保持為最小。長晶粒連接件126A允許積體電路晶粒114電耦合到隨後形成的前側重佈線結構131（參見例如圖10），其中配線晶粒位於積體電路晶體粒114和前側重佈線結構131之間。在一些實施例中，這些短和長的晶粒連接件可以藉由類似的製程而形成，且短晶粒連接件126B可經由額外的製程（例如是蝕刻製程）而使高度縮減。在一些實施例中，長晶粒連接件126A與短晶粒連接件126B分別由單獨的形成製程形成。舉例而言，長晶粒連接件126A可以使用第一形成製程（例如第一鍍覆程）形成。接著，在以第二形成製程（例如是第二鍍覆製程）形成短晶粒連接件126B時，可以罩幕覆蓋長晶粒連接件126A。
黏著層116位於積體電路晶粒114的背側上，並將積體電路晶粒114黏合到離型層102上。黏著層116可以是任何合適的黏著材料、環氧樹脂、晶粒貼合膜（die attach film，DAF）或其類似者。在一些實施例中，黏著層的厚度約為5 μm至約30 μm，其厚度是在垂直於各個積體電路晶粒114的背側的方向上所測量得到。黏著層116可用於積體電路晶粒114的背側，例如用於相應的半導體晶圓的背側，或者可以用於載體基底100的表面上。積體電路晶粒114可以藉由例如是鋸切（sawing）或切割（dicing）的方法而單體化，並且藉由使用取放工具（pick-and-place tool）將單體化的積體電路晶粒114藉由黏著層116而黏合到離型層102上。
在圖6中，示出了配線晶粒160。配線晶粒160可以是積體被動元件（integrated passive device，IPD）、表面安裝元件（surface mount device，SMD）、無主動和被動元件的配線晶粒、積體電路晶粒或其類似者。配線晶粒160可以使用與上述用於積體電路晶粒114的類似製程來製造。舉例而言，每一配線晶粒160包括基底162、內連線結構163和配線接墊164。基底162可以由半導體材料形成，例如是經摻雜或未經摻雜的矽或半導體上覆絕緣體基底的主動層。基底可以包括其他半導體材料，例如鍺；包括碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦及/或銻化銦的化合物半導體；包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP的合金半導體；或其組合。也可以使用其他基底，如多層基底或梯度基底。
內連線結構163由基底162上的一或多個介電層中的金屬化圖案161形成。在一些實施例中，內連線結構163經由鑲嵌及/或雙鑲嵌製程形成。在一些實施例中，內連線結構163的金屬化圖案161是具有精細間距的金屬化圖案，因此金屬化圖案的間距（例如線寬和間距）小於典型的重佈線結構。在一些實施例中，具有精細間距的金屬化圖案的線寬度在0.03 μm至約12 μm的範圍內，如約0.4 μm，並且具有細間距的金屬化圖案的線之間的間距在0.03 μm至約12 μm的範圍內，例如約0.4 μm。
在一些實施例中，配線晶粒160不含主動元件和被動元件，且用於在多個積體電路晶粒114之間配線訊號（routing signal）。在一些實施例中，例如是電晶體、二極體、電容器、電阻器件等元件可以形成在基底162中及/或基底162上，並且可以藉由內連線結構163互連以形成積體電路。
配線晶粒160更包括接墊164，如銅接墊或鋁接墊。外部連線經製造以連接接墊164。保護膜166位於配線晶粒160上並且可以位於部分的接墊164上。開口穿過保護膜166至接墊164。晶粒連接件168位於穿過保護膜166的開口中，並且機械地和電性地連接於相應的接墊164。舉例而言，晶粒連接件168例如是導電柱。導電柱例如是包括金屬（例如是銅），且具有或不具有焊料覆蓋層。舉例而言，晶粒連接件168可以藉由鍍覆或其類似方法來形成。晶粒連接件168電性耦接配線晶粒160的相應的金屬化圖案161。
在圖7A和圖7B中，配線晶粒160接合到積體電路晶粒114。在一些實施例中，配線晶粒160的晶粒連接件168接合到積體電路晶粒114的短晶粒連接件126B。在另一些實施例中，晶粒連接件168接合到金屬接墊122上，亦即短金屬接墊122上不存在短晶粒連接件126B。在一些實施例中，配線晶粒160將鄰近的積體電路晶粒114彼此電耦合，並且允許相對於僅包括前側重佈線結構（例如圖10中的前側重佈線結構131）的結構上的配線密度增加。
配線晶粒160與積體電路晶粒114的接合可為焊料接合或直接金屬對金屬接合（例如銅-銅或錫-錫接合）。在一實施例中，配線晶粒160通過回流製程接合到積體電路晶粒114上。在該回流製程中，晶粒連接件168與晶粒連接件126B接觸，以將配線晶粒160物理性地和電性地連接至積體電路晶粒114。在接合製程之後，可以在晶粒連接件126和晶粒連接件168的介面上形成介金屬化合物（intermetallic compound，IMC）（未示出）。
配線晶粒160與積體電路晶粒114接合後，配線晶粒160與距離最近的長晶粒連接件126A之間具有距離D1。在一些實施例中，距離D1大於或等於約2 μm，例如3 μm。接合的配線晶粒也具有高度H2。高度H2是從金屬接墊122到配線晶粒160的背側所量測到的距離。該高度H2小於長晶粒連接件126A的高度H1。高度H1是從金屬接墊122到晶粒連接件126A的頂部表面所量測到的距離。在一些實施例中，高度H1比高度H2至少大約3 μm，例如高度H1比高度H2大4 μm。
圖7B示出了圖7A中的結構的上視圖。如圖7B所示，可存在耦合到一對積體電路晶粒114上且位於該對積體電路晶粒114之間的多個配線晶粒160。圖7A可為沿著圖7B的線AA或線BB的剖視圖。圖7B進一步示出了每個配線晶粒160可以具有不同數量和配置的晶粒連接件168，例如2、4、6、10、20或數百個晶粒連接件168。
在圖8中，在各種構件上形成包封體130。包封體130可以是模塑化合物、環氧樹脂或其類似者，並且可以藉由應用壓塑（compression molding）、轉移模塑（transfer molding）或其類似方法來形成包封體130。包封體130可以形成在載體基底100上方，使得電性連接件112、長晶粒連接件126A和配線晶粒160被埋入或覆蓋。包封體130在配線晶粒160與其所接合的積體電路晶粒114之間延伸。在一些實施例中，包封體環繞配線晶粒160的晶粒連接件168以及積體電路晶粒114的長晶粒連接件126A與短晶粒連接件126B。接著，可固化包封體130。
在圖9中，包封體130可以經過研磨製程以暴露電性連接件112和長晶粒連接件126A。在研磨製程之後，電性連接件112、長晶粒連接件126A和包封體130的頂面表面是水平的。在一些實施例中，舉例而言，若電性連接件112和長晶粒連接件126A已經暴露出，可省略研磨製程。以下可將電性連接件112稱為穿孔112。在一些實施例中，在研磨製程之後，配線晶粒160的背側被覆蓋。在一些實施例中，至少一部分的配線晶粒160的背側在研磨製程後暴露出來。
在圖10中，形成前側重佈線結構131。前側重佈線結構131包括介電層132、介電層136、介電層140和介電層144，且包括金屬化圖案134、金屬化圖案138和金屬化圖案142。
前側重佈線結構131的形成可以始於在包封體130、穿孔112和長晶粒連接件126A上沉積介電層132。在一些實施例中，介電層132由聚合物形成，其可以是光敏材料，例如聚苯並噁唑、聚亞胺、苯並環丁烯或其類似者。上述的光敏材料可以使用微影罩幕來進行圖案化。在其他實施例中，介電層132由例如是氮化矽的氮化物；例如是氧化矽、磷矽玻璃、硼矽玻璃、硼摻雜磷矽玻璃等氧化物；或其類似者來形成。介電層132可以藉由旋轉塗佈、疊層、化學氣相沉積、其類似者或其組合來形成。
接下來，將介電層132圖案化。此圖案化形成開口以暴露穿孔112和一部分的長晶粒連接件126A。圖案化可以藉由可接受的製程來實施，例如當介電層132是光敏材料時，藉由將介電層132暴露於光線，或者藉由使用例如是非等向性蝕刻的方法來蝕刻介電層132。若介電層132是光敏材料，則可在介電層132曝光之後進行顯影。
接下來，在介電層132上形成具有通孔的金屬化圖案134。作為形成金屬化圖案134的例子，將晶種層（未示出）形成在介電層132上並且位於穿過介電層132的開口中。在一些實施例中，晶種層為金屬層，其可以是單層或包括由不同材料形成的多個子層的複合層。在一些實施例中，晶種層包括鈦層和在鈦層上的銅層。舉例而言，晶種層可以用物理氣相沉積或其類似方法形成。接著，在晶種層上形成光阻並將其圖案化。光阻可由旋轉塗佈或其類似者形成，並可暴露於光線，以進行圖案化。光阻的圖案對應於金屬化圖案134。此圖案化形成穿過光阻的開口，以暴露晶種層。導電材料形成在光阻的開口處和晶種層的暴露部分上。導電材料可以藉由鍍覆（例如是電鍍或無電鍍）或其類似方法形成。導電材料可以包括金屬，如銅、鈦、鎢、鋁或其類似者。然後，去除光阻和其上未形成導電材料的晶種層的部分。光阻可以通過可接受的灰化或剝離製程來去除，例如使用氧電漿或其類似者。一旦光阻被去除，晶種層的暴露部分也將會被去除。舉例而言，藉由使用可接受的蝕刻製程（例如濕式蝕刻或乾式蝕刻）來去除晶種層的暴露部分。晶種層的剩餘部分和導電材料構成金屬化圖案134和通孔。通孔形成於穿過介電層132的開口中，例如是暴露出穿孔112及/或長晶粒連接件126A的開口中。
可重複進行上述製程以形成介電層136和介電層140、金屬化圖案138和金屬化圖案142以及通孔，以繼續形成重佈線結構131。用於形成重佈線結構131的這些層的材料和製程可以與介電層132和金屬化圖案134和通孔的材料和製程相似，此處不再贅述。
在形成金屬化圖案142和通孔之後，在金屬化圖案142和介電層140上沉積介電層144。在一些實施例中，介電層144由聚合物形成，其可以是光敏材料，例如聚苯並噁唑、聚亞胺、苯並環丁烯或其類似者，且光敏材料可以使用微影罩幕進行圖案化。在其他實施例中，介電層144由例如是氮化矽的氮化物；例如是氧化矽、磷矽玻璃、硼矽玻璃、硼摻雜磷矽玻璃的氧化物；或其類似者來形成。介電層144可以透過旋轉塗佈、疊層、化學氣相沉積、其類似者或其組合來形成。
在圖11中，接著圖案化介電層144。此圖案化形成開口，以暴露金屬化圖案142的一部分。此圖案化可以通過可接受的製程，例如當介電層是光敏材料時，藉由將介電層144暴露於光線，或者藉由例如是非等向性蝕刻的方法來對介電層144進行蝕刻。若介電層144是光敏材料，則可在介電層144曝光之後進行顯影。
前側重佈線結構131為一範例。在前側重佈線結構131中可以形成更多或更少的介電層和金屬化圖案。若要形成更少的介電層和金屬化圖案，可省略上述的步驟和製程。若要形成更多的介電層和金屬化圖案，可重複上述討論的步驟和製程。所屬領域中具有通常知識者將容易地理解哪個步驟和製程將被省略或重複。
在一些實施例中，配線晶粒160的配線密度比前側重佈線結構131可能的配線密度大約五倍。舉例而言，前側重佈線結構的金屬化圖案131的線寬可以在約2 μm至約15 μm的範圍內，並且前側重佈線結構131的金屬化圖案的線之間的間距可以在約2 μm至約15 μm的範圍內。如上所述，配線晶粒160的線寬/間距可在0.03 μm/0.03 μm至約12 μm/12 μm的範圍內，例如是約為0.4 μm/0.4 μm。
因此，在配線晶粒的線寬和間距分別約為0.03 μm與約0.03 μm的實施例中，配線晶粒的配線密度可比前側重佈線結構131的最小配線密度大約500倍及/或比前側重佈線結構131的最大配線密度大約66倍。在配線晶粒的線寬和間距分別約為0.4 μm與約0.4 μm的實施例中，配線晶粒的配線密度可以比前側重佈線結構131的最小配線密度大約375倍及/或比前側重佈線結構131的最大配線密度大約5倍。在配線晶粒的線寬和間距分別約為12 μm與約12 μm的實施例中，配線晶粒的配線密度可比前側重佈線131的最小配線密度大約1.25倍，及/或比前側重佈線131的最大配線密度小約6倍。
再者，在圖11中，接墊150形成在前側重佈線結構131的外側上。接墊150用於耦合到導電連接件152（如圖12所示），並且可以稱為凸塊下金屬（under bump metallurgy，UBM）150。在示出的實施例中，接墊150穿過貫穿介電層144的開口至金屬化圖案142。作為形成接墊150的例子，在介電層144上形成晶種層（未示出）。在一些實施例中，晶種層是金屬層，其可以是單層或包括由不同材料形成的多個子層的複合層。在一些實施例中，晶種層包括鈦層和在鈦層上的銅層。舉例而言，晶種層可以用物理氣相沉積或其類似方法形成。接著，在晶種層上形成光阻並將其圖案化。光阻可能由旋轉塗佈或其類似方法形成，並可能暴露於光線，以進行圖案化。光阻的圖案對應於接墊150。圖案化形成穿過光阻的開口，以暴露晶種層。在光阻的開口處和晶種層的暴露部分上形成導電材料。導電材料可以藉由鍍覆（例如電鍍或無電鍍）或其類似方法來形成。導電材料可以包括金屬，如銅、鈦、鎢、鋁或其類似者。隨後，去除光阻以及其上未形成有導電材料的晶種層的部分。光阻可以藉由可接受的灰化或剝離製程來去除，例如使用氧電漿或其類似者。一旦光阻被去除，晶種層的暴露部分也將會被去除。舉例而言，透過使用可接受的蝕刻製程（例如濕式蝕刻或乾式蝕刻）去除晶種層的暴露部分。晶種層的剩餘部分和導電材料形成接墊150。在形成彼此不同的多個接墊150的實施例中，可以採用更多的光阻和圖案化步驟。
在圖12中，在凸塊下金屬150上形成導電連接件152。導電連接件152可以是球柵陣列（ball grid array，BGA）連接件、焊球、金屬柱體、受控塌陷晶片連接（controlled collapse chip connection，C4）凸塊、微凸塊、以化學鎳鈀浸金（electroless nickel-electroless palladium-immersion gold，ENEPIG）技術形成的凸塊或其類似似者。導電連接件152可以包括諸如焊料、銅、鋁、金、鎳、銀、鈀、錫、其類似者或其組合的導電材料。在一些實施例中，導電連接件152的形成方法包括先藉由蒸鍍、電鍍、印刷、焊料轉移、植球或其類似的方法形成焊料層。一旦在結構上形成了焊料層，可以進行回流，以便將材料成形為所需的凸塊形狀。另一實施例中，導電連接件152為濺鍍、印刷、電鍍、無電鍍覆、化學氣相沉積或其類似的方法形成的金屬柱體（如銅柱體）。金屬柱體可不含焊料，並具有實質上垂直的側壁。在一些實施例中，金屬覆蓋層（未示出）形成在金屬柱體導電連接件152的頂部上。金屬覆蓋層可以包括鎳、錫、錫-鉛、金、銀、鈀、銦、鎳-鈀-金、鎳-金等或其組合，並且可以藉由鍍覆製程形成。
在圖13中，進行載體基底分離（de-bonding）以將載體基底100從背側重佈線結構110（例如是介電層104）剝離（或分離）。如此一來，在每個第一封裝區600和第二封裝區602中形成第一封裝200。根據一些實施例，分離包括將諸如雷射光線或UV光線的光線投射在離型層102上，使得離型層102在光線的熱量下分解，並且可以去除載體基底100。然後將結構翻轉並放置在膠帶176上。此外，形成穿過介電層104的開口178，以暴露金屬化圖案106的一部分。舉例而言，開口178可以使用雷射鑽孔、蝕刻、或其類似的方法形成。
圖14和圖15根據一些實施例繪示在用於形成封裝結構500的製程期間的中間步驟的剖視圖。封裝結構500可以稱為疊層封裝（package-on-package，PoP）結構。
在圖14中，第二封裝300附接至第一封裝200。第二封裝300包括基底302和耦合到基底302的一或多個堆疊晶粒308（包括晶粒308A和晶粒308B）。雖然圖中繪示單一堆疊晶粒308（包括晶粒308A和晶粒308B），然而在其他實施例中可將多個堆疊晶粒308（各自具有一或多個堆疊的晶粒）並排設置且耦合到基底302的同一表面。基底302可以由諸如矽、鍺、金剛石或其類似者的半導體材料製成。在一些實施例中，基底302也可由化合物材料如矽鍺、碳化矽、砷化鎵、砷化銦、磷化銦、碳化矽、磷砷化鎵、磷化鎵銦或其組合以及其類似者製成。另外，基底302可以是絕緣體上覆半導體基底。一般而言，絕緣體上覆半導體基底包括諸如磊晶矽、鍺、矽鍺或其組合等半導體材料層。在另一實施例中，基底302是諸如玻璃纖維增強樹脂核心（fiberglass reinforced resin core）的絕緣核心（insulating core）。核心材料的一個例子是諸如FR4等級的玻璃纖維樹脂。核心材料的其他選擇包括雙馬來醯亞胺-三氮雜苯樹脂（bismaleimide-trizaine，BT）樹脂或其他印刷電路板（printed circuit board，PCB）材料或膜。例如是味之素堆積膜（Ajinomoto build-up film，ABF）的增層膜或其他層壓材料可用於基底302。
基底302可以包括主動和被動元件（未示出）。如所屬領域中具有通常知識者將認識到的，可以使用各種各樣的元件，例如電晶體、電容器、電阻器、其組合以及其類似者，以產生用於設計第二封裝300的結構和功能要求。元件可以使用任何合適的方法來形成。
基底302還可以包括金屬化層（未示出）和穿孔306。金屬化層可以形成在主動和被動元件上，並且被設計為連接各種元件以形成功能電路（functional circuitry）。金屬化層可以由介電質（例如，低介電常數介電材料）和導電材料（例如銅）的交替堆疊層形成，其中通孔互連導電材料層。此外，可以通過任何合適的製程如沉積、鑲嵌、雙鑲嵌或其類似方法形成金屬化層。在一些實施例中，基底302是實質上沒有主動和被動元件的。
基底302可以具有在基底302的第一側上的接合墊303，以耦合至堆疊晶粒308。此外，基底302更可以具有在基底302的第二側上的接合墊304，以耦合至導電連接件314。基底302的第二側相對於第一側。在一些實施例中，接合墊303與接合墊304的形成方法包括在基底302的第一側和第二側的介電層（未示出）中形成凹槽（未示出）。凹槽可經形成以允許接合墊303和接合墊304嵌入到介電層中。在其他實施例中，接合墊303和接合墊304可以形成在介電層上，故可以省略凹槽。在一些實施例中，接合墊303和接合墊304包括由銅、鈦、鎳、金、鈀、其類似者或其組合製成的薄晶種層（未示出）。接合墊303和接合墊304的導電材料可以沉積在薄晶種層上。導電材料可以通過電化學鍍覆製程、無電鍍覆製程、化學氣相沉積、原子層沉積（atomic layer deposition，ALD）、物理氣相沉積、其類似者或其組合來形成。在一實施例中，接合墊303和接合墊304的導電材料是銅、鎢、鋁、銀、金、其類似者或其組合。
在實施例中，接合墊303和接合墊304是包括三層導電材料（例如鈦層、銅層和鎳層）的凸塊下金屬。然而，所屬領域中具有通常知識者將會認識到，接合墊303和接合墊304的材料和層疊有許多合適的配置，例如鉻/鉻銅合金/銅/金的配置、鈦/鈦鎢/銅的配置或者銅/鎳/金的配置。可以用於接合墊303和接合墊304的任何合適的材料或材料層皆屬於本揭露的範疇內。在一些實施例中，穿孔306延伸穿過基底302並將至少一個接合墊303耦合於至少一個接合接合墊304。
在所示的實施例中，堆疊晶粒308藉由打線（wire bond）310與基底302耦合，但也可以使用其他連接結構，例如導電凸塊。在一實施例中，堆疊晶粒308為堆疊記憶體晶粒。舉例而言，堆疊晶粒308可以是記憶體晶粒，例如是低功率雙倍資料速率（low-power double data rate，LPDDR）記憶體模組。舉例而言，低功率雙倍資料速率記憶體模組為LPDDR1、LPDDR2、LPDDR3、LPDDR4或其類似的記憶體模組。
堆疊晶粒308和打線310可以被模塑材料312包封。模塑材料312可以使用例如是壓縮成型（compression molding）的方法模製於堆疊晶粒308和打線310上。在一些實施例中，模塑材料312是模塑化合物、聚合物、環氧樹脂、氧化矽填充材料、其類似者或其組合。模塑材料312可以執行固化步驟以固化之，其中固化可以是熱固化、UV固化、其類似者或其組合。
在一些實施例中，堆疊晶粒308和打線310被埋入模塑材料312中。此外，在模塑材料312固化之後，執行例如是研磨的平坦化步驟，以去除多餘的部分並且為第二封裝300提供實質上平坦的表面。
在形成第二封裝300後，第二封裝300經由導電連接件314、接合墊304和金屬化圖案106機械地和電性地接合到第一封裝200。在一些實施例中，堆疊晶粒308可以經由打線310、接合墊303和接合墊304、穿孔306、導電連接件314和穿孔112耦合到積體電路晶粒114。
導電連接件314可以類似於上述的導電連接件152，並且此處不再重複描述。然而，導電連接件314和導電連接件152並不需要相同。導電連接件314可以設置在基底302的相對於堆疊晶粒308的一側上，且位於開口178中。在一些實施例中，也可以在基底的相對於堆疊晶粒308的一側上形成焊料抗蝕劑（未單獨標記）。導電連接件314可以設置於焊料抗蝕劑的開口中，以電性地和機械地耦合於基底302中的導電特徵（例如，接合墊304）。焊料抗蝕劑可經使用以保護基底302的區域，以免受外部損傷。
在一些實施例中，在接合導電連接件314之前，導電連接件314塗有助焊劑（未示出），如免清洗助焊劑（no-clean flux）。導電連接件314可以浸入助焊劑中，或可以將助焊劑噴射到導電連接件314上。在另一實施例中，可以將助焊劑應用於金屬化圖案106的表面。
在一些實施例中，在對導電連接件314進行回流之前，可選擇性地在導電連接件314上形成環氧樹脂助焊劑（未示出）。在第二封裝300附接至第一封裝200之後，環氧樹脂助焊劑的至少一些部分的環氧樹脂殘留下來。
在第一封裝200和第二封裝300之間可以形成底部填充物（未示出）並且底部填充物圍繞導電連接件314。底部填充物可以減小由導電連接件314的回流導致的應力，並保護接點。在附接第一封裝200之前，可以藉由毛細流動（capillary flow）製程或適合的沉積方法形成底部填充物。在一實施例中，環氧樹脂助焊劑所形成之處可以作為底部填充物。
第二封裝300和第一封裝200之間的接合可以是焊料接合。在一實施例中，第二封裝300透過回流製程接合到第一封裝200。在該回流製程期間，導電連接件314接觸於接合墊304和金屬化圖案106，以將第二封裝300物理性地和電性地耦合到第一封裝200。在接合製程之後，在金屬化圖案106和導電連接件314的介面處，以及在導電連接件314和接合墊304之間的介面處（未示出）可以形成介金屬化合物（intermetallic compound，IMC）（未示出）。
藉由沿切割線區域（例如在第一封裝區600和第二封裝區602之間）鋸切來進行單體化製程。上述的鋸切將第二封裝區602自第一封裝區600分離。所得到的第一封裝200和第二封裝300來自於第一封裝區600或第二封裝區602的其中一者。在一些實施例中，於第二封裝300附接於第一封裝200之後才進行單體化製程。在其他實施例中（未示出），單體化製程在第二封裝300附接於第一封裝200之前（例如是在載體基底100已分離且形成開口178之後）進行。
在圖15中，使用導電連接件152將第一封裝200安裝至封裝基底400。封裝基底400可以由諸如矽、鍺、金剛石或其類似者的半導體材料製成。或者，也可以使用例如是矽鍺、碳化矽、砷化鎵、砷化銦、磷化銦、碳化矽鍺、磷化鎵砷、磷化鎵銦、其組合以及其類似者的化合物材料製成封裝基底400。另外，封裝基底400可以是絕緣體上覆半導體基底。一般而言，絕緣體上覆半導體基底包括諸如磊晶矽、鍺、矽鍺或其組合的半導體材料層。在另一實施例中，封裝基底400是諸如玻璃纖維增強樹脂核心的絕緣核心。核心材料的一個實例是諸如FR4等級的玻璃纖維樹脂。核心材料的其他選擇包括雙馬來醯亞胺-三氮雜苯樹脂（bismaleimide-trizaine，BT）樹脂或其他印刷電路板（printed circuit board，PCB）材料或膜。例如是味之素堆積膜（Ajinomoto build-up film，ABF）的增層膜或其他層壓材料可用於封裝基底400。
封裝基底400可以包括主動元件和被動元件（未示出）。如本領域普通技術人員將認識到的，可以使用各種各樣的元件，例如電晶體、電容器、電阻器、其組合以及其類似者來產生用於設計封裝結構500的結構和功能要求。上述的元件可以使用任何合適的方法形成。
封裝基底400還可以包括金屬化層和通孔（未示出）以及位於金屬化層和通孔上方的接合墊402。金屬化層可以形成在主動和被動元件之上，並被設計成連接各種元件以形成功能電路。金屬化層可以由介電質（例如，低介電常數介電材料）和導電材料（例如銅）的交替堆疊層形成，其中通孔互連導電材料層。此外，可以透過任何合適的製程如沉積、鑲嵌、雙鑲嵌或其類似方法形成金屬化層。在一些實施例中，封裝基底400實質上不包括主動和被動元件。
在一些實施例中，對導電連接件152進行回流以將第一封裝200附接到接合墊402。導電連接件152將封裝基底400電性地及/或物理性地耦合至第一封裝200。封裝基底400包括位於封裝基底400中的金屬化層。在一些實施例中，被動元件（例如，表面安裝元件（SMD），未示出）可以在安裝至封裝基底400上之前附接到第一封裝200（例如，接合到接合墊402）。在這些實施例中，被動元件可以與導電連接件152接合到第一封裝200的同一表面上。
在一些實施例中，在對導電連接件152進行回流之前，可以在導電連接件152上形成環氧樹脂助焊劑（未示出）。在第一封裝200附接至封裝基底400之後，環氧樹脂助焊劑的至少一些部分的環氧樹脂殘留下來。殘留的環氧樹脂的部分可作為底部填充物，以減小由導電連接件152的回流導致的應力，並保護接點。在一些實施例中，底部填充物（未示出）可以形成在第一封裝200和封裝基底400之間並且圍繞導電連接件152。在附接第一封裝200之前，可以藉由毛細流動（capillary flow）製程或適合的沉積方法形成底部填充物。
圖16至圖19根據某些實施例繪示另一種封裝結構的剖視圖。圖16至19中的實施例類似於圖1至15中所示的實施例，只是本實施例包括具有延伸穿過配線晶粒160的基底162的穿孔170的配線晶粒160。關於本實施例的細節相似於前述的實施例的內容，在此不再贅述。
在圖16中，配線晶粒160被示出為包括穿孔170。本實施例的關於配線晶粒160的細節類似於前述實施例中的配線晶粒160的內容，在此不再贅述。
在本實施例中，穿孔170從內連線結構163的金屬化圖案161穿過基底162延伸到基底162的背側。穿孔170可以暴露於基底162的背側，且暴露的部分可以電性耦合到上覆的導電特徵（例如，上覆的重佈線結構中的金屬化圖案）。
儘管在配線晶粒160中示出了兩個穿孔170，但應該認識到，在每個配線晶粒160中可以存在更多或更少的穿孔170。
圖17繪示如上述圖7A和圖7B所示的處理的等效中間階段，並且在此不再贅述重複的內容。在圖17中，配線晶粒160接合至積體電路晶粒114。在一些實施例中，配線晶粒160的晶粒連接件168接合至積體電路晶粒114的短晶粒連接件126B。在另一些實施例中，晶粒連接件168黏接到金屬接墊122上，使得金屬接墊122上不存在短晶粒連接件126B。在一些實施例中，配線晶粒160與相鄰的積體電路晶粒114彼此電性耦合，並將積體電路晶粒114電性耦合至上覆的導電特徵，並且允許相較於僅包括前側重佈線結構（例如圖10所示的前側重佈線結構131）的結構上的配線密度增加。
與前述的實施例類似，配線晶粒160的高度H2最初可小於長晶粒連接件126A的高度H1。在本實施例中，高度H1和高度H2之間的差異將在隨後的平坦化製程（例如，研磨包封體130）中去除，使得配線晶粒160的穿孔170、長晶粒連接件126A和穿孔112（參見例如圖18）具有齊平的頂面。在一些實施例中，配線晶粒160的高度H2最初可以與長晶粒連接件126A的高度H1大致相同，且不需要調平（leveling）就可以達到同樣的高度。
圖18繪示對於圖17的結構的進一步處理。此兩張圖所示的階段之間的處理類似於參考前述圖8至圖12所示和描述的處理，其中圖12是與圖18等效的中間階段，並且在此不再贅述重複的內容。
在圖18中，配線晶粒160的穿孔170物理性地和電性地連接到前側重佈線結構131的金屬化圖案134和通孔。穿孔170可以簡化前側重佈線結構131中的線和訊號的配線。
圖19繪示對於圖18的結構的進一步處理。此兩張圖所示的階段之間的處理類似於參考前述圖13至圖15所示和描述的處理，其中圖14是與圖19等效的中間階段，並且在此不再贅述重複的內容。
在圖19中，封裝結構500包括配有穿孔170的配線晶粒160的封裝結構200。關於本實施例的與前述實施例類似的細節在此不再贅述。
藉由在封裝結構中包括連接一個或多個晶粒的配線晶粒，可以增加封裝結構的配線密度。在一些實施例中，配線晶粒是具有精細間距的配線晶粒，使得配線的間距（例如線寬和線間距）小於典型重佈線結構的間距。配線晶粒可以是積體被動元件（IPD）、表面安裝元件（SMD）、無主動元件和被動元件的配線晶粒、積體電路晶粒或其類似者。配線晶粒可以與一個或多個晶粒面對面地接合。另外，配線晶粒可以與一個或多個晶粒封裝在相同的包封體中。在一些實施例中，包含一個或多個晶粒和配線晶粒的封裝的前側重佈線結構可以覆蓋配線晶粒鰭，使得配線晶粒位於一個或多個晶粒與前側重佈線結構之間。本揭露的實施例可以包括配線晶粒，其配線密度可比典型重佈線結構的配線密度高66倍。此外，包含配線晶粒的封裝結構與其他封裝結構相比，可以減少翹曲，而且，與另一個欲在重佈線結構中達到相似的配線密度封裝結構相比，可以以節省製造時間。
在一實施例中，半導體封裝包括第一封裝結構。所述第一封裝結構包括：第一積體電路晶粒，具有主動側和背側，所述第一積體電路晶粒的所述主動側包括晶粒連接件；第二積體電路晶粒，相鄰於所述第一積體電路晶粒，所述第二積體電路晶粒具有主動側和背側，所述第二積體電路晶粒的所述主動側包括晶粒連接件；配線晶粒，接合至所述第一積體電路晶粒與所述第二積體電路晶粒，所述配線晶粒具有前側與背側，所述配線晶粒的所述前側包括晶粒連接件，所述配線晶粒的所述晶粒連接件接合至所述第一積體電路晶粒與所述第二積體電路晶粒的所述主動側，所述配線晶粒將所述第一積體電路晶粒電性耦合至所述第二積體電路晶粒；包封體，包封所述第一積體電路晶粒、所述第二積體電路晶粒和所述配線晶粒；以及第一重佈線結構，位於所述第一積體電路晶粒與所述第二積體電路晶粒的所述晶粒連接件上且電性連接至所述第一積體電路晶粒與所述第二積體電路晶粒的所述晶粒連接件，所述配線晶粒位於所述第一重佈線結構與所述第一積體電路晶粒之間以及所述第一重佈線結構與所述第二積體電路晶粒之間。
實施例可能包括以下一項或多項特徵。所述第一封裝結構更包括：第一穿孔，相鄰於所述第一積體電路晶粒，所述第一穿孔延伸穿過所述包封體。半導體封裝，更包括：第二封裝結構，經由第一組導電連接件接合至所述第一穿孔。所述第一封裝結構更包括：第二重佈線結構，位於所述第一穿孔上且電性連接於所述第一穿孔，所述第二重佈線結構位於所述第一積體電路晶粒與所述第二封裝結構之間。半導體封裝，更包括：封裝基底，經由第二組導電連接件接合至所述第一封裝結構的所述第一重佈線結構。所述包封體延伸於所述配線晶粒與所述第一積體電路晶粒之間以及所述配線晶粒與所述第二積體電路晶粒之間，所述包封體圍繞所述配線晶粒的所述晶粒連接件。所述包封體延伸於所述配線晶粒與所述第一重佈線結構之間。所述配線晶粒包括：基底；內連線結構，位於所述基底上，所述內連線結構包括位於一或多個介電層中的金屬化圖案；以及晶粒連接件，電性耦合至所述內連線結構的所述金屬化圖案。所述配線晶粒更包括延伸穿過所述基底的穿孔，所述配線晶粒的所述穿孔物理性地和電性地連接至所述第一重佈線結構。所述配線晶粒包括主動元件或被動元件。所述配線晶粒實質上不包括主動元件和被動元件。
在一個實施例中，一種半導體封裝的形成方法包括：形成第一封裝，所述形成所述第一封裝的步驟包括：在載體基底上形成電性連接件；使用黏著層而將第一晶粒的背側附接到所述載體基底上，所述第一晶粒相鄰於所述電性連接件；使用黏著層而將第二晶粒的背側附接到所述載體基底上，所述第二晶粒相鄰於所述第一晶粒；藉由使用位於所述配線晶粒上的晶粒連接件將配線晶粒接合至所述第一晶粒與所述第二晶粒的主動側，所述配線晶粒電性耦合所述第一晶粒與所述第二晶粒；以模塑化合物包封所述第一晶粒、所述第二晶粒、所述配線晶粒以及所述電性連接件；在所述第一晶粒、所述第二晶粒、所述配線晶粒、所述模塑化合物和所述電性連接件上形成第一重佈線結構；以及去除所述載體基底；以及使用第一組導電連接件將所述第二封裝接合到所述第一封裝，所述第二封裝接近所述第一晶粒和所述第二晶粒的所述背側。
實施例可能包括以下一項或多項特徵。所述的半導體封裝的形成方法，更包括：在所述第一晶粒和所述第二晶粒的所述背側上以及在所述電性連接件的第一端上形成第二重佈線結構，所述第二重佈線結構電性連接到所述電性連接件，所述第二封裝接合到所述第二重佈線結構。所述模塑化合物延伸於所述配線晶粒與所述第一晶粒之間以及所述配線晶粒和所述第二晶粒之間，所述模塑化合物圍繞所述配線晶粒的所述晶粒連接件。所述模塑化合物在所述配線晶粒和所述第一重佈線結構之間延伸。所述的半導體封裝的形成方法，更包括：平坦化所述模塑化合物，在所述第一晶粒與所述第二晶粒的主動側上的所述晶粒連接件以及所述電性連接件具有齊平的表面。所述配線晶粒包括：基底；內連線結構，位於所述基底上，所述內連線結構包括位於一或多個介電層中的金屬化圖案；穿孔，延伸穿過所述基底，所述穿孔物理性地和電性地連接到所述第一重佈線結構；以及晶粒連接件，電性連接到所述內連線結構的所述金屬化圖案。
在實施例中，一種半導體封裝的形成方法包括：形成第一封裝，所述形成所述第一封裝的步驟包括：在載體基底上形成電性連接件；將第一晶粒黏著至所述載體基底，所述第一晶粒的主動側包括第一組晶粒連接件以及第二組晶粒連接件，所述主動側相對於背側，所述第一晶粒相鄰於所述電性連接件；將第二晶粒黏著到所述載體基底，所述第二晶粒的主動側包括第三組晶粒連接件和第四組晶粒連接件，所述主動側相對於背側，所述第二晶粒相鄰於所述第一晶粒；使用所述第一組晶粒連接件和所述第三組晶粒連接件將配線晶粒接合至所述第一晶粒和所述第二晶粒上；使用模塑化合物包封所述第一晶粒、所述第二晶粒、所述配線晶粒和所述電性連接件；形成重佈線結構，所述重佈線結構上覆所述第一晶粒的所述主動側、所述模塑化合物和所述電性連接件，所述重佈線結構電性連接到所述第二組晶粒連接件、所述第四組晶粒連接件以及所述電性連接件；以及去除所述載體基底；以及使用第一組導電連接件將第二封裝接合到所述第一封裝，所述第二封裝接近所述配線晶粒的背側。
以上概述了若干實施例的特徵，以使熟習此項技術者可更佳地理解本揭露的各個態樣。熟習此項技術者應知，其可容易地使用本揭露作為設計或修改其他製程及結構的基礎來施行與本文中所介紹的實施例相同的目的及/或達成與本文中所介紹的實施例相同的優點。熟習此項技術者亦應認識到，該些等效構造並不背離本揭露的精神及範圍，而且他們可在不背離本揭露的精神及範圍的條件下對其作出各種改變、代替、及變更。
100‧‧‧載體基底
102‧‧‧離型層
104、108、132、136、140、144‧‧‧介電層
106、161、134、138、142‧‧‧金屬化圖案
110‧‧‧背側重佈線結構
112‧‧‧電性連接件/穿孔
114‧‧‧積體電路晶粒
116‧‧‧黏著層
118‧‧‧半導體基底
120、163‧‧‧內連線結構
122、164‧‧‧接墊
124‧‧‧保護膜
126、126A、126B、168‧‧‧晶粒連接件
130‧‧‧包封體
131‧‧‧前側重佈線結構
150‧‧‧接墊/凸塊下金屬
152、314‧‧‧導電連接件
160‧‧‧配線晶粒
162、302‧‧‧基底
166‧‧‧保護膜
170、306‧‧‧穿孔
176‧‧‧膠帶
178‧‧‧開口
200‧‧‧第一封裝
300‧‧‧第二封裝
303、304、402‧‧‧接合墊
308‧‧‧堆疊晶粒
308A、308B‧‧‧晶粒
310‧‧‧打線
312‧‧‧模塑材料
400‧‧‧封裝基底
500‧‧‧封裝結構
600‧‧‧第一封裝區
602‧‧‧第二封裝區
D1‧‧‧距離
H1、H2‧‧‧高度
結合附圖閱讀以下詳細說明，會最佳地理解本發明實施例的各個態樣。應注意，根據本行業中的標準慣例，各種特徵並非按比例繪製。事實上，為論述清晰起見，可任意增大或減小各種特徵的尺寸。 　　圖1至圖15根據一些實施例繪示在用於形成封裝結構的製程期間的中間步驟的剖視圖和上視圖。 　　圖16至圖19根據一些實施例繪示在用於形成封裝結構的製程期間的中間步驟的剖視圖。

Claims (20)

  1. 一種半導體封裝，包括： 第一封裝結構，包括 第一積體電路晶粒，具有主動側和背側，所述第一積體電路晶粒的所述主動側包括晶粒連接件； 第二積體電路晶粒，相鄰於所述第一積體電路晶粒，所述第二積體電路晶粒具有主動側和背側，所述第二積體電路晶粒的所述主動側包括晶粒連接件； 配線晶粒，接合至所述第一積體電路晶粒與所述第二積體電路晶粒，所述配線晶粒具有前側與背側，所述配線晶粒的所述前側包括晶粒連接件，所述配線晶粒的所述晶粒連接件接合至所述第一積體電路晶粒與所述第二積體電路晶粒的所述主動側，所述配線晶粒將所述第一積體電路晶粒電性耦合至所述第二積體電路晶粒； 包封體，包封所述第一積體電路晶粒、所述第二積體電路晶粒和所述配線晶粒；以及 第一重佈線結構，位於所述第一積體電路晶粒與所述第二積體電路晶粒的所述晶粒連接件上，且電性連接至所述第一積體電路晶粒與所述第二積體電路晶粒的所述晶粒連接件，所述配線晶粒位於所述第一重佈線結構與所述第一積體電路晶粒之間以及所述第一重佈線結構與所述第二積體電路晶粒之間。
  2. 如申請專利範圍第1項所述的半導體封裝，其中所述第一封裝結構更包括： 第一穿孔，相鄰於所述第一積體電路晶粒，所述第一穿孔延伸穿過所述包封體。
  3. 如申請專利範圍第2項所述的半導體封裝，更包括： 第二封裝結構，經由第一組導電連接件接合至所述第一穿孔。
  4. 如申請專利範圍第3項所述的半導體封裝，其中所述第一封裝結構更包括： 第二重佈線結構，位於所述第一穿孔上且電性連接於所述第一穿孔，所述第二重佈線結構位於所述第一積體電路晶粒與所述第二封裝結構之間。
  5. 如申請專利範圍第3項所述的半導體封裝，更包括： 封裝基底，經由第二組導電連接件接合至所述第一封裝結構的所述第一重佈線結構。
  6. 如申請專利範圍第1項所述的半導體封裝，其中所述包封體延伸於所述配線晶粒與所述第一積體電路晶粒之間以及所述配線晶粒與所述第二積體電路晶粒之間，所述包封體圍繞所述配線晶粒的所述晶粒連接件。
  7. 如申請專利範圍第1項所述的半導體封裝，其中所述包封體延伸於所述配線晶粒與所述第一重佈線結構之間。
  8. 如申請專利範圍第1項所述的半導體封裝，其中所述配線晶粒包括： 基底； 內連線結構，位於所述基底上，所述內連線結構包括位於一或多個介電層中的金屬化圖案；以及 晶粒連接件，電性耦合至所述內連線結構的所述金屬化圖案。
  9. 如申請專利範圍第8項所述的半導體封裝，其中所述配線晶粒更包括延伸穿過所述基底的穿孔，所述配線晶粒的所述穿孔物理性地和電性地連接至所述第一重佈線結構。
  10. 如申請專利範圍第1項所述的半導體封裝，其中所述配線晶粒包括主動元件或被動元件。
  11. 如申請專利範圍第1項所述的半導體封裝，其中所述配線晶粒實質上不包括主動元件和被動元件。
  12. 一種半導體封裝的形成方法，包括： 形成第一封裝，包括： 在載體基底上形成電性連接件； 使用黏著層而將第一晶粒的背側附接到所述載體基底上，所述第一晶粒相鄰於所述電性連接件； 使用黏著層而將第二晶粒的背側附接到所述載體基底上，所述第二晶粒相鄰於所述第一晶粒； 藉由使用位於所述配線晶粒上的晶粒連接件將配線晶粒接合至所述第一晶粒與所述第二晶粒的主動側，所述配線晶粒電性耦合所述第一晶粒與所述第二晶粒； 以模塑化合物包封所述第一晶粒、所述第二晶粒、所述配線晶粒以及所述電性連接件； 在所述第一晶粒、所述第二晶粒、所述配線晶粒、所述模塑化合物和所述電性連接件上形成第一重佈線結構；以及 去除所述載體基底；以及 使用第一組導電連接件將所述第二封裝接合到所述第一封裝，所述第二封裝接近所述第一晶粒和所述第二晶粒的所述背側。
  13. 如申請專利範圍第12項所述的半導體封裝的形成方法，更包括： 在所述第一晶粒和所述第二晶粒的所述背側上以及在所述電性連接件的第一端上形成第二重佈線結構，所述第二重佈線結構電性連接到所述電性連接件，所述第二封裝接合到所述第二重佈線結構。
  14. 如申請專利範圍第12項所述的半導體封裝的形成方法，其中所述模塑化合物延伸於所述配線晶粒與所述第一晶粒之間以及所述配線晶粒和所述第二晶粒之間，所述模塑化合物圍繞所述配線晶粒的所述晶粒連接件。
  15. 如申請專利範圍第12項所述的半導體封裝的形成方法，其中所述模塑化合物在所述配線晶粒和所述第一重佈線結構之間延伸。
  16. 如申請專利範圍第12項所述的半導體封裝的形成方法，更包括： 平坦化所述模塑化合物，在所述第一晶粒與所述第二晶粒的主動側上的所述晶粒連接件以及所述電性連接件具有齊平的表面。
  17. 如申請專利範圍第12項所述的半導體封裝的形成方法，其中所述配線晶粒包括： 基底； 內連線結構，位於所述基底上，所述內連線結構包括位於一或多個介電層中的金屬化圖案； 穿孔，延伸穿過所述基底，所述穿孔物理性地和電性地連接到所述第一重佈線結構；以及 晶粒連接件，電性連接到所述內連線結構的所述金屬化圖案。
  18. 一種半導體封裝的形成方法，包括： 形成第一封裝，包括： 在載體基底上形成電性連接件； 將第一晶粒黏著至所述載體基底，所述第一晶粒的主動側包括第一組晶粒連接件以及第二組晶粒連接件，所述主動側相對於背側，所述第一晶粒相鄰於所述電性連接件； 將第二晶粒黏著到所述載體基底，所述第二晶粒的主動側包括第三組晶粒連接件和第四組晶粒連接件，所述主動側相對於背側，所述第二晶粒相鄰於所述第一晶粒； 使用所述第一組晶粒連接件和所述第三組晶粒連接件將配線晶粒接合至所述第一晶粒和所述第二晶粒上； 使用模塑化合物包封所述第一晶粒、所述第二晶粒、所述配線晶粒和所述電性連接件； 形成重佈線結構，所述重佈線結構上覆所述第一晶粒的所述主動側、所述模塑化合物和所述電性連接件，所述重佈線結構電性連接到所述第二組晶粒連接件、所述第四組晶粒連接件以及所述電性連接件；以及 去除所述載體基底；以及 使用第一組導電連接件將第二封裝接合到所述第一封裝，所述第二封裝接近所述配線晶粒的背側。
  19. 如申請專利範圍第18項所述的半導體封裝的形成方法，其中所述第一晶粒和所述第二晶粒的所述第二組晶粒連接件和所述第四組晶粒連接件相鄰於所述配線晶粒，並從所述配線晶粒的前側延伸到所述配線晶粒的所述背側。
  20. 如申請專利範圍第18項所述的半導體封裝的形成方法，其中所述第二組晶粒連接件和所述第四組晶粒連接件的晶粒連接件具有第一高度，並且其中所述配線晶粒具有第二高度，所述第一高度大於所述第二高度。
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