CN103426846A - 晶圆级封装机构 - Google Patents

晶圆级封装机构 Download PDF

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CN103426846A
CN103426846A CN2012103876047A CN201210387604A CN103426846A CN 103426846 A CN103426846 A CN 103426846A CN 2012103876047 A CN2012103876047 A CN 2012103876047A CN 201210387604 A CN201210387604 A CN 201210387604A CN 103426846 A CN103426846 A CN 103426846A
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tube core
moulding compound
layer
semiconductor element
rdl
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CN103426846B (zh
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林俊成
洪瑞斌
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明涉及晶圆级封装机构。形成再分布线(RDL)之前，在上述晶圆级封装(WLP)机构的实施例中，利用平坦化停止层来确定去除多余模塑料的终点。利用这种WLP机构来实现扇出和多芯片封装。这种机构也可用于制造含有不同类型的外部连接的芯片(或管芯)封装。例如，具有预先设定凸块的管芯可以和没有预先设定凸块的管芯封装在一起。

Description

晶圆级封装机构
相关申请的交叉参考
本申请要求于2012年5月18日提交的美国临时专利申请第61/649,174号的优先权，其全部内容结合于此作为参考。
本申请涉及下列同时待审且共同转让的专利申请：于2010年9月13日提交的第12/880,736号标题为“嵌入式晶圆级接合方法”(代理案号TSMC2010-0667)以及于2012年4月20日提交的第13/452,140号标题为“多芯片扇出(fan out)封装件及其形成方法”(代理案号TSMC2012-0045)，其全部内容结合于此作为参考。
技术领域
本发明总体上涉及半导体领域，更具体地，涉及晶圆级封装机构。
背景技术
随着半导体技术的不断发展，半导体芯片/管芯变得越来越小。同时，半导体管芯集成了更多的功能。因此，在半导体芯片的较小面积内，可以堆叠越来越多的输入/输出(I/O)焊盘。所以，在封装半导体管芯时会更加困难，进而也对封装件的产量带来不利影响。
常规的封装技术可以分为两大类。第一大类，进行锯切之前，晶圆上的管芯是被封装的。这种封装技术具有一些优点，如高产出和低成本。此外，仅需要较少的底层填料或模塑料。但是，这种封装技术也有一些缺点。如上所述，管芯的尺寸变得越来越小，相应的封装件只能是扇入式封装件，其中，每个管芯的I/O焊盘直接被限制在相应管芯的表面上方的区域内。在管芯的有限区域内，由于限定了I/O焊盘的节距，所以I/O焊盘的数量也被限制。如果焊盘节距变小，可能会出现焊料桥接(solder bridging)。此外，根据固定的球尺寸要求，必须预先设定焊料球的尺寸，进而限制可被封装在管芯表面上的焊料球数量。
封装技术的第二大类，封装管芯之前，先从晶圆上锯切管芯，而只封装合格管芯。这种封装技术的优点在于有可能形成扇出封装件，这就意味着可以将管芯上的I/O焊盘重新分布在比管芯面积更大的区域里，因此，能够增加封装在管芯表面上的I/O焊盘数量。
发明内容
为解决上述问题，本发明提供了一种半导体封装件，包括：第一半导体管芯，被模塑料包围；第一半导体管芯的第一导电焊盘，其中，该导电焊盘位于第一半导体管芯的顶部金属平面上；以及再分布线(RDL)，形成在第一导电焊盘的上方，其中，RDL延伸超出半导体管芯的边界，RDL的一部分与第一导电焊盘接触，其中，第一导电焊盘与RDL的一部分接触的表面与延伸超出第一半导体管芯的边界的RDL下方的模塑料的表面处于不同的平面。
其中，RDL通过至少一个导电插塞与第一导电焊盘接触。
其中，第一导电焊盘的表面与模塑料的表面之间的高度差值在大约5μm到大约100μm之间的范围内。
该半导体封装件进一步包括：第二半导体管芯，第二半导体管芯包括柱形凸块，柱形凸块位于第二半导体管芯上方的第二导电焊盘之上。
其中，柱形凸块的表面与模塑料的表面基本处于同一平面。
其中，柱形凸块由包括铝、铜、铝铜合金、或它们的组合的材料制成。
其中，第二半导体管芯的输入/输出(I/O)的数量少于第一半导体管芯的输入/输出(I/O)的数量。
其中，模塑料的表面基本平坦。
其中，模塑料包围柱形凸块。
此外，本发明还提供了一种形成半导体封装件的方法，包括：提供其上布置有粘结层的载体；提供包括衬底的管芯，其中，多个接合焊盘形成在衬底的上方，并且平坦化停止层形成在多个接合焊盘的上方；将管芯放置在粘结层上；形成模塑料以覆盖管芯，其中，模塑料包围管芯；平坦化模塑料，直到露出平坦化停止层；去除平坦化停止层；以及在管芯的上方形成再分布线，其中，再分布线电连接至多个接合焊盘中的至少一个。
其中，平坦化停止层的厚度在大约5μm到大约100μm之间的范围内。
其中，在执行平坦化模塑料的过程中，平坦化停止层的第一平坦化率低于模塑料的第二平坦化率。
其中，通过使用平坦化工具检测阻抗变化来确定执行平坦化模塑料的终点，其中，由于平坦化停止层与模塑料相比较低的杨氏模量而引起阻抗变化。
其中，采用旋涂工艺将平坦化停止层形成在多个接合焊盘的上方。
该方法进一步包括：在形成再分布线之前，形成导电插塞以与多个接合焊盘中的至少一个接触，其中，再分布线的一部分与导电插塞接触。
其中，再分布线延伸超出管芯的边界。
该方法进一步包括：提供另一管芯，其中，另一管芯包括多个柱形凸块，形成于另一管芯的接合焊盘上方；以及在粘结层上放置另一管芯。
其中，多个柱形凸块由包括铝、铜、铝铜合金、或它们的组合的材料制成。
其中，在将另一管芯放置在粘结层上之前，在另一管芯的接合焊盘的上方形成柱形凸块。
此外，还提供了一种形成半导体封装件的方法，包括：提供其上布置有粘结层的载体；提供包括第一衬底的第一管芯，其中，多个第一接合焊盘形成在衬底的上方，并且平坦化停止层形成在多个第一接合焊盘的上方；在粘结层上放置第一管芯；提供包括第二衬底的第二管芯；在粘结层上放置第二管芯；在第二管芯的多个第二接合焊盘的上方形成柱形凸块；形成模塑料，以覆盖第一管芯和第二管芯，其中，模塑料包围第一管芯和第二管芯；平坦化模塑料，直到露出平坦化停止层；去除平坦化停止层；以及在第一管芯和第二管芯的上方形成再分布线，其中，再分布线电连接至多个第一接合焊盘中的至少一个和多个第二接合焊盘中的至少一个。
附图说明
为了更全面地理解实施例及其优点，现将结合附图作为参考来进行如下描述，其中：
图1-图10示出了根据不同实施例的在不同的制造阶段的晶圆级封装件的截面图。
图11示出了根据一些实施例的在衬底上的具有柱形凸块(stud bump)的管芯的截面图。
图12示出了根据一些实施例的封装截面图。
具体实施方式
下面，详细讨论本发明各实施例的制造和使用。然而，应该理解，这些实施例提供了许多可以在各种具体环境中实现的可应用的概念。所讨论的具体实施例仅仅示出了制造和使用本发明的具体方式，而不用于限制本发明的范围。
根据一个或多个实施例提供了一种新式嵌入式晶圆级封装结构及其形成方法。示出了根据一个或多个实施例的制造封装结构的中间步骤。同时也讨论了一个或多个实施例的变化。所有的不同视图和给出的实施例中，相同的参考数字用于表示相同的元件。
图1示出了根据一些示例性实施例的管芯120的截面图。晶圆100包括多个管芯120(也称之为芯片)。此外，晶圆100(和晶圆100中的管芯120)可以包括半导体衬底121，也可以包括集成电路器件123以及上覆盖互连结构116。集成电路器件123包括有源器件，如晶体管。在一些示例性实施例中，互连结构116包括金属线和形成在介电层117中的通孔118。介电层117包括低介电常数(低k)介电层，例如，其介电常数值(k值)小于大约3.0，而钝化层位于低k介电层的上方。导电焊盘122形成在管芯120的顶面，且通过互连结构116电连接至集成电路器件123。在一些实施例中，导电焊盘122是接合焊盘(bond pad)。导电焊盘122包括金属，如铝、铜、镍、金、或其组合。
如图1所示，平坦化停止层125形成在管芯120的顶面上且覆盖导电焊盘122。在平坦化过程中，平坦化停止层125起到保护管芯120的作用，下文会给出详细介绍。在一些实施例中，平坦化停止层125的厚度H1的取值范围介于大约5μm到大约100μm之间。
沿着划线129锯切晶圆100，使得管芯120相互分离。对准标记(未示出)可以形成在靠近管芯120的顶面，且从上往下俯视时该对准标记可见。
参见图2，粘结层(adhesive layer)28布置(例如，叠压)在载体30上。粘结层28可能由胶粘剂形成，或可能是由金属箔形成的叠合层。然后将管芯120放置在载体30上且粘附于粘结层(adhesive layer)28。在一些实施例中，管芯120包括半导体衬底121的对应部分，且半导体衬底121的底面21b与粘结层28相接触。载体30包括对准标记(未示出)，所以管芯120能够被准确地安装在载体30的理想位置上。将管芯120安装在载体30上之前，先测试管芯120以确定哪个管芯是劣质管芯。只有优质管芯才可以安装在载体30上。
图2还示出了管芯220在粘结层28上的布置，其中，管芯220可以彼此相同。将管芯220安装在载体30上之前，也要对管芯220进行测试以保证只有优质管芯安装在载体30上。根据一些实施例，管芯220是器件管芯，其包括有源器件，如，相应半导体衬底221的表面上的晶体管223。在一些实施例中，导电焊盘222形成在管芯220的顶面上。导电焊盘222可以包括金、铝、铜、镍、或其组合。与管芯120相似的，平坦化停止层225也覆盖在管芯220的顶面。管芯220的结构可以不同于管芯120的结构，二者结构的差别可以包括其结构内形成的电路的差别、顶视图尺寸的差别、以及高度的差别等。在一些实施例中，管芯220可以由不同于晶圆100的尺寸的晶圆构成(如图1)。相邻的管芯120和220之间存在间隙31。当从顶视图观测时，间隙31会形成将管芯120和220围起来的栅栏。
如图3所示，根据一些实施例，管芯120和220放置在载体20上之后，聚合物34填充管芯120和220之间的间隙。在一些示例性实施例中，聚合物34是一种模塑料，因此也称之为模塑料34，当然，除了是模塑料外，聚合物34也可能是其他材料。例如，聚合物34由其他介电材料构成，如模制底层填料(molding underfill)、环氧树脂等。然后进行固化工艺，以固化模塑料34。
参见图4，对模塑料34进行平坦化，如进行磨削操作，直到露出平坦化停止层125和225。因此，平坦化停止层125的顶面125a和平坦化停止层225的顶面225a基本上在同一平面上且大致平坦。在一些实施例中，平坦化停止层125和225在形式上是液态的，如糊剂或胶粘剂。在一些实施例中，液态的平坦化停止层125和/或225通过旋转涂布进行沉积。在一些实施例中，平坦化停止层125和225是固态的。在一些实施例中，通过沉积工艺，如化学气相沉积(CVD)形成固态的平坦化停止层125和/或225。
平坦化停止层125和225的硬度明显地低于模塑料34的硬度。例如，模塑料34的杨氏模量(硬度测量)的范围介于大约10GPa到大约30GPa的范围内，而平坦化停止层125和225的杨氏模量小于大约5GPa。在一些实施例中，平坦化停止层125和225的杨氏模量小于大约0.1GPa。在平坦化模塑料34的过程中，当露出平坦化停止层125和225中的一个或两个时，由于平坦化停止层125和/或225以及模塑料34的杨氏模量(反映硬度)不同，所以平坦化工具如削磨机检测到的阻抗也会不同。平坦化工具检测到的不同阻抗可用以确定平坦化工艺的终点。
在一些实施例中，在平坦化过程中，平坦化停止层125和/或225的去除率大致小于模塑料34的去除率。在一些实施例中，模塑料34的去除率和平坦化停止层125或225的去除率的比率等于或大于大约1.3。在一些实施例中，上述两者的比率等于或大于大约2。在一些实施例中，上述两者的比率等于或大于大约3。模塑料34的平坦化率和平坦化停止层125和/或225的平坦化率的差别有助于确定平坦化工艺的终点。
在一些实施例中，平坦化停止层125和225是由聚合物制成，如环氧树脂等。在一些实施例中，平坦化停止层125或225的厚度范围介于大约5μm至100μm之间。在一些实施例中，具有平坦化停止层125的管芯120的总厚度H120(见图2)和具有平坦化停止层225的管芯220的总厚度H220(见图2)大致相同。
接下来，如图5所示，根据一些实施例，去除平坦化停止层125和225。通过采用不同的方法，如蚀刻工艺(可以是干式工艺或湿式工艺)或剥离工艺去除层125和225。例如，层125和/或225可以由紫外线(UV)胶带构成，在其在UV光下曝光后，层125和/或225不粘附于表面。在UV光下曝光后，可剥离掉衬底30表面上的层125和/或225。在一些实施例中，如果层125和/或225是液态的，则使用化学溶剂去除层125和/或225。
根据一些实施例，如图5所示，因为去除平坦化停止层125和225，所以导电焊盘122和222的表面122a和222a分别低于模塑料34的表面34a。在一些实施例中，高度差H2的范围介于大约5μm至100μm之间。
然后，如图6所示，根据一些实施例，导电插塞126和226分别形成于导电焊盘122和222的上方。根据一些实施例，为了形成导电插塞126和226，所以形成介电层124以填充之前被层125和225占用的间隙。在一些实施例中，介电层124在模塑料34的上方延伸。介电层24的材料可选自可定光阻焊剂(photo-definable solder resists)、聚合物(如聚酰亚胺)、聚苯并恶唑(PBO)、苯并环丁烯(BCB)、和模塑料等。介电层124采用软材料以吸收球安装工艺所产生的压力，下文会详细介绍。然后，在一些实施例中，图案化介电层124以形成导电插塞126和226的插塞开口。然后，用导电材料填充插塞开口，以形成导电插塞126和226。在一些实施例中，填充插塞开口包括电镀金属(如铜)，然后例如通过化学机械抛光(CMP)工艺去除插塞开口外侧的多余金属。
在上述的工艺流程中，利用平坦化停止层125或/和225来确定对模塑料34进行平坦化工艺的终点。在一些晶圆级封装(WLP)技术中，在晶圆上的介电层中形成铜插塞(或铜柱)之后再锯切管芯。这样的铜插塞可以用作平坦化停止。
然后，如图7所示，根据一些实施例，再分布线(RDL)40形成在管芯120和220的上方，且连接至导电插塞126和226。根据一些实施例，RDL 40的形成包括：采用诸如物理气相沉积(PVD)的方法沉积导电层；图案化导电层；以及蚀刻导电层。之后，在RDL 40的上方形成介电层38，以覆盖RDL 40的一部分，然后露出剩余部分。介电层38的材料可选自可定光阻焊剂(photo-definable solder resists)、聚合物(如聚酰亚胺)、聚苯并恶唑(PBO)、苯并环丁烯(BCB)和模塑料等。介电层124采用软材料以吸收球安装过程中所产生的压力，下文会进行详细介绍。
在可选的实施例中，RDL 40的形成方法包括波形花纹(damascene)工艺。RDL 40形成在介电层38中，且包括金属线和通孔。在一些实施例中，RDL 40延伸超出了相应管芯120和220的边缘且覆盖填充在管芯120和220之间的模塑料34的部分。因此，最终封装件是扇出封装件。在一些实施例中，RDL 40包括铜和/或铜合金。RDL 40也可包括铜阻挡层，以防止RDL 40中的铜与周围介电层直接接触。
图8示出了根据一些实施例的电连接至RDL 40的电连接件42的形成。因此，电连接件42位于新形成的晶圆44(RDL 40的露出的表面)的顶面上。电连接件42可以是通过使用球状安装头(未示出)将其转移到晶圆44上的锡球。在一些可选的实施例中，电连接件42可以包括铜凸块(或铜柱)。在一些实施例中，在RDL 40和该电连接件42之间形成凸块底部金属化层(UBM)43。UBM层43可包括子层。例如，如果RDL 40由铝制成，就可以使用具有钛子层(扩散层)和铜子层(晶种层)的UBM层43。钛子层用作阻挡层，而铜子层用作晶种层，用于电镀铜凸块(作为连接件42)。
一些电连接件42形成在管芯120和220之上且与之对准，而其他的电连接件42也可以形成在模塑料34之上并与之对准，并且与管芯120和220之间的间隙对准。RDL 40启用在管芯120和220的边界外形成电连接件42的步骤。如上所述，管芯边界外的连接件构成扇出封装件的一部分。
接着，如图9所示，根据一些实施例，从晶圆44上卸掉载体30，同时还可以去除粘结层28，剩下晶圆44。然后，晶圆44粘附在胶带46上，接着沿划线48将两者锯切开。因此，形成封装件50。
图10示出了一个示例性封装件50。应该了解，在每个封装件50中，管芯120的底面120b和管芯220的底面220b基本上与模塑料34的底面34b在同一平面上。此外，管芯120的底面120b也可以是衬底121的底面121b，且管芯220的底面220b也是衬底221的底面221b。因此，衬底121的底面121b和衬底221的底面221b与模塑料34的底面34b在同一平面上。从上面的角度来看，RDL 40形成于导电插塞126和226的上方且与之电连接。此外，RDL 40在填充管芯120和220之间间隙的部分模塑料34的上方延伸。由此，封装件50是扇出封装件。
根据一些实施例，图1-图10示出了封装件50的形成，其中，封装件50包括互不相同的管芯120和220。在一些实施例中，管芯120和220是相同的。如图11所示，在一些可选的实施例中，多个管芯220’布置在粘结层(adhesive layer)28上。然后，在管芯220的上方形成柱形凸块226’。在一些实施例中，先在管芯220上形成柱形凸块226’，然后再将管芯220放置在粘结层28上。柱形凸块226’可以由铝、铜、金、焊料、其合金、或其组合制成。根据一些实施例，平坦化层没有覆盖管芯220’。如图11所示，使用模塑料34覆盖管芯120和220’。根据一些实施例，具有平坦化停止层125的管芯120的总高度H120低于管芯220’的总高度H220’。柱形凸块226’用作平坦化停止(用于确定平坦化工艺中的终点)。在一些实施例中，在露出柱形凸块226’的顶面后，在固定的时间内可以采用附加平坦化以露出平坦化停止层125的顶面。在其他可选的实施例中，H120高于H220’，且平坦化停止层125用于确定平坦化操作的终点。根据一些实施例，在露出平坦化停止层125的顶面后，在固定的时间内采用附加平坦化，以露出柱形凸块226’的顶面。
如图12所示，根据一些实施例，为了完成封装件50’的形成，除了用柱形凸块226’代替导电插塞226之外，下列处理操作与图3-10所示的操作相似。
上述的实施例中，每个封装件包括两个管芯。但是，可以采用上述封装机制来封装各种管芯的组合。例如，每个封装件中只能有一个管芯。在一些可选的实施例中，一个封装件里可以包含三个或三个以上的管芯。
在形成再分布线(RDL)40之前，在上述晶圆级封装(WLP)机构的实施例中，利用平坦化停止层示出了去除多余模塑料的终点。这种WLP机构能够启用扇出和多芯片封装。这种机构也能将具有不同类型的外部连接的芯片(或管芯)封装在一起。例如，具有预先形成的凸块的管芯能够和没有预先形成的凸块的管芯封装在一起。
根据一些实施例，提供了一种半导体封装件。该半导体封装件包括由模塑料包围的第一半导体管芯及其第一导电焊盘。导电焊盘位于第一半导体管芯的顶部金属平面。半导体封装件也包括形成在第一导电焊盘上方的再分布线(RDL)。RDL延伸超出了半导体管芯的边界，以及RDL的一部分与第一导电焊盘接触。与RDL的一部分接触的第一导电焊盘的表面与延伸超出了第一半导体管芯边界的RDL下方的模塑料的表面处在不同平面。
根据其他一些实施例，提供一种形成半导体封装件的方法。该方法包括提供其上布置有粘结层的载体和含有衬底的管芯。在衬底的上方形成多个接合焊盘，而在多个接合焊盘的上方形成平坦化停止层。该方法还包括：在粘结层上放置管芯，然后形成模塑料，以覆盖管芯，其中模塑料包围管芯。该方法进一步包括：平坦化模塑料，直到露出平坦化停止层，然后去除平坦化停止层。此外，该方法包括在管芯的上方形成再分布线，而再分布线电连接至多个接合焊盘中的至少一个。
根据一些其他实施例，提供一种形成半导体封装件的方法。该方法包括：提供其上布置有粘结层的载体以及含有第一衬底的第一管芯。多个第一接合焊盘形成在衬底的上方而在多个第一接合焊盘的上方形成平坦化停止层。该方法也包括：在粘结层上放置管芯，然后提供含有第二衬底的第二管芯。该方法进一步包括：在粘结层上放置第二管芯，然后在第二管芯的多个第二接合焊盘的上方形成柱形凸块。此外，该方法包括形成模塑料以覆盖第一管芯和第二管芯，模塑料包围第一管芯和第二管芯。此外，该方法包括：平坦化模塑料，直到露出平坦化停止层，然后去除平坦化停止层。该方法还包括：在第一管芯和第二管芯的上方形成再分布线，再分布线电连接至多个第一接合焊盘中的至少一个和多个第二接合焊盘中的至少一个。
尽管已经详细地描述了本发明及其优点，但应该理解，可以在不背离所附权利要求限定的本发明主旨和范围的情况下，做各种不同的改变，替换和更改。而且，本申请的范围并不仅限于本说明书中描述的工艺、机器、制造、材料组分、装置、方法和步骤的特定实施例。作为本领域普通技术人员应理解，通过本发明，现有的或今后开发的用于执行与根据本发明所采用的所述相应实施例基本相同的功能或获得基本相同结果的工艺、机器、制造，材料组分、装置、方法或步骤根据本发明可以被使用。因此，所附权利要求应该包括在这样的工艺、机器、制造、材料组分、装置、方法或步骤的范围内。此外，每条权利要求构成单独的实施例，并且多个权利要求和实施例的组合在本发明的范围内。

Claims (10)

1.一种半导体封装件，包括：
第一半导体管芯，被模塑料包围；
所述第一半导体管芯的第一导电焊盘，其中，该导电焊盘位于所述第一半导体管芯的顶部金属平面上；以及
再分布线(RDL)，形成在所述第一导电焊盘的上方，其中，所述RDL延伸超出所述半导体管芯的边界，所述RDL的一部分与所述第一导电焊盘接触，其中，所述第一导电焊盘与所述RDL的一部分接触的表面与延伸超出所述第一半导体管芯的边界的所述RDL下方的模塑料的表面处于不同的平面。
2.根据权利要求1所述的半导体封装件，其中，所述RDL通过至少一个导电插塞与所述第一导电焊盘接触。
3.根据权利要求1所述的半导体封装件，其中，所述第一导电焊盘的表面与所述模塑料的表面之间的高度差值在大约5μm到大约100μm之间的范围内。
4.根据权利要求1所述的半导体封装件，进一步包括：
第二半导体管芯，所述第二半导体管芯包括柱形凸块，所述柱形凸块位于所述第二半导体管芯上方的第二导电焊盘之上。
5.根据权利要求4所述的半导体封装件，其中，所述柱形凸块的表面与所述模塑料的表面基本处于同一平面。
6.根据权利要求4所述的半导体封装件，其中，所述柱形凸块由包括铝、铜、铝铜合金、或它们的组合的材料制成。
7.根据权利要求4所述的半导体封装件，其中，所述第二半导体管芯的输入/输出(I/O)的数量少于所述第一半导体管芯的输入/输出(I/O)的数量。
8.根据权利要求1所述的半导体封装件，其中，所述模塑料的表面基本平坦。
9.一种形成半导体封装件的方法，包括：
提供其上布置有粘结层的载体；
提供包括衬底的管芯，其中，多个接合焊盘形成在所述衬底的上方，并且平坦化停止层形成在所述多个接合焊盘的上方；
将所述管芯放置在所述粘结层上；
形成模塑料以覆盖所述管芯，其中，所述模塑料包围所述管芯；
平坦化所述模塑料，直到露出所述平坦化停止层；
去除所述平坦化停止层；以及
在所述管芯的上方形成再分布线，其中，所述再分布线电连接至所述多个接合焊盘中的至少一个。
10.一种形成半导体封装件的方法，包括：
提供其上布置有粘结层的载体；
提供包括第一衬底的第一管芯，其中，多个第一接合焊盘形成在所述衬底的上方，并且平坦化停止层形成在所述多个第一接合焊盘的上方；
在所述粘结层上放置所述第一管芯；
提供包括第二衬底的第二管芯；
在所述粘结层上放置所述第二管芯；
在所述第二管芯的多个第二接合焊盘的上方形成柱形凸块；
形成模塑料，以覆盖所述第一管芯和所述第二管芯，其中，所述模塑料包围所述第一管芯和所述第二管芯；
平坦化所述模塑料，直到露出所述平坦化停止层；
去除所述平坦化停止层；以及
在所述第一管芯和所述第二管芯的上方形成再分布线，其中，所述再分布线电连接至所述多个第一接合焊盘中的至少一个和所述多个第二接合焊盘中的至少一个。
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