CN102347251A - 嵌入式晶圆级接合方法 - Google Patents

嵌入式晶圆级接合方法 Download PDF

Info

Publication number
CN102347251A
CN102347251A CN2011101661510A CN201110166151A CN102347251A CN 102347251 A CN102347251 A CN 102347251A CN 2011101661510 A CN2011101661510 A CN 2011101661510A CN 201110166151 A CN201110166151 A CN 201110166151A CN 102347251 A CN102347251 A CN 102347251A
Authority
CN
China
Prior art keywords
dielectric layer
tube core
moulding compound
bond pads
tube
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN2011101661510A
Other languages
English (en)
Other versions
CN102347251B (zh
Inventor
余振华
林俊成
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN102347251A publication Critical patent/CN102347251A/zh
Application granted granted Critical
Publication of CN102347251B publication Critical patent/CN102347251B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561Batch processing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568Temporary substrate used as encapsulation process aid
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/03Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19Manufacturing methods of high density interconnect preforms
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/023Redistribution layers [RDL] for bonding areas
    • H01L2224/0233Structure of the redistribution layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/023Redistribution layers [RDL] for bonding areas
    • H01L2224/0233Structure of the redistribution layers
    • H01L2224/02333Structure of the redistribution layers being a bump
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/023Redistribution layers [RDL] for bonding areas
    • H01L2224/0237Disposition of the redistribution layers
    • H01L2224/02379Fan-out arrangement
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0556Disposition
    • H01L2224/05571Disposition the external layer being disposed in a recess of the surface
    • H01L2224/05572Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/11001Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
    • H01L2224/11002Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for supporting the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/113Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/11334Manufacturing methods by local deposition of the material of the bump connector in solid form using preformed bumps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/96Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20Structure, shape, material or disposition of high density interconnect preforms
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01042Molybdenum [Mo]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01047Silver [Ag]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01074Tungsten [W]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • H01L2924/1815Shape
    • H01L2924/1816Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress
    • H01L2924/3511Warping

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)

Abstract

一种方法包括:提供载体,该载体上设置有粘结层;以及提供管芯,该管芯包括第一表面、相对于第一表面的第二表面。管芯进一步包括邻近第二表面的多个接合焊盘;以及多个接合焊盘上方的介电层。该方法进一步包括:将管芯置于粘结层上,使得第一表面面向粘结层,介电层背向粘结层;形成模塑料以覆盖管芯,其中模塑料包围管芯;将处于管芯正上方的模塑料移除,以暴露出介电层;以及在模塑料上面形成再分布线,并且该再分布线穿过介电层电连接到的多个接合焊盘。

Description

嵌入式晶圆级接合方法
相关申请的交叉参考
本申请要求于2010年7月30日提交的美国临时专利申请第61/369,366号名称为“Embedded Wafer-Level Bonding Approaches”的优先权,其全部内容通过引证结合在此。
技术领域
本发明涉及半导体领域,更具体地,涉及嵌入式晶圆级接合方法。
背景技术
随着半导体技术的发展,半导体芯片/管芯变得越来越小。同时,有更多的功能需要集成到半导体管芯中。因此,半导体管芯需要将越来越多的I/O焊盘封装到越来越小的区域,因而I/O焊盘的密度随着时间迅速增加。故半导体管芯的封装变得越发困难,这对于封装的产量(yield)产生了不利影响。
传统的封装技术可以划分为两类。在第一类中,在切割晶圆上的管芯之前对该管芯进行封装。这种封装技术具有一些优点,比如生产量较高,并且成本较低。此外,需要较少的底部填充或者模塑料(moldingcompound)。然而,这种封装技术也有缺点。如上所述,管芯的尺寸变得越来越小,对应的封装可以只是扇入型(fan-in type)封装,其中,每个管芯的I/O焊盘都被限制在对应管芯表面的正上方的区域。随着管芯的区域被限制,由于限制了I/O焊盘的间距(pitch),因此就限制了I/O焊盘的数量。如果焊盘的间距减小,则会形成焊桥。另外,在固定的球尺寸需求下,焊球必须具有确定尺寸,这样就限制了能够封装到管芯表面的焊球数量。
在另一种封装类型中,在管芯被封装之前就将管芯从晶圆上切割下来,并且只有“已知的合格管芯”才能够被封装。这种封装技术的优点是能够形成扇出型(fan-out)封装,这就意味着管芯上的I/O焊盘可以重新分布到大于管芯的区域,因此,可以增加封装到管芯表面的I/O焊盘数量。
发明内容
为解决上述问题,本发明提供了一种方法,包括:提供载体,在载体上设置有粘结层;提供管芯,管芯包括:衬底;多个接合焊盘,位于衬底上方;以及介电层,位于多个接合焊盘上方;将管芯置于粘结层上;形成模塑料以覆盖管芯,其中,模塑料包围管芯;移除模塑料的管芯正上方的部分,以暴露介电层;以及在介电层上面形成再分布线,再分布线与多个接合焊盘中的至少一个电连接。
其中,在将管芯置于粘结层上的步骤之前,管芯进一步包括:金属支柱,金属支柱形成在介电层中,并且与多个接合焊盘电连接。
其中,在形成再分布线的步骤期间,金属支柱用作对准标记。
该方法进一步包括:在移除模塑料的部分的步骤之后,形成穿透介电层的金属支柱,金属支柱与多个接合焊盘电连接。
其中,移除模塑料的部分的步骤包括:在模塑料上实施化学机械抛光(CMP)。
该方法进一步包括:在形成再分布线的步骤之后,在再分布线的上方形成金属凸块,金属凸块与再分布线电连接。
该方法进一步包括:卸下载体。
其中,介电层的厚度大于大约10μm。
此外,还提供了一种方法,包括:提供载体,在载体上设置有粘结层;提供多个管芯,多个管芯中的每个管芯都包括:衬底;多个接合焊盘,位于衬底上方;介电层,位于多个接合焊盘上方;以及多个金属支柱,位于介电层中,并与多个接合焊盘电连接;将多个管芯置于粘结层上,多个管芯中的每个管芯的衬底的底面面向粘结层;将模塑料填入多个管芯之间,其中,模塑料覆盖多个管芯中的每个管芯的介电层;对模塑料实施平坦化,直到暴露多个金属支柱;以及在多个金属支柱上方形成再分布线,再分布线与多个金属支柱电连接。
其中,在实施平坦化的步骤之前,金属支柱的顶表面基本上与介电层的顶表面平齐。
其中,在实施平坦化的步骤之前,金属支柱的顶表面低于介电层的顶表面。
其中,介电层包含非模塑料介电材料。
其中,介电层包括模塑料。
其中,再分布线延伸到模塑料的正上方。
该方法进一步包括:在形成再分布线的步骤之后,在再分布线中的一条的上方形成金属凸块,金属凸块与再分布线中的一条连接;以及将载体从多个管芯和模塑料上移除。
此外,还提供了一种方法,包括:提供载体,在载体上设置有粘结层;提供多个管芯,多个管芯中的每个管芯都包括:衬底;多个接合焊盘,位于衬底上方;以及介电层,位于多个接合焊盘上方;将多个管芯置于粘结层上,多个管芯中的每个管芯的衬底的底面面向粘结层;将模塑料填入多个管芯之间,其中,模塑料覆盖多个管芯中的每个管芯的介电层;对模塑料实施平坦化,直到暴露介电层;蚀刻介电层的暴露部分,以形成多个开口,从而暴露多个接合焊盘;以及在多个开口中形成多个导电支柱。
该方法进一步包括:在多个导电支柱上方形成再分布线,并且再分布线与多个导电支柱电连接。
该方法进一步包括:在形成再分布线的步骤之后,在再分布线上方形成多个金属凸块,并且金属凸块与再分布线电连接;以及将载体从多个管芯和模塑料下面移除。
其中,多个导电支柱包含铜。
其中,介电层的厚度大于大约10μm。
附图说明
为了更加全面地理解本发明及其优点,现在将以下描述和附图结合起来作为参考,其中:
图1到图7A是根据各种实施例的制作嵌入型晶圆级封装的中间阶段的横截面图;
图7B示出了图7A中所示管芯的俯视图;以及
图8到图13是根据备选实施例的制作嵌入型晶圆级封装的中间阶段的横截面图。
具体实施方式
下面,详细讨论本发明优选实施例的制造和使用。然而,应该理解,本发明提供了许多可以在各种具体环境中实现的可应用的概念。所讨论的具体实施例仅仅示出制造和使用本发明的具体方式,而不用于限制本公开的范围。
根据实施例,提供了一种新式的嵌入式晶圆级封装结构及其形成方法。示出了制作的中间阶段的实施例。还论述了实施例的变化。在各个视图和所示实施例中,相似的参考标号用于表示相似的部件。
参考图1,提供了管芯20,该管芯20是多个相同管芯20(参考图2)中的一个。管芯20可以包括半导体衬底21,还可以包括集成电路器件23以及形成在其中的覆盖的互连结构(未示出)。集成电路器件23可以包括有源器件,比如晶体管。接合(bond)焊盘22形成在管芯20中,并且通过互连结构电连接到集成电路器件23。接合焊盘22可以由铝、铜、镍、或者其组合物制成。介电层24形成在接合焊盘22上方。在实施例中,接合焊盘22的顶表面基本上和介电层24的底表面24b平齐。介电层24是厚度为T的厚层,该厚度T大于大约10μm,还可以处于大约10μm和30μm之间,或者处于大约10μm和大约50μm之间。介电层24的材料可以选自阻焊、聚苯并恶唑(polybenzoxazole,PBO)、苯环丁烯(benzocyclobutene,BCB)、模塑料等等。介电层24的边缘垂直对齐到衬底21的相应边缘。
金属支柱(metal pillar)26形成在介电层24中,并且电连接到接合焊盘22。在实施例中,金属支柱26的底表面与接合焊盘22的顶表面相接触。金属支柱26可以包含铜,从而在整个描述中可选地将其称为铜支柱26。然而,其他导电材料(比如镍和/或铝)也可以用到铜支柱26中。铜支柱26的高度H也可以大于大约10μm,还可以处于大约5μm和30μm之间,或者处于大约10μm和大约50μm之间。横向尺寸W(取决于铜支柱26的俯视图形状)可以是长度/宽度或者直径,该横向尺寸W可以小于大约60μm。因此,H/W的比率可以大于大约0.15。在实施例中,铜支柱26的顶表面26a基本上与介电层24的顶表面24a平齐。在其他实施例中,铜支柱26的顶表面26’a高于顶表面24a,从而使得铜支柱26的部分突出到顶表面24a以上。在其他实施例中,铜支柱26的顶表面26”低于顶表面24a,从而将铜支柱26嵌入到介电层24中,此时介电层24的薄层处于铜支柱26的正上方。
参考图2,粘结层28(adhesive layer)设置(例如,层压(laminate))于载体30上。粘结层28可以由胶粘剂(glue)形成,或者可以是由箔形成的迭层(lamination layer)。接着,管芯20通过粘结层28被置于载体30上。在管芯20包括半导体衬底21的实施例中,半导体衬底21的底表面21b与粘结层28相接触。载体30可以包括对准标记31,从而使得管芯20准确地安装在载体30的期望位置上。在相邻的管芯20之间留有空间。
图3示出了将模塑料34填入管芯20之间的空间。管芯20的顶表面也由模塑料34覆盖。模塑料34可以是有机材料(比如环氧树脂),该有机材料以液态形式填充到管芯22之间的空间。接着,实施固化工艺(curingprocess),以使模塑料34凝固。
参考图4,在模塑料34上实施平坦化(比如,研磨(grinding)),直到铜支柱26(可能还有介电层24)暴露出来。因此,介电层24的顶表面24a、铜支柱26的顶表面26a、以及模塑料34的顶表面34a相互之间可以基本平齐。在铜支柱26嵌入到介电层24的实施例中,介电层24也被研磨。研磨的结果是,没有模塑料34处在管芯20的正上方。当从上面看下去时,铜支柱26被介电层24包围,并且与介电层24相接触。此外,每个管芯20中的铜支柱26和介电层24形成集成元件,该集成元件被模塑料34包围。
接下来,如图5所示,形成有再分布层(redistribution layer,RDL),其中RDL包括(多个)介电层38,以及介电层38中的导电线路40(包括金属线和金属通孔,也称为再分布线)。导电线路40可以延伸到对应管芯20的边缘之外,模塑料34的正上方,这样所形成的封装是扇出封装。在导电线路40的形成过程中,铜支柱26可以用作对准标记。因此,RDL在形成中的准确性得以改进。这样,就行成了晶圆44,包括管芯20、模塑料34、和RDL。
图6示出了金属凸块42的形成,该金属凸块42电连接到导电线路40。此外,还形成了接合焊盘(未示出),金属凸块42形成在接合焊盘上,并且与其物理接触。因此,金属凸块42位于新形成的晶圆44的顶表面上。金属凸块42可以是焊球,使用球装头部(ball-mounting head)将该焊球传送到晶圆44上。备选地,金属凸块42是非可回流(non-reflowable)凸块,比如铜凸块。一些金属凸块42还可以形成在模塑料34正上方之外。
接下来,如图7A所示,将载体30从晶圆44上卸下,以及将粘结层28移除并使其离开晶圆44。接着,晶圆44被固定到带子46上,并且沿着划片槽(scribe line)48切割开晶圆44。因此,形成了管芯50。可以理解,在每个管芯50中,管芯20的底表面20b与模塑料34的底表面34b平齐。图7B示出了管芯50的俯视图,该俯视图示出模塑料34包围管芯20,并且与管芯20的侧壁相接触。
图8到图13示出了制作根据备选实施例的嵌入型晶圆级封装的中间阶段的横截面图。除非另有说明,在这些实施例中的参考标号表示与图1到图7B中的实施例相似的部件。参考图8,提供了管芯20(带有所示出的管芯20之一)。除了在接合焊盘22上方没有铜支柱形成,管芯20与图1中的管芯20相似。这样,介电层24覆盖了接合焊盘22,介电层24的底表面24b基本上与接合焊盘22的顶表面22a平齐。介电层24中没有形成导电部件。此外,介电层24的厚度T可以大于大约10μm,还可以处于大约10μm和30μm之间,或者处于大约10μm和大约50μm之间。
接下来,如图9所示,管芯20通过粘结层28被安装到载体30上,随后施用模塑料34,如图10所示。模塑料34的顶表面34a高于介电层24的顶表面24a。接着,模塑料34被研磨,直到介电层24暴露出来,并且模塑料34处于管芯20正上方的部分被移除。所得到的结构如图11所示。
参考图12,通过蚀刻介电层24,在介电层24中形成开口54。接合焊盘22通过开口54而暴露出来。在实施例中,开口54是单镶嵌开口(singledamascene opening)。在备选实施例中,介电层38形成在介电层24上方,开口54是双镶嵌开口,包括处于介电层24中的下部和处于介电层38中的上部,其中上部比下部宽。参考图13,开口54中被填入导电材料,以形成导电柱26,除导电柱26之外还可能填入导电线路40。在实施例中,导电支柱26和导电线路40由铜、铝、铁、银、钼、焊膏等等形成。可以实施平坦化(比如化学机械抛光,CMP),以使得导电支柱26(或者导电线路40,如果有的话)的顶表面与介电层24(或者介电层38的顶表面)的顶表面平齐。在其他实施例中,实施电镀步骤,以将铜填入到开口54中。在其他实施例中,可以使用其他方法(比如物理气相沉积(PVD)),并且填入的材料可以包括钛层(未示出)和位于钛层上方的铜层(未示出)。图13还示出了介电层60的形成。剩下的步骤实质上与图7A和图7B中所示出的相同,因此在本文中不再赘述。
根据实施例的形成工艺,载体30用于在再分布线的研磨和形成期间支撑相应的覆盖封装结构。从而,可以减小模塑料34的厚度。因此,晶圆44(参考图6)的翘曲(warpage)较小。模塑料34(如图7A)没有形成在管芯20的背面上,从而管芯20的热消散不会被弱化(degraded)。此外,金属支柱26还可以用作对准标记以提高对准的精度。
根据实施例,一种方法包括:提供载体,该载体上设置有粘结层;以及提供管芯,该管芯包括第一表面、相对于第一表面的第二表面。管芯进一步包括邻近第二表面的多个接合焊盘;以及多个接合焊盘上方的介电层。该方法进一步包括:将管芯置于粘结层上,使得第一表面面向粘结层,介电层背向粘结层;形成模塑料以覆盖管芯,其中模塑料包围管芯;将处于管芯正上方的模塑料移除,以暴露出介电层;以及在模塑料上面形成再分布线,并且该再分布线穿过介电层电连接到多个接合焊盘中的一个上。
根据其他实施例,一种方法包括:提供载体,在该载体上设置有粘结层;以及提供多个管芯,该多个管芯中的每个管芯都包括:具有底面的衬底;在相对于底面的一侧上的接合焊盘;在多个接合焊盘上方的介电层;以及介电层中多个金属支柱,该金属支柱电连接到多个接合焊盘。该方法进一步包括:将多个管芯置于粘结层上,多个管芯中的每个管芯的衬底的底面都面向粘结层;将模塑料填充到多个管芯之间,其中,模塑料覆盖了多个管芯中的每个管芯的介电层;在模塑料上实施平坦化,直到多个金属支柱暴露出来;以及在介电层上方形成再分布线,该再分布线电连接到多个金属支柱。
根据其他实施例,一种方法包括:提供载体,在该载体上设置有粘结层;以及提供多个管芯,该多个管芯中的每个管芯都包括:具有底面的衬底;在相对于底面的一侧上的接合焊盘;在多个接合焊盘上方的介电层,其中介电层中基本上没有导电部件。该方法进一步包括:将多个管芯置于粘结层上,多个管芯中的每个管芯的衬底的底面都面向粘结层;将模塑料填充到多个管芯之间,其中模塑料覆盖了多个管芯中的每个管芯的介电层;以及在模塑料上实施平坦化,直到多个金属支柱暴露出来。在实施平坦化的步骤之后,介电层被蚀刻以形成多个开口,其中多个接合焊盘通过多个开口暴露出来。开口被填充以形成多个导电支柱。
根据其他实施例,一种器件包括:衬底;衬底上方的介电层;介电层中的多个金属支柱;以及与衬底和介电层的边缘相接触的模塑料。介电层和模塑料由不同的介电材料形成。
根据其他实施例,一种器件包括:半导体衬底;半导体衬底表面上方的有源器件;半导体衬底上方的介电层;介电层中的多个金属支柱;以及包围半导体衬底和介电层,并且与半导体衬底和介电层的边缘相接触的模塑料,模塑料和介电层由不同的材料形成。模塑料的顶表面基本上与金属支柱的顶表面和介电层的顶表面平齐。该器件进一步包括:介电层上方的再分布线,该再分布线电连接到多个金属支柱。
尽管已经详细地描述了本发明及其优势,但应该理解,可以在不背离所附权利要求限定的本发明主旨和范围的情况下,做各种不同的改变,替换和更改。而且,本申请的范围并不仅限于本说明书中描述的工艺、机器、制造、材料组分、装置、方法和步骤的特定实施例。作为本领域普通技术人员应理解,通过本发明,现有的或今后开发的用于执行与根据本发明所采用的所述相应实施例基本相同的功能或获得基本相同结果的工艺、机器、制造,材料组分、装置、方法或步骤根据本发明可以被使用。因此,所附权利要求应该包括在这样的工艺、机器、制造、材料组分、装置、方法或步骤的范围内。此外,每条权利要求构成单独的实施例,并且多个权利要求和实施例的组合在本发明的范围内。

Claims (10)

1.一种方法,包括:
提供载体,在所述载体上设置有粘结层;
提供管芯,所述管芯包括:衬底;多个接合焊盘,位于所述衬底上方;以及介电层,位于所述多个接合焊盘上方;
将所述管芯置于所述粘结层上;
形成模塑料以覆盖所述管芯,其中,所述模塑料包围所述管芯;
移除所述模塑料的所述管芯正上方的部分,以暴露所述介电层;以及
在所述介电层上面形成再分布线,所述再分布线与所述多个接合焊盘中的至少一个电连接。
2.根据权利要求1所述的方法,其中,在将所述管芯置于所述粘结层上的步骤之前,所述管芯进一步包括:金属支柱,所述金属支柱形成在所述介电层中,并且与所述多个接合焊盘电连接。
3.根据权利要求2所述的方法,其中,在形成再分布线的步骤期间,所述金属支柱用作对准标记。
4.根据权利要求1所述的方法,进一步包括:在移除所述模塑料的所述部分的步骤之后,形成穿透所述介电层的金属支柱,所述金属支柱与所述多个接合焊盘电连接。
5.根据权利要求1所述的方法,其中,移除所述模塑料的所述部分的步骤包括:在所述模塑料上实施化学机械抛光(CMP)。
6.根据权利要求1所述的方法,进一步包括:在形成再分布线的步骤之后,在所述再分布线的上方形成金属凸块,所述金属凸块与所述再分布线电连接。
7.根据权利要求1所述的方法,进一步包括:卸下所述载体。
8.根据权利要求1所述的方法,其中,所述介电层的厚度大于大约10μm。
9.一种方法,包括:
提供载体,在所述载体上设置有粘结层;
提供多个管芯,所述多个管芯中的每个管芯都包括:
衬底;
多个接合焊盘,位于所述衬底上方;
介电层,位于所述多个接合焊盘上方;以及
多个金属支柱,位于所述介电层中,并与所述多个接合焊盘电连接;
将所述多个管芯置于所述粘结层上,所述多个管芯中的每个管芯的衬底的底面面向所述粘结层;
将模塑料填入所述多个管芯之间,其中,所述模塑料覆盖所述多个管芯中的每个管芯的介电层;
对所述模塑料实施平坦化,直到暴露所述多个金属支柱;以及
在所述多个金属支柱上方形成再分布线,所述再分布线与所述多个金属支柱电连接。
10.一种方法,包括:
提供载体,在所述载体上设置有粘结层;
提供多个管芯,所述多个管芯中的每个管芯都包括:
衬底;
多个接合焊盘,位于所述衬底上方;以及
介电层,位于所述多个接合焊盘上方;
将所述多个管芯置于所述粘结层上,所述多个管芯中的每个管芯的衬底的底面面向所述粘结层;
将模塑料填入所述多个管芯之间,其中,所述模塑料覆盖所述多个管芯中的每个管芯的介电层;
对所述模塑料实施平坦化,直到暴露所述介电层;
蚀刻所述介电层的暴露部分,以形成多个开口,从而暴露所述多个接合焊盘;以及
在所述多个开口中形成多个导电支柱。
CN2011101661510A 2010-07-30 2011-06-15 嵌入式晶圆级接合方法 Active CN102347251B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US36936610P 2010-07-30 2010-07-30
US61/369,366 2010-07-30
US12/880,736 US8361842B2 (en) 2010-07-30 2010-09-13 Embedded wafer-level bonding approaches
US12/880,736 2010-09-13

Publications (2)

Publication Number Publication Date
CN102347251A true CN102347251A (zh) 2012-02-08
CN102347251B CN102347251B (zh) 2013-05-15

Family

ID=45527152

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2011101661510A Active CN102347251B (zh) 2010-07-30 2011-06-15 嵌入式晶圆级接合方法

Country Status (3)

Country Link
US (2) US8361842B2 (zh)
CN (1) CN102347251B (zh)
TW (1) TWI415202B (zh)

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103426846A (zh) * 2012-05-18 2013-12-04 台湾积体电路制造股份有限公司 晶圆级封装机构
CN104051287A (zh) * 2013-03-15 2014-09-17 台湾积体电路制造股份有限公司 扇出互连结构及其形成方法
US9553000B2 (en) 2011-06-28 2017-01-24 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structure for wafer level package
CN106558565A (zh) * 2015-09-30 2017-04-05 台湾积体电路制造股份有限公司 芯片封装件及其制造方法
CN107464789A (zh) * 2016-06-03 2017-12-12 艾马克科技公司 半导体装置
US10522473B2 (en) 2014-05-29 2019-12-31 Taiwan Semiconductor Manufacturing Company, Ltd. Alignment mark design for packages
US10700025B2 (en) 2013-03-15 2020-06-30 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out interconnect structure and method for forming same
CN112349601A (zh) * 2019-08-09 2021-02-09 矽磐微电子(重庆)有限公司 芯片封装结构的制作方法
CN112349608A (zh) * 2019-08-09 2021-02-09 矽磐微电子(重庆)有限公司 芯片封装结构的制作方法
CN112349595A (zh) * 2019-08-09 2021-02-09 矽磐微电子(重庆)有限公司 芯片封装结构的制作方法
CN112420531A (zh) * 2020-11-27 2021-02-26 上海易卜半导体有限公司 半导体封装方法、半导体组件以及包含其的电子设备
CN115101427A (zh) * 2022-08-26 2022-09-23 成都奕斯伟系统集成电路有限公司 芯片封装结构的制造方法及芯片封装结构

Families Citing this family (280)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9385095B2 (en) 2010-02-26 2016-07-05 Taiwan Semiconductor Manufacturing Company, Ltd. 3D semiconductor package interposer with die cavity
US9497862B2 (en) * 2011-01-30 2016-11-15 Nantong Fujitsu Microelectronics Co., Ltd. Packaging structure
US8729697B2 (en) * 2012-01-09 2014-05-20 Infineon Technologies Ag Sensor arrangement, a measurement circuit, chip-packages and a method for forming a sensor arrangement
US9613917B2 (en) 2012-03-30 2017-04-04 Taiwan Semiconductor Manufacturing Company, Ltd. Package-on-package (PoP) device with integrated passive device in a via
US9165887B2 (en) 2012-09-10 2015-10-20 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device with discrete blocks
US8975726B2 (en) 2012-10-11 2015-03-10 Taiwan Semiconductor Manufacturing Company, Ltd. POP structures and methods of forming the same
US9391041B2 (en) 2012-10-19 2016-07-12 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out wafer level package structure
US20140162407A1 (en) * 2012-12-10 2014-06-12 Curtis Michael Zwenger Method And System For Semiconductor Packaging
US9048222B2 (en) 2013-03-06 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating interconnect structure for package-on-package devices
US9142432B2 (en) * 2013-09-13 2015-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out package structures with recesses in molding compound
US9466581B2 (en) * 2013-10-18 2016-10-11 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package device and manufacturing method thereof
US9373527B2 (en) 2013-10-30 2016-06-21 Taiwan Semiconductor Manufacturing Company, Ltd. Chip on package structure and method
US9679839B2 (en) 2013-10-30 2017-06-13 Taiwan Semiconductor Manufacturing Company, Ltd. Chip on package structure and method
US9576930B2 (en) * 2013-11-08 2017-02-21 Taiwan Semiconductor Manufacturing Co., Ltd. Thermally conductive structure for heat dissipation in semiconductor packages
US9530762B2 (en) * 2014-01-10 2016-12-27 Taiwan Semiconductor Manufacturing Company Limited Semiconductor package, semiconductor device and method of forming the same
US9698121B2 (en) * 2014-01-27 2017-07-04 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and structures for packaging semiconductor dies
US9583420B2 (en) 2015-01-23 2017-02-28 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufactures
US10056267B2 (en) 2014-02-14 2018-08-21 Taiwan Semiconductor Manufacturing Company, Ltd. Substrate design for semiconductor packages and method of forming same
US10026671B2 (en) 2014-02-14 2018-07-17 Taiwan Semiconductor Manufacturing Company, Ltd. Substrate design for semiconductor packages and method of forming same
US9653443B2 (en) 2014-02-14 2017-05-16 Taiwan Semiconductor Manufacturing Company, Ltd. Thermal performance structure for semiconductor packages and method of forming same
US9768090B2 (en) 2014-02-14 2017-09-19 Taiwan Semiconductor Manufacturing Company, Ltd. Substrate design for semiconductor packages and method of forming same
US9935090B2 (en) 2014-02-14 2018-04-03 Taiwan Semiconductor Manufacturing Company, Ltd. Substrate design for semiconductor packages and method of forming same
US9263302B2 (en) 2014-02-21 2016-02-16 Taiwan Semiconductor Manufacturing Company, Ltd. Via structure for packaging and a method of forming
US9589900B2 (en) 2014-02-27 2017-03-07 Taiwan Semiconductor Manufacturing Company, Ltd. Metal pad for laser marking
US9281297B2 (en) 2014-03-07 2016-03-08 Taiwan Semiconductor Manufacturing Company, Ltd. Solution for reducing poor contact in info packages
US9293442B2 (en) 2014-03-07 2016-03-22 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and method
US9824990B2 (en) 2014-06-12 2017-11-21 Taiwan Semiconductor Manufacturing Company, Ltd. Pad design for reliability enhancement in packages
US9881857B2 (en) 2014-06-12 2018-01-30 Taiwan Semiconductor Manufacturing Company, Ltd. Pad design for reliability enhancement in packages
US9449947B2 (en) 2014-07-01 2016-09-20 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package for thermal dissipation
US9754928B2 (en) 2014-07-17 2017-09-05 Taiwan Semiconductor Manufacturing Company, Ltd. SMD, IPD, and/or wire mount in a package
US9613910B2 (en) 2014-07-17 2017-04-04 Taiwan Semiconductor Manufacturing Company, Ltd. Anti-fuse on and/or in package
US9812337B2 (en) 2014-12-03 2017-11-07 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package pad and methods of forming
US11069734B2 (en) 2014-12-11 2021-07-20 Invensas Corporation Image sensor device
US10424541B2 (en) 2014-12-16 2019-09-24 At&S Austria Technologie & Systemtechnik Aktiengesellschaft Component carrier and method for manufacturing the same
US10032651B2 (en) 2015-02-12 2018-07-24 Taiwan Semiconductor Manufacturing Company, Ltd. Package structures and method of forming the same
US10032704B2 (en) 2015-02-13 2018-07-24 Taiwan Semiconductor Manufacturing Company, Ltd. Reducing cracking by adjusting opening size in pop packages
US9564416B2 (en) 2015-02-13 2017-02-07 Taiwan Semiconductor Manufacturing Company, Ltd. Package structures and methods of forming the same
US10497660B2 (en) 2015-02-26 2019-12-03 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structures, packaged semiconductor devices, and methods of packaging semiconductor devices
US9595482B2 (en) 2015-03-16 2017-03-14 Taiwan Semiconductor Manufacturing Company, Ltd. Structure for die probing
US9589903B2 (en) 2015-03-16 2017-03-07 Taiwan Semiconductor Manufacturing Company, Ltd. Eliminate sawing-induced peeling through forming trenches
US10115647B2 (en) 2015-03-16 2018-10-30 Taiwan Semiconductor Manufacturing Company, Ltd. Non-vertical through-via in package
US10368442B2 (en) 2015-03-30 2019-07-30 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit structure and method of forming
US9786519B2 (en) 2015-04-13 2017-10-10 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor devices and methods of packaging semiconductor devices
US9653406B2 (en) 2015-04-16 2017-05-16 Taiwan Semiconductor Manufacturing Company, Ltd. Conductive traces in semiconductor devices and methods of forming same
US9461018B1 (en) 2015-04-17 2016-10-04 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out PoP structure with inconsecutive polymer layer
US9659805B2 (en) 2015-04-17 2017-05-23 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out interconnect structure and methods forming the same
US9666502B2 (en) 2015-04-17 2017-05-30 Taiwan Semiconductor Manufacturing Company, Ltd. Discrete polymer in fan-out packages
US10340258B2 (en) 2015-04-30 2019-07-02 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structures, packaged semiconductor devices, and methods of packaging semiconductor devices
US9613931B2 (en) 2015-04-30 2017-04-04 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out stacked system in package (SIP) having dummy dies and methods of making the same
US9748212B2 (en) 2015-04-30 2017-08-29 Taiwan Semiconductor Manufacturing Company, Ltd. Shadow pad for post-passivation interconnect structures
TWI563600B (en) * 2015-06-17 2016-12-21 Unimicron Technology Corp Package structure and fabrication method thereof
US9484227B1 (en) 2015-06-22 2016-11-01 Taiwan Semiconductor Manufacturing Company, Ltd. Dicing in wafer level package
US9741620B2 (en) 2015-06-24 2017-08-22 Invensas Corporation Structures and methods for reliable packages
US9818711B2 (en) 2015-06-30 2017-11-14 Taiwan Semiconductor Manufacturing Company, Ltd. Post-passivation interconnect structure and methods thereof
US10276541B2 (en) 2015-06-30 2019-04-30 Taiwan Semiconductor Manufacturing Company, Ltd. 3D package structure and methods of forming same
US9793231B2 (en) 2015-06-30 2017-10-17 Taiwan Semiconductor Manufacturing Company, Ltd. Under bump metallurgy (UBM) and methods of forming same
US9741586B2 (en) 2015-06-30 2017-08-22 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating package structures
US10170444B2 (en) 2015-06-30 2019-01-01 Taiwan Semiconductor Manufacturing Company, Ltd. Packages for semiconductor devices, packaged semiconductor devices, and methods of packaging semiconductor devices
US9842826B2 (en) 2015-07-15 2017-12-12 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacture
US9373605B1 (en) 2015-07-16 2016-06-21 Taiwan Semiconductor Manufacturing Company, Ltd. DIE packages and methods of manufacture thereof
US9391028B1 (en) 2015-07-31 2016-07-12 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit dies having alignment marks and methods of forming same
US10141288B2 (en) 2015-07-31 2018-11-27 Taiwan Semiconductor Manufacturing Company, Ltd. Surface mount device/integrated passive device on package or device structure and methods of forming
US9570410B1 (en) 2015-07-31 2017-02-14 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming connector pad structures, interconnect structures, and structures thereof
US10269767B2 (en) 2015-07-31 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-chip packages with multi-fan-out scheme and methods of manufacturing the same
US11018025B2 (en) 2015-07-31 2021-05-25 Taiwan Semiconductor Manufacturing Company, Ltd. Redistribution lines having stacking vias
US9847269B2 (en) 2015-07-31 2017-12-19 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out packages and methods of forming same
US9564345B1 (en) 2015-08-18 2017-02-07 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and manufacturing method thereof
US9768145B2 (en) 2015-08-31 2017-09-19 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming multi-die package structures including redistribution layers
US9881850B2 (en) 2015-09-18 2018-01-30 Taiwan Semiconductor Manufacturing Company, Ltd. Package structures and method of forming the same
US9685411B2 (en) 2015-09-18 2017-06-20 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit dies having alignment marks and methods of forming same
US9917072B2 (en) 2015-09-21 2018-03-13 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing an integrated stacked package with a fan-out redistribution layer (RDL) and a same encapsulating process
US10049953B2 (en) 2015-09-21 2018-08-14 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing an integrated fan-out package having fan-out redistribution layer (RDL) to accommodate electrical connectors
US9929112B2 (en) 2015-09-25 2018-03-27 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacture
US10068844B2 (en) 2015-09-30 2018-09-04 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out structure and method of forming
US10720788B2 (en) 2015-10-09 2020-07-21 Taiwan Semiconductor Manufacturing Company, Ltd. Wireless charging devices having wireless charging coils and methods of manufacture thereof
US9640498B1 (en) 2015-10-20 2017-05-02 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out (InFO) package structures and methods of forming same
US10304700B2 (en) 2015-10-20 2019-05-28 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US9691723B2 (en) 2015-10-30 2017-06-27 Taiwan Semiconductor Manufacturing Company, Ltd. Connector formation methods and packaged semiconductor devices
US9524959B1 (en) 2015-11-04 2016-12-20 Taiwan Semiconductor Manufacturing Company, Ltd. System on integrated chips and methods of forming same
US9953892B2 (en) 2015-11-04 2018-04-24 Taiwan Semiconductor Manufacturing Company, Ltd. Polymer based-semiconductor structure with cavity
US9953963B2 (en) 2015-11-06 2018-04-24 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit process having alignment marks for underfill
US9735131B2 (en) 2015-11-10 2017-08-15 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-stack package-on-package structures
US9793245B2 (en) 2015-11-16 2017-10-17 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacture
US9786614B2 (en) 2015-11-16 2017-10-10 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out structure and method of forming
US9898645B2 (en) 2015-11-17 2018-02-20 Taiwan Semiconductor Manufacturing Company, Ltd. Fingerprint sensor device and method
US9892962B2 (en) 2015-11-30 2018-02-13 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer level chip scale package interconnects and methods of manufacture thereof
US9627365B1 (en) 2015-11-30 2017-04-18 Taiwan Semiconductor Manufacturing Company, Ltd. Tri-layer CoWoS structure
US9735118B2 (en) 2015-12-04 2017-08-15 Taiwan Semiconductor Manufacturing Company, Ltd. Antennas and waveguides in InFO structures
US9893042B2 (en) 2015-12-14 2018-02-13 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US10074472B2 (en) 2015-12-15 2018-09-11 Taiwan Semiconductor Manufacturing Company, Ltd. InFO coil on metal plate with slot
US10165682B2 (en) 2015-12-28 2018-12-25 Taiwan Semiconductor Manufacturing Company, Ltd. Opening in the pad for bonding integrated passive device in InFO package
US10050013B2 (en) 2015-12-29 2018-08-14 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor devices and packaging methods
US9850126B2 (en) 2015-12-31 2017-12-26 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method of forming same
US9984998B2 (en) 2016-01-06 2018-05-29 Taiwan Semiconductor Manufacturing Company, Ltd. Devices employing thermal and mechanical enhanced layers and methods of forming same
US9881908B2 (en) 2016-01-15 2018-01-30 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out package on package structure and methods of forming same
US9773757B2 (en) 2016-01-19 2017-09-26 Taiwan Semiconductor Manufacturing Company, Ltd. Devices, packaged semiconductor devices, and semiconductor device packaging methods
US9620465B1 (en) 2016-01-25 2017-04-11 Taiwan Semiconductor Manufacturing Company, Ltd. Dual-sided integrated fan-out package
US9768303B2 (en) 2016-01-27 2017-09-19 Taiwan Semiconductor Manufacturing Co., Ltd. Method and structure for FinFET device
DE102016118802B4 (de) 2016-01-29 2022-12-08 Taiwan Semiconductor Manufacturing Co. Ltd. Drahtloses Ladepaket mit in Spulenmitte integriertem Chip und Herstellungsverfahren dafür
US10269702B2 (en) 2016-01-29 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Info coil structure and methods of manufacturing same
US9761522B2 (en) 2016-01-29 2017-09-12 Taiwan Semiconductor Manufacturing Company, Ltd. Wireless charging package with chip integrated in coil center
TW201729308A (zh) * 2016-02-05 2017-08-16 力成科技股份有限公司 晶圓級封裝結構的製造方法
US9904776B2 (en) 2016-02-10 2018-02-27 Taiwan Semiconductor Manufacturing Company, Ltd. Fingerprint sensor pixel array and methods of forming same
US9911629B2 (en) 2016-02-10 2018-03-06 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated passive device package and methods of forming same
US9754805B1 (en) * 2016-02-25 2017-09-05 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging method and structure
US10797038B2 (en) 2016-02-25 2020-10-06 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and rework process for the same
US9842815B2 (en) 2016-02-26 2017-12-12 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacture
US10062648B2 (en) 2016-02-26 2018-08-28 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and method of forming the same
US9847320B2 (en) 2016-03-09 2017-12-19 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and method of fabricating the same
US9831148B2 (en) 2016-03-11 2017-11-28 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out package including voltage regulators and methods forming same
US9633925B1 (en) * 2016-03-25 2017-04-25 Globalfoundries Inc. Visualization of alignment marks on a chip covered by a pre-applied underfill
US10026716B2 (en) 2016-04-15 2018-07-17 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC formation with dies bonded to formed RDLs
US9935024B2 (en) 2016-04-28 2018-04-03 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming semiconductor structure
US9859229B2 (en) 2016-04-28 2018-01-02 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method for forming the same
US9997464B2 (en) 2016-04-29 2018-06-12 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy features in redistribution layers (RDLS) and methods of forming same
US9947552B2 (en) 2016-04-29 2018-04-17 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and formation method of chip package with fan-out structure
US9935080B2 (en) 2016-04-29 2018-04-03 Taiwan Semiconductor Manufacturing Company, Ltd. Three-layer Package-on-Package structure and method forming same
US9922895B2 (en) 2016-05-05 2018-03-20 Taiwan Semiconductor Manufacturing Company, Ltd. Package with tilted interface between device die and encapsulating material
US9806059B1 (en) 2016-05-12 2017-10-31 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-stack package-on-package structures
US10797025B2 (en) 2016-05-17 2020-10-06 Taiwan Semiconductor Manufacturing Company, Ltd. Advanced INFO POP and method of forming thereof
US10204893B2 (en) 2016-05-19 2019-02-12 Invensas Bonding Technologies, Inc. Stacked dies and methods for forming bonded structures
US9870997B2 (en) 2016-05-24 2018-01-16 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and method of fabricating the same
US10157807B2 (en) 2016-05-26 2018-12-18 Taiwan Semiconductor Manufacturing Co., Ltd. Sensor packages and manufacturing mehtods thereof
US9852957B2 (en) 2016-05-27 2017-12-26 Taiwan Semiconductor Manufacturing Company, Ltd. Testing, manufacturing, and packaging methods for semiconductor devices
US10269481B2 (en) 2016-05-27 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked coil for wireless charging structure on InFO package
US9941216B2 (en) 2016-05-30 2018-04-10 Taiwan Semiconductor Manufacturing Co., Ltd. Conductive pattern and integrated fan-out package having the same
US9941248B2 (en) 2016-05-30 2018-04-10 Taiwan Semiconductor Manufacturing Co., Ltd. Package structures, pop devices and methods of forming the same
US9812381B1 (en) * 2016-05-31 2017-11-07 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and method of fabricating the same
US9793246B1 (en) 2016-05-31 2017-10-17 Taiwan Semiconductor Manufacturing Co., Ltd. Pop devices and methods of forming the same
US10032722B2 (en) 2016-05-31 2018-07-24 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package structure having am antenna pattern and manufacturing method thereof
US9985006B2 (en) 2016-05-31 2018-05-29 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method thereof
US11056436B2 (en) 2016-06-07 2021-07-06 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out structure with rugged interconnect
US10354114B2 (en) 2016-06-13 2019-07-16 Taiwan Semiconductor Manufacturing Company, Ltd. Fingerprint sensor in InFO structure and formation method
US10050024B2 (en) 2016-06-17 2018-08-14 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package and manufacturing method of the same
US10475769B2 (en) 2016-06-23 2019-11-12 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package and manufacturing method of the same
US10431738B2 (en) 2016-06-24 2019-10-01 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and method for fabricating the same
US10229901B2 (en) 2016-06-27 2019-03-12 Taiwan Semiconductor Manufacturing Company, Ltd. Immersion interconnections for semiconductor devices and methods of manufacture thereof
US9812426B1 (en) 2016-06-29 2017-11-07 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package, semiconductor device, and method of fabricating the same
US9653391B1 (en) 2016-06-30 2017-05-16 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor packaging structure and manufacturing method thereof
US9859254B1 (en) 2016-06-30 2018-01-02 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and a manufacturing method thereof
US9966360B2 (en) 2016-07-05 2018-05-08 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and manufacturing method thereof
US9793230B1 (en) 2016-07-08 2017-10-17 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure and method of forming
US10163800B2 (en) 2016-07-08 2018-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure with dummy feature in passivation layer
US9824902B1 (en) 2016-07-12 2017-11-21 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and method of fabricating the same
US9825007B1 (en) 2016-07-13 2017-11-21 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure with molding layer and method for forming the same
US11469215B2 (en) 2016-07-13 2022-10-11 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure with molding layer and method for forming the same
US9661794B1 (en) 2016-07-13 2017-05-23 Taiwan Semiconductor Manufacturing Co., Ltd. Method of manufacturing package structure
US9691708B1 (en) 2016-07-20 2017-06-27 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and manufacturing method thereof
US9799615B1 (en) 2016-07-20 2017-10-24 Taiwan Semiconductor Manufacturing Co., Ltd. Package structures having height-adjusted molding members and methods of forming the same
US10062654B2 (en) 2016-07-20 2018-08-28 Taiwan Semiconductor Manufacturing Co., Ltd. Semicondcutor structure and semiconductor manufacturing process thereof
US10276542B2 (en) 2016-07-21 2019-04-30 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and manufacturing method thereof
US10276506B2 (en) 2016-07-21 2019-04-30 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package
US9984960B2 (en) 2016-07-21 2018-05-29 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and method of fabricating the same
US10163860B2 (en) 2016-07-29 2018-12-25 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package structure
US10083949B2 (en) 2016-07-29 2018-09-25 Taiwan Semiconductor Manufacturing Company, Ltd. Using metal-containing layer to reduce carrier shock in package formation
US10340206B2 (en) 2016-08-05 2019-07-02 Taiwan Semiconductor Manufacturing Company, Ltd. Dense redistribution layers in semiconductor packages and methods of forming the same
US10134708B2 (en) 2016-08-05 2018-11-20 Taiwan Semiconductor Manufacturing Company, Ltd. Package with thinned substrate
US10297551B2 (en) 2016-08-12 2019-05-21 Taiwan Semiconductor Manufacturing Co., Ltd. Method of manufacturing redistribution circuit structure and method of manufacturing integrated fan-out package
US10658334B2 (en) 2016-08-18 2020-05-19 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming a package structure including a package layer surrounding first connectors beside an integrated circuit die and second connectors below the integrated circuit die
US10672741B2 (en) 2016-08-18 2020-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages with thermal-electrical-mechanical chips and methods of forming the same
US10120971B2 (en) 2016-08-30 2018-11-06 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and layout method thereof
US9741690B1 (en) 2016-09-09 2017-08-22 Taiwan Semiconductor Manufacturing Company, Ltd. Redistribution layers in semiconductor packages and methods of forming same
US10128182B2 (en) 2016-09-14 2018-11-13 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package structure and manufacturing method thereof
US10529697B2 (en) 2016-09-16 2020-01-07 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of forming the same
US9922896B1 (en) 2016-09-16 2018-03-20 Taiwan Semiconductor Manufacturing Company, Ltd. Info structure with copper pillar having reversed profile
US9922964B1 (en) 2016-09-19 2018-03-20 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure with dummy die
US9859245B1 (en) 2016-09-19 2018-01-02 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure with bump and method for forming the same
US9911672B1 (en) 2016-09-30 2018-03-06 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor devices, method for fabricating integrated fan-out packages, and method for fabricating semiconductor devices
US9837359B1 (en) 2016-09-30 2017-12-05 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and method of fabricating the same
US10515899B2 (en) 2016-10-03 2019-12-24 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure with bump
US10157846B2 (en) 2016-10-13 2018-12-18 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming chip package involving cutting process
US10163801B2 (en) 2016-10-14 2018-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and formation method of chip package with fan-out structure
US10014260B2 (en) 2016-11-10 2018-07-03 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method for forming the same
US10163813B2 (en) 2016-11-17 2018-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure including redistribution structure and conductive shielding film
US9837366B1 (en) 2016-11-28 2017-12-05 Taiwan Semiconductor Manufacturing Co., Ltd. Semicondcutor structure and semiconductor manufacturing process thereof
US10103125B2 (en) 2016-11-28 2018-10-16 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure and method for forming the same
US10692813B2 (en) 2016-11-28 2020-06-23 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package with dummy bumps connected to non-solder mask defined pads
US10177078B2 (en) 2016-11-28 2019-01-08 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming chip package structure
US10037963B2 (en) 2016-11-29 2018-07-31 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of forming the same
US10128193B2 (en) 2016-11-29 2018-11-13 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method for forming the same
US10304793B2 (en) 2016-11-29 2019-05-28 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method for forming the same
US10163824B2 (en) 2016-12-02 2018-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and method of fabricating the same
US9972581B1 (en) 2017-02-07 2018-05-15 Taiwan Semiconductor Manufacturing Company, Ltd. Routing design of dummy metal cap and redistribution line
US10854568B2 (en) 2017-04-07 2020-12-01 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with Si-substrate-free interposer and method forming same
DE102017123449B4 (de) 2017-04-10 2023-12-28 Taiwan Semiconductor Manufacturing Co. Ltd. Gehäuse mit Si-substratfreiem Zwischenstück und Ausbildungsverfahren
US10522449B2 (en) 2017-04-10 2019-12-31 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with Si-substrate-free interposer and method forming same
US10685896B2 (en) * 2017-04-13 2020-06-16 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit package and method of fabricating the same
US10325868B2 (en) 2017-04-24 2019-06-18 Advanced Semiconductor Engineering, Inc. Semiconductor package device and method of manufacturing the same
US10879212B2 (en) 2017-05-11 2020-12-29 Invensas Bonding Technologies, Inc. Processed stacked dies
US10217720B2 (en) 2017-06-15 2019-02-26 Invensas Corporation Multi-chip modules formed using wafer-level processing of a reconstitute wafer
US10170341B1 (en) 2017-06-30 2019-01-01 Taiwan Semiconductor Manufacturing Company, Ltd. Release film as isolation film in package
US10269589B2 (en) 2017-06-30 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing a release film as isolation film in package
DE102017126028B4 (de) 2017-06-30 2020-12-10 Taiwan Semiconductor Manufacturing Co., Ltd. Gehäuse und Herstellungsverfahren mit einem Trennfilm als Isolierfilm
US10867924B2 (en) 2017-07-06 2020-12-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package with redistribution structure and pre-made substrate on opposing sides for dual-side metal routing
US10522526B2 (en) 2017-07-28 2019-12-31 Taiwan Semiconductor Manufacturing Company, Ltd. LTHC as charging barrier in InFO package formation
US10290571B2 (en) 2017-09-18 2019-05-14 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with si-substrate-free interposer and method forming same
US10276537B2 (en) * 2017-09-25 2019-04-30 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and manufacturing method thereof
US10319707B2 (en) * 2017-09-27 2019-06-11 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor component, package structure and manufacturing method thereof
US10629540B2 (en) 2017-09-27 2020-04-21 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US11217555B2 (en) 2017-09-29 2022-01-04 Taiwan Semiconductor Manufacturing Company, Ltd. Aligning bumps in fan-out packaging process
US10727217B2 (en) 2017-09-29 2020-07-28 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing semiconductor device that uses bonding layer to join semiconductor substrates together
US10790244B2 (en) 2017-09-29 2020-09-29 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US10269773B1 (en) 2017-09-29 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages and methods of forming the same
KR102124892B1 (ko) * 2017-09-29 2020-06-22 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 팬-아웃 패키징 공정에서의 범프 정렬
US10665582B2 (en) * 2017-11-01 2020-05-26 Taiwan Semiconductor Manufacturing Co., Ltd. Method of manufacturing semiconductor package structure
US10957672B2 (en) * 2017-11-13 2021-03-23 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of manufacturing the same
US10529650B2 (en) 2017-11-15 2020-01-07 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and method
US11031342B2 (en) 2017-11-15 2021-06-08 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and method
US10784203B2 (en) 2017-11-15 2020-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and method
US10522501B2 (en) 2017-11-17 2019-12-31 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure and method of forming the same
US10734323B2 (en) * 2017-11-22 2020-08-04 Taiwan Semiconductor Manufacturing Co., Ltd. Package structures
US10468339B2 (en) 2018-01-19 2019-11-05 Taiwan Semiconductor Manufacturing Company, Ltd. Heterogeneous fan-out structure and method of manufacture
US10762319B2 (en) * 2018-01-30 2020-09-01 Taiwan Semiconductor Manufacturing Co., Ltd. Fingerprint sensor and manufacturing method thereof
US10510650B2 (en) 2018-02-02 2019-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing semiconductor device packaging structure having through interposer vias and through substrate vias
US11488881B2 (en) 2018-03-26 2022-11-01 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacture
US11062915B2 (en) 2018-03-29 2021-07-13 Taiwan Semiconductor Manufacturing Company, Ltd. Redistribution structures for semiconductor packages and methods of forming the same
US10504858B2 (en) * 2018-04-27 2019-12-10 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method of fabricating the same
US10510595B2 (en) 2018-04-30 2019-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out packages and methods of forming the same
US10631392B2 (en) 2018-04-30 2020-04-21 Taiwan Semiconductor Manufacturing Company, Ltd. EUV collector contamination prevention
US11276676B2 (en) 2018-05-15 2022-03-15 Invensas Bonding Technologies, Inc. Stacked devices and methods of fabrication
US11114407B2 (en) * 2018-06-15 2021-09-07 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out package and manufacturing method thereof
US10340249B1 (en) 2018-06-25 2019-07-02 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US11049805B2 (en) 2018-06-29 2021-06-29 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and method
US10886231B2 (en) 2018-06-29 2021-01-05 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming RDLS and structure formed thereof
US10825696B2 (en) 2018-07-02 2020-11-03 Taiwan Semiconductor Manufacturing Company, Ltd. Cross-wafer RDLs in constructed wafers
US11004803B2 (en) 2018-07-02 2021-05-11 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy dies for reducing warpage in packages
WO2020010265A1 (en) * 2018-07-06 2020-01-09 Invensas Bonding Technologies, Inc. Microelectronic assemblies
WO2020010136A1 (en) 2018-07-06 2020-01-09 Invensas Bonding Technologies, Inc. Molded direct bonded and interconnected stack
US11502067B2 (en) * 2018-07-26 2022-11-15 Advanced Semiconductor Engineering, Inc. Package structure and method for manufacturing the same
US10515848B1 (en) 2018-08-01 2019-12-24 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and method
US10658348B2 (en) 2018-09-27 2020-05-19 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices having a plurality of first and second conductive strips
US10832985B2 (en) 2018-09-27 2020-11-10 Taiwan Semiconductor Manufacturing Company, Ltd. Sensor package and method
US10861841B2 (en) 2018-09-28 2020-12-08 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device with multiple polarity groups
DE102019101999B4 (de) 2018-09-28 2021-08-05 Taiwan Semiconductor Manufacturing Company, Ltd. Halbleitervorrichtung mit mehreren polaritätsgruppen
US11164754B2 (en) 2018-09-28 2021-11-02 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out packages and methods of forming the same
US10679915B2 (en) * 2018-10-28 2020-06-09 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and manufacturing method thereof
US10665520B2 (en) 2018-10-29 2020-05-26 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method
US11217538B2 (en) 2018-11-30 2022-01-04 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method
US11121089B2 (en) 2018-11-30 2021-09-14 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method
US11011451B2 (en) 2018-12-05 2021-05-18 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method
US11217546B2 (en) 2018-12-14 2022-01-04 Taiwan Semiconductor Manufacturing Company, Ltd. Embedded voltage regulator structure and method forming same
US11410875B2 (en) * 2018-12-19 2022-08-09 Texas Instruments Incorporated Fan-out electronic device
US11538735B2 (en) 2018-12-26 2022-12-27 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming integrated circuit packages with mechanical braces
CN113330557A (zh) 2019-01-14 2021-08-31 伊文萨思粘合技术公司 键合结构
US10978382B2 (en) 2019-01-30 2021-04-13 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method
TWI810380B (zh) * 2019-02-22 2023-08-01 南韓商愛思開海力士有限公司 包括橋接晶粒的系統級封裝件
US11145560B2 (en) 2019-04-30 2021-10-12 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and methods of manufacturing
US11088094B2 (en) 2019-05-31 2021-08-10 Taiwan Semiconductor Manufacturing Company, Ltd. Air channel formation in packaging process
US11133282B2 (en) 2019-05-31 2021-09-28 Taiwan Semiconductor Manufacturing Company, Ltd. COWOS structures and methods forming same
US10950519B2 (en) 2019-05-31 2021-03-16 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method
US11380620B2 (en) 2019-06-14 2022-07-05 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package including cavity-mounted device
US11004758B2 (en) 2019-06-17 2021-05-11 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method
US11296053B2 (en) 2019-06-26 2022-04-05 Invensas Bonding Technologies, Inc. Direct bonded stack structures for increased reliability and improved yield in microelectronics
US11133258B2 (en) 2019-07-17 2021-09-28 Taiwan Semiconductor Manufacturing Company, Ltd. Package with bridge die for interconnection and method forming same
US11387191B2 (en) 2019-07-18 2022-07-12 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method
US10879114B1 (en) 2019-08-23 2020-12-29 Taiwan Semiconductor Manufacturing Company, Ltd. Conductive fill
US11211371B2 (en) 2019-10-18 2021-12-28 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit package and method
US11532533B2 (en) 2019-10-18 2022-12-20 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit package and method
US11387222B2 (en) 2019-10-18 2022-07-12 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit package and method
DE102020114141B4 (de) 2019-10-18 2024-03-28 Taiwan Semiconductor Manufacturing Co., Ltd. Integriertes schaltungspackage und verfahren
US11227837B2 (en) 2019-12-23 2022-01-18 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method
US11515224B2 (en) 2020-01-17 2022-11-29 Taiwan Semiconductor Manufacturing Co., Ltd. Packages with enlarged through-vias in encapsulant
US11227795B2 (en) 2020-01-17 2022-01-18 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method
US11682626B2 (en) 2020-01-29 2023-06-20 Taiwan Semiconductor Manufacturing Co., Ltd. Chamfered die of semiconductor package and method for forming the same
US11393746B2 (en) 2020-03-19 2022-07-19 Taiwan Semiconductor Manufacturing Company, Ltd. Reinforcing package using reinforcing patches
US11264359B2 (en) 2020-04-27 2022-03-01 Taiwan Semiconductor Manufacturing Co., Ltd. Chip bonded to a redistribution structure with curved conductive lines
US11948930B2 (en) 2020-04-29 2024-04-02 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and method of manufacturing the same
US11929261B2 (en) 2020-05-01 2024-03-12 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and method of manufacturing the same
US11942417B2 (en) 2020-05-04 2024-03-26 Taiwan Semiconductor Manufacturing Co., Ltd. Sensor package and method
US11631647B2 (en) 2020-06-30 2023-04-18 Adeia Semiconductor Bonding Technologies Inc. Integrated device packages with integrated device die and dummy element
US11670601B2 (en) 2020-07-17 2023-06-06 Taiwan Semiconductor Manufacturing Co., Ltd. Stacking via structures for stress reduction
US11532524B2 (en) 2020-07-27 2022-12-20 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit test method and structure thereof
US11652037B2 (en) 2020-07-31 2023-05-16 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and method of manufacture
US11764177B2 (en) 2020-09-04 2023-09-19 Adeia Semiconductor Bonding Technologies Inc. Bonded structure with interconnect structure
US11728273B2 (en) 2020-09-04 2023-08-15 Adeia Semiconductor Bonding Technologies Inc. Bonded structure with interconnect structure
US11454888B2 (en) 2020-09-15 2022-09-27 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method of manufacture
US11868047B2 (en) 2020-09-21 2024-01-09 Taiwan Semiconductor Manufacturing Co., Ltd. Polymer layer in semiconductor device and method of manufacture
US11830821B2 (en) 2020-10-19 2023-11-28 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor devices and methods of manufacture
CN115763346A (zh) * 2021-09-03 2023-03-07 群创光电股份有限公司 电子装置的制造方法
JP2023038075A (ja) * 2021-09-06 2023-03-16 キオクシア株式会社 半導体製造装置および半導体装置の製造方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1568546A (zh) * 2002-08-09 2005-01-19 卡西欧计算机株式会社 半导体器件及其制造方法
US20090001598A1 (en) * 2007-06-27 2009-01-01 Wen-Chih Chiou Formation of Through Via before Contact Processing

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10137184B4 (de) 2001-07-31 2007-09-06 Infineon Technologies Ag Verfahren zur Herstellung eines elektronischen Bauteils mit einem Kuststoffgehäuse und elektronisches Bauteil
TW533559B (en) * 2001-12-17 2003-05-21 Megic Corp Chip package structure and its manufacturing process
TW200611385A (en) * 2004-09-29 2006-04-01 Phoenix Prec Technology Corp Carried structure of integrated semiconductor element and method for fabricating the same
TWI301663B (en) * 2006-08-02 2008-10-01 Phoenix Prec Technology Corp Circuit board structure with embedded semiconductor chip and fabrication method thereof

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1568546A (zh) * 2002-08-09 2005-01-19 卡西欧计算机株式会社 半导体器件及其制造方法
US20090001598A1 (en) * 2007-06-27 2009-01-01 Wen-Chih Chiou Formation of Through Via before Contact Processing

Cited By (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9553000B2 (en) 2011-06-28 2017-01-24 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structure for wafer level package
US10008463B2 (en) 2012-05-18 2018-06-26 Taiwan Semiconductor Manufacturing Co., Ltd. Wafer-level packaging mechanisms
CN103426846A (zh) * 2012-05-18 2013-12-04 台湾积体电路制造股份有限公司 晶圆级封装机构
CN103426846B (zh) * 2012-05-18 2017-04-05 台湾积体电路制造股份有限公司 晶圆级封装机构
US10700025B2 (en) 2013-03-15 2020-06-30 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out interconnect structure and method for forming same
CN104051287A (zh) * 2013-03-15 2014-09-17 台湾积体电路制造股份有限公司 扇出互连结构及其形成方法
CN104051287B (zh) * 2013-03-15 2017-06-16 台湾积体电路制造股份有限公司 扇出互连结构及其形成方法
US11133274B2 (en) 2013-03-15 2021-09-28 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out interconnect structure and method for forming same
US10522473B2 (en) 2014-05-29 2019-12-31 Taiwan Semiconductor Manufacturing Company, Ltd. Alignment mark design for packages
US11742298B2 (en) 2014-05-29 2023-08-29 Taiwan Semiconductor Manufacturing Company, Ltd. Alignment mark design for packages
US11133286B2 (en) 2015-09-30 2021-09-28 Taiwan Semiconductor Manufacturing Company, Ltd. Chip packages and methods of manufacture thereof
CN106558565A (zh) * 2015-09-30 2017-04-05 台湾积体电路制造股份有限公司 芯片封装件及其制造方法
US10483234B2 (en) 2015-09-30 2019-11-19 Taiwan Semiconductor Manufacturing Company, Ltd. Chip packages and methods of manufacture thereof
CN107464789A (zh) * 2016-06-03 2017-12-12 艾马克科技公司 半导体装置
CN107464789B (zh) * 2016-06-03 2023-09-22 艾马克科技公司 半导体装置
CN112349601A (zh) * 2019-08-09 2021-02-09 矽磐微电子(重庆)有限公司 芯片封装结构的制作方法
CN112349595A (zh) * 2019-08-09 2021-02-09 矽磐微电子(重庆)有限公司 芯片封装结构的制作方法
CN112349608A (zh) * 2019-08-09 2021-02-09 矽磐微电子(重庆)有限公司 芯片封装结构的制作方法
CN112420531A (zh) * 2020-11-27 2021-02-26 上海易卜半导体有限公司 半导体封装方法、半导体组件以及包含其的电子设备
CN115101427A (zh) * 2022-08-26 2022-09-23 成都奕斯伟系统集成电路有限公司 芯片封装结构的制造方法及芯片封装结构

Also Published As

Publication number Publication date
TWI415202B (zh) 2013-11-11
TW201205699A (en) 2012-02-01
US20130122655A1 (en) 2013-05-16
CN102347251B (zh) 2013-05-15
US8580614B2 (en) 2013-11-12
US20120028411A1 (en) 2012-02-02
US8361842B2 (en) 2013-01-29

Similar Documents

Publication Publication Date Title
CN102347251B (zh) 嵌入式晶圆级接合方法
US10833039B2 (en) Multi-chip fan out package and methods of forming the same
US10128211B2 (en) Thin fan-out multi-chip stacked package structure and manufacturing method thereof
CN101221936B (zh) 具有晶粒置入通孔之晶圆级封装及其方法
CN105374693B (zh) 半导体封装件及其形成方法
CN107275294B (zh) 薄型芯片堆叠封装构造及其制造方法
US8134235B2 (en) Three-dimensional semiconductor device
CN104377171B (zh) 具有中介层的封装件及其形成方法
CN105845636B (zh) 在用于接合管芯的中介层中的具有不同尺寸的tsv
TWI254425B (en) Chip package structure, chip packaging process, chip carrier and manufacturing process thereof
CN104217997A (zh) 3d封装件及其形成方法
CN103515305A (zh) 3d ic堆叠器件及制造方法
KR20150066184A (ko) 반도체 패키지 및 그 제조방법
US8101461B2 (en) Stacked semiconductor device and method of manufacturing the same
CN103295986A (zh) 形成用于堆叠封装件的连接件的机构
CN104183597A (zh) 具有管芯和穿衬底过孔的半导体器件
US8785297B2 (en) Method for encapsulating electronic components on a wafer
CN104051355B (zh) 层叠封装结构及其形成方法
CN106298683B (zh) 半导体器件
CN112349595A (zh) 芯片封装结构的制作方法
CN106098569A (zh) 用于半导体封装件的模制层的形成方法
CN105720007B (zh) 电子封装结构及其制法
CN109698136B (zh) 一种射频soi芯片的封装方法及封装结构
CN112786542A (zh) 半导体封装及其制造方法
TWI627694B (zh) 模封互連基板之面板組合構造及其製造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant