CN106298683B - 半导体器件 - Google Patents
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- CN106298683B CN106298683B CN201610004045.5A CN201610004045A CN106298683B CN 106298683 B CN106298683 B CN 106298683B CN 201610004045 A CN201610004045 A CN 201610004045A CN 106298683 B CN106298683 B CN 106298683B
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Abstract
本发明公开了一种半导体器件,包含有一芯片,其具有一有源面以及一背面,相对于所述有源面;一模塑料,封盖住所述芯片的所述有源面以外的部分;一重分布层,设置在所述有源面上以及所述模塑料上,其中所述重分布层是电连接所述芯片;以及一应力缓和结构特征,埋设置在所述模塑料中。
Description
技术领域
本发明是有关于一种半导体器件,特别是有关于一种晶圆级封装(wafer levelpackage,WLP),具有应力缓和结构特征(stress-relief features),设置在模塑料(molding compound)的上部。
背景技术
晶圆级封装工艺是本领域技术人员已熟知的技术。在晶圆级封装工艺中,包含集成电路形成其中或芯片安装其上的晶圆会经过一连串工艺,例如抛光、晶粒对准接合,以及封模成型等步骤,最后再经过切割得到最终产品。现今本领域普遍认为晶圆级封装工艺是最适合应用在小尺寸与高速芯片封装的技术。
现有技术中,进行晶圆级封装时,会使用一相对厚的模塑料(molding compound)覆盖住晶圆与安装在晶圆上的晶粒。由于模塑料的热膨胀系数(CTE)与晶圆的不同,由一定厚度的模塑料所构成的封装体受到热变化时容易翘曲。不仅如此,模塑料的存在也使封装体的整体厚度增加。晶圆翘曲的问题一直是本领域技术人员企图解决的问题。
晶圆翘曲造成晶粒与晶圆间的连接不易维持,致使晶粒与晶圆叠层组装失败。翘曲问题在大尺寸晶圆上更是明显,使大尺寸晶圆的晶圆级封装更加困难。有鉴于此,本领域仍需要一个改良的晶圆级封装方法,可以解决上述先前技术的问题。
发明内容
本发明的主要目的在于提供一改良的半导体器件,可以减轻或消除晶圆或封装体翘曲的问题,使制得的半导体封装体具有更好的可靠度。
本发明一实施例提供一种半导体器件,包含有一芯片,其具有一有源面以及一背面,相对于所述有源面;一模塑料,封盖住所述芯片的所述有源面以外的部分;一重分布层,设置在所述有源面上以及所述模塑料上,其中所述重分布层是电连接所述芯片;以及一应力缓和结构特征,埋设在所述模塑料中。
根据本发明一实施例,所述半导体器件还包括一穿硅通孔(TSV)中介层,连接所述重分布层。所述TSV中介层的一底面上具有多数个焊锡球,为后续连接用,例如,连结到一主机板或印刷电路板。
毋庸置疑的,本领域的技术人员读完接下来本发明优选实施例的详细描述与附图后,均可了解本发明的目的。
附图说明
图1到图8为示意性剖面图,说明根据本发明一实施例,制作一具有穿硅通孔的晶圆级封装体的方法。
图9A到图9C是示意性俯视图,图示模塑料上的沟槽的例示性布局。
图10到图17为示意性剖面图,说明根据本发明另一实施例,制作一晶圆级封装体的方法。
其中,附图标记说明如下:
10 晶圆级封装
100 晶圆
100a 正面
100b 背面
101 TSV中介层
102 穿硅通孔
110、410 重分布层
112、412 介电层
114、414 金属层
116、416 凸块
118、418 底胶
120、420 芯片或晶粒
121、421 输出/输入(I/O)接垫
200、500 模塑料
202、502 沟槽
204、504 应力缓和结构特征
210、510 凸块焊盘
212、512 绝缘层
220、520 焊锡球
300 载体
302 黏着层
310 介电层
具体实施方式
接下来的详细说明须参考相关附图所示内容,用来说明可依据本发明具体实施的实施例。
这些实施例提供足够的细节,可使此领域中的技术人员充分了解并具体实施本发明。在不悖离本发明的范围内,可做结构、逻辑和电性上的修改应用在其他实施例上。
接下来的详细说明并非用来对本发明加以限制。本发明涵盖的范围由其权利要求界定。与本发明权利要求具同等意义者,也应属本发明涵盖的范围。
本发明实施例所参考的附图为示意图,并未按比例绘制,且相同或类似的特征通常以相同的附图标记描述。
在本说明书中,“晶粒”、“半导体芯片”与“半导体晶粒”具有相同含意,可交替使用。
在本说明书中,“晶圆”与“基板”意指任何包含一暴露面,可在其上沉积材料并制作例如本发明实施例的重分布层(RDL)电路结构的任何结构物。
须了解的是,“基板”包含半导体晶圆,但不限于此。半导体工艺中,“基板”也用来表示包含制作于其上的材料层的半导体结构物。
在本说明书中,“穿硅通孔(TSV)”一词被广义定义为包括任何芯片或集成电路裸晶上所具有的孔洞或穿孔,其内填充有导电填料材料(例如,铜或钨等金属)。TSV通孔提供从芯片或集成电路裸晶的底面延伸到晶圆顶侧上或芯片表面上的接触层或任何金属互连层的电连结。
请参考图1到图8。图1到图8为示意性剖面图,说明根据本发明一实施例,制作一具有穿硅通孔(through substrate via,TSV)的晶圆级封装体的方法。
如图1所示,首先提供一晶圆100。晶圆100包含硅晶圆、半导体晶圆或中介层晶圆,但不限于此。例如,晶圆100可为一硅中介层晶圆。晶圆100具有一正面100a与一背面100b,相对于正面100a。在晶圆100的正面100a上,形成有多数个穿硅通孔102。
制作穿硅通孔102的方法已为本技术领域的技术人员所熟悉。举例来说,制作穿硅通孔102的方法包含首先在晶圆100的正面100a制作距离晶圆100主表面一预定深度的TSV孔洞,然后在TSV孔洞内沉积金属层,例如扩散阻障金属层与铜层,但不限于此。接着对晶圆100的正面100a进行一抛光工艺,移除TSV孔洞外多余的金属层。
接着,如图2所示,在晶圆100的正面100a上形成一重分布层(RDL)110。重分布层110可以包含至少一介电层112与至少一金属层114。穿硅通孔102可以与金属层114电性连接。重分布层110可以包含一增层内连线(build-up interconnect)结构。
接着,在重分布层110上形成多数个凸块116,例如,微凸块(micro-bumps),为后续连接用。凸块116可分别直接形成在金属层114的接触垫上。
如图3所示,形成凸块116后,接着将个别覆晶芯片或晶粒120有源面朝下,通过凸块116安装到重分布层110上,得到一芯片对晶圆叠合的构造。在各芯片或晶粒120的有源面上具有多数个输出/输入(I/O)接垫121,安装时,使凸块116对准输出/输入接垫121。
接下来,可选择性的在每一芯片或晶粒120与晶圆100的正面100a之间填充一底胶118。然后,进行一热处理,使凸块116回流焊。
如图4所示,完成晶粒接合后,接着在晶圆100的正面100a上覆盖模塑料200。模塑料200封盖住已贴合好的芯片或晶粒120,并且覆盖重分布层110的上表面。接着,模塑料200可以进行一固化工艺。
根据例示的实施例,模塑料200可使用例如转印模具及热固成型化合物来形成。可以使用其他手段来分配模塑料。也可使用在升高的温度或环境温度下为液体的环氧树脂、树脂和化合物。模塑料200是电绝缘体,并且可以是热导体。不同填料可以被添加以增强模塑料200的热传导,刚度或黏附性能。
如图5所示,形成模塑料200之后,在模塑料200的上部继续形成多数个沟槽202。沟槽202可以利用切割、线锯、激光或蚀刻等方式形成,但不限于此。根据例示的实施例,沟槽202可以直接位于芯片或晶粒120的正上方。
第9A到9C图是示意性俯视图,图示模塑料200上的沟槽202的一些例示性布局。如图9A所示,沟槽202可以被布置成栅格图案。如图9B所示,沟槽202可以被布置成分离的孔洞图案。如图9C所示,沟槽202可以被布置成同心圆图案。但是应该理解的是,根据设计要求,也可采用其它图案。
如图6所示,随后,应力缓和结构特征204被形成在模塑料200的各沟槽202中。根据所示的实施例中,应力缓和结构特征204可以完全填满沟槽202。应力缓和结构特征204可包括具有相对低杨氏系数(Young's Modulus)的弹性材料。例如,上述弹性材料可包括有机材料,例如光刻胶、聚酰亚胺(polyimide)或苯并环丁烯(benzocyclobutene)。
如图7所示,形成模塑料200和应力缓和结构特征204后,继续对晶圆100进行一晶背抛光工艺,以从背面100b抛光掉部分厚度的晶圆100,从而形成TSV中介层101。例如,晶圆100可以首先被装载到芯片抛光机(图未示)。然后,使抛光垫与晶圆100的背面100b接触,并开始抛光背面100b。上述抛光处理降低了晶圆100的厚度,因此露出所述的穿硅通孔102的下端。
如图8所示,可以继续在晶圆100的背面100b进行金属化工艺,以在绝缘层212内形成多数个凸块焊盘210。之后,可以在个别的凸块焊盘210上形成焊锡凸块或焊锡球220。然后,晶圆100可以被切割成彼此分离的个别的晶圆级封装10。
根据例示的实施例,嵌入在模塑料200的上部的应力缓和结构特征204可以改善或避免晶圆100在晶圆层级或在芯片层级的翘曲情形。
请参考图10到图17。图10到图17为示意性剖面图,说明根据本发明另一实施例,制作一晶圆级封装体的方法。
如图10所示,提供一载体300,其可以是一可撕除的基板材料,且其上可具有一黏着层302。在载体300上可形成有至少一介电层310。
如图11所示,接着,在介电层310上形成一重分布层(RDL)410。重分布层410可以包含至少一介电层412与至少一金属层414。接着,在重分布层410上形成多数个凸块416,例如,微凸块(micro-bumps),为后续连接用。凸块416可分别直接形成在金属层414的接触垫上。
如图12所示,形成凸块416后,接着将个别的覆晶芯片或晶粒420有源面朝下,通过凸块416安装到重分布层410上,得到一芯片对晶圆叠合的构造。在个别的芯片或晶粒420的有源面上具有多数个输出/输入(I/O)接垫421,安装时,使凸块416对准输出/输入接垫421。接下来,可选择性的在每一芯片或晶粒420下方填充一底胶418。然后,进行一热处理,使凸块416回流焊。
如图13所示,完成晶粒接合后,接着覆盖一模塑料500。模塑料500封盖住已贴合好的芯片或晶粒420,并且覆盖重分布层410的上表面。接着,模塑料500可以进行一固化工艺。
如图14所示,形成模塑料500之后,在模塑料500的上部继续形成多数个沟槽502。沟槽502可以利用切割、线锯、激光或蚀刻等方式形成,但不限于此。根据例示的实施例,沟槽502可以直接位于芯片或晶粒420的正上方。
如图15所示,随后,应力缓和结构特征504被形成在模塑料500的各沟槽502中。根据所示的实施例中,应力缓和结构特征504可以完全填满沟槽502。应力缓和结构特征504可包括具有相对低杨氏系数的弹性材料。例如,上述弹性材料可包括有机材料,例如光刻胶,聚酰亚胺或苯并环丁烯。
如图16所示,形成模塑料500和应力缓和结构特征504后,将载体300及黏着层302去除或撕除,以显露出介电层310。
如图17所示,可以继续在介电层310上进行金属化工艺,以在绝缘层512内形成多数个凸块焊盘510。之后,可以在个别的凸块焊盘510上形成焊锡凸块或焊锡球520。然后,可以进行切割制程,形成彼此分离的个别的晶圆级封装10。
以上所述仅为本发明的优选实施例而已,并不用于限制本发明,对于本领域的技术人员来说,本发明可以有各种更改和变化。凡在本发明的精神和原则之内,所作的任何修改、等同替换、改进等,均应包含在本发明的保护范围之内。
Claims (7)
1.一种半导体器件,其包含:
芯片,其具有有源面以及与所述有源面相对的背面;
模塑料,其封盖住所述芯片的除了所述有源面以外的部分;
重分布层,其设置在所述有源面上以及所述模塑料上,其中所述重分布层是电连接至所述芯片的;
多个沟槽,其位于所述模塑料的上部,所述多个沟槽中的至少一些直接位于所述芯片的所述背面的上方;以及
应力缓和结构特征,其埋设在所述模塑料的所述多个沟槽内。
2.根据权利要求1所述的半导体器件,其中所述应力缓和结构特征是由具有相对低杨氏系数的弹性材料所构成。
3.根据权利要求2所述的半导体器件,其中所述弹性材料包含光刻胶、聚酰亚胺或苯并环丁烯。
4.根据权利要求1所述的半导体器件,其中所述重分布层是经由多数个凸块与所述芯片电连接。
5.根据权利要求1所述的半导体器件,其中所述重分布层包含至少一介电层与至少一金属层。
6.根据权利要求1所述的半导体器件,其还包括耦合至所述重分布层的穿硅通孔中介层。
7.根据权利要求6所述的半导体器件,其还包括设置在所述穿硅通孔中介层的底面上的多数个焊锡球。
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