TW533559B - Chip package structure and its manufacturing process - Google Patents

Abstract

A chip package structure and its manufacturing process are disclosed in the present invention. In the invention, a chip is bonded to a glass substrate, and a laminated circuit layer having an external circuit is formed on the chip and the glass substrate. Part of the external circuit is electrically connected to metal pad of the chip and is extended to the region except that above the active surface of the chip for fanning out the metal pad of the chip to the region except that above the active surface of the chip. In addition, the active surface of the chip even has an internal circuit and plural active devices such that signal can be transmitted from an active device to the external circuit via the internal circuit and is transmitted from the external circuit to the other active device via the internal circuit. Furthermore, it is capable of integrating the chips having the same function or different functions in a packaging body so as to make the chips electrically connect with each other through the external circuit.

Description

533559 AS B8 C8 D8 Six-patent patent fan park 2. A chip packaging structure 'at least includes: a broken glass substrate; a plurality of wafers, each of which has an active surface and a corresponding back surface, and each of these The wafers each have a plurality of metal pads, which are disposed on the corresponding active surface, and the wafers are attached to the glass substrate with the back surface; and-a laminated circuit layer is disposed on the glass substrate and the On these chips, the laminated circuit layer has an external circuit, wherein the external circuits are electrically connected to the metal pads of the chips, and at least part of the external circuits extend beyond the active surface of the chip = area In addition, the external circuit has a plurality of bonding pads, which are located on the surface layer of the wiring layer, and each of the bonding pads is electrically connected to one of the metal pads and a part of the wafers respectively. The layer includes at least a patterned wire layer, a dielectric layer 2. A plurality of conductive plugs, and the dielectric layer is disposed on the glass substrate and the wafer, and the pattern The wire layer is disposed on the dielectric layer, and the conductive plugs respectively penetrate the dielectric layer, and are electrically connected to the patterned wire layer and the metal ridges of the chip, wherein the patterned wire layer And the conductive plugs form the external circuit, and once the patterned wire layer is formed. To form the bonding pads, the external circuit further includes at least a passive element, wherein the passive element is guided by the patterned wire layer. It is composed of a part of the structure, in which the material of the patterned wire layer is copper. 142981-1001111.doc This paper size is applicable to Chinese National Standard (CNS) A4 specification (210 X 297 mm) 533559 A8 B8 C8 D8 VI. Patent application park 3 · A chip packaging process, including at least: Provide a glass substrate ' The glass substrate has a plurality of wafers provided, each of the wafers has a corresponding surface and a corresponding one of the back surfaces, and each of the wafers has a plurality of metal pads, which are respectively disposed on the corresponding ones and the wafers are pasted on the back surface Attached to the glass is a first dielectric layer on the active surface of the sheet of the glass substrate, where the first dielectric first through holes respectively correspond to the metal pad dielectric layers; filled with conductive The first through-holes are divided into the first conductive plugs by a material; and a first patterned conductive layer is disposed in the first intermediary, and the first patterned conductive layer passes through the first conductive plugs. Plug, and the metal pads and part of the first patterned wire layer extend to areas beyond the active surface, wherein the first layer further has a plurality of first bonding pads. 4. According to the patent-scope item _3, the glass substrate has a plurality of tHJ holes, the surface of the glass substrate, and the wafers are based on the bottom of one of the recesses. wall. 142981-1001111.doc. This paper size applies to China National Standard Car (CNS) A4 specification (210 X 297 mm). Surface; has an active watch and more complex active surface, respectively, the surface of the substrate and the surface The crystalline electrical layers have a plurality of electrical layers that pass through the first layer to form a plurality of electrical layers, and are electrically connected within a through hole, the wafer, the patterned wire assembly process, and do not dent in the glass. Separately attached on the back

533559 AS B8 C8 D8 6. Application for patent scope 5 · The depth of the recesses encapsulated by the chip as described in item 4 of the patent application scope is equal to the wafers respectively 6. The chip as described in item 4 of the patent application scope The cavities are formed by lithographic etching. 7. The chip package according to item 5 of the scope of the patent application, the glass substrate comprises a patterned glass layer, and the surface is one of the layers of the glass layer, and the glass The layer has a plurality of opening glass layers, and the side walls of the openings and the thermal conductor constitute the cavities, and the wafers are bottom walls of one of the back cavities. '8. The chip package as described in item 7 of the scope of the patent application. The openings are formed on the glass layer by lithographic etching and ending at the moment. 9. The chip package according to item 7 in the scope of the patent application. The thickness of the glass layer is equal to the thickness of the wafers. 10. The chip package according to item 7 in the scope of the patent application. The material of the thermally conductive layer includes metal. 1 1 · The chip package as described in item 3 of the scope of patent application, after attaching the wafers, and configuring the first one, further includes forming a filling layer on the glass substrate and surrounding the wafers. The perimeter, and the pad is aligned with the active surface of the wafers. '142981-10011Il.doc -4- The size of this paper applies to the Chinese National Standard (CMS) A4 specification (210X297 mm). Process, including thickness. Process, in which the process and a thermally conductive layer are far away from the thermal conductivity, which is attached to the process through the surface of the layer, wherein the thermally conductive layer is the etch I process, where the 0 process, the process, and the dielectric layer before Top surface of soil filling layer on this surface 533559

AS B8 C8 D8 6. Scope of patent application 12. The chip packaging process according to item 11 of the scope of patent application, wherein the material of the filling layer includes one of epoxy and polymer. 1 3. The chip packaging process according to item 3 of the scope of patent application, wherein the material of the first dielectric layer includes one of polyimide, phenylcyclobutene, porous dielectric material, and elastic buffer material. . 1 4. The chip packaging process according to item 3 of the scope of patent application, wherein the method of disposing the first patterned wire layer on the first dielectric layer includes one of sputtering, electroplating, and electroless plating. . 15. The chip packaging process as described in item 3 of the scope of patent application, wherein when the first patterned conductive layer is disposed on the first dielectric layer, the first patterned conductive layer can be combined with A conductive material is filled in the first through holes to form the first conductive plugs respectively. 16. The chip packaging process according to item 14 of the scope of patent application, further comprising configuring a patterned protective layer on the first dielectric layer and the first patterned conductive layer, and exposing the first A bonding pad. 1 7. The chip packaging process as described in item 3 of the scope of patent application, further comprising disposing a contact on the first bonding pads, respectively. 1 8. The chip packaging process according to item 17 of the scope of patent application, wherein the types of the contacts include one of a solder ball, a bump, and a pin. 1 9. According to the chip packaging process described in item 3 of the scope of the patent application, after the contacts are respectively arranged on the bonding pads, the packaging structure of the chips is further divided. 20. The chip packaging process as described in item 19 of the scope of patent application, of which 142981-1001111.doc -5- This paper size applies to China National Standard (CNS) A4 specifications (210X 297 mm) · 533559 AS B8 C8 D8, The scope of the patent application is to divide the packaging structure of these wafers by dividing them by a single wafer. 2 1. The chip packaging process as described in item 20 of the scope of patent application, wherein when dividing the packaging structure of these wafers, multiple wafers are used as the unit for division. 2 2. The chip packaging process according to item 3 of the scope of patent application, further comprising: (a) disposing a second dielectric layer on the first dielectric layer and the first patterned wire layer, wherein ' The second dielectric layer has a plurality of second through-holes, which respectively penetrate the second dielectric layer corresponding to the first bonding pad; (b) filling the second through-holes with a conductive material and forming the second through-holes respectively. A plurality of second conductive plugs; and (c) a second patterned conductive layer is disposed on the second dielectric layer, wherein the second patterned conductive layer passes through the second conductive plugs.] • . "Plug, and is electrically connected to the first patterned wire layer, and part of the second patterned wire layer extends to an area other than above the active surface of the chips, wherein the second patterned wire layer It also has a plurality of second bonding pads. 23 · The chip packaging process according to item 22 of the scope of patent application, wherein the material of the second dielectric layer includes one of polyethylenamine, phenylcyclobutene, a porous dielectric material, and an elastic buffer material . 24. The chip packaging process described in item 22 of the scope of application for patents, of which 14298M001111.doc This paper size applies the Chinese National Standard (CNS) A4 specification (210 × 297 mm). 533559

AS B8 C8 D8 6. The scope of patent application. The method of arranging the second patterned wire layer on the second dielectric layer includes one of sputtering, electroplating, and electroless plating. 25. The chip packaging process as described in item 3 of the scope of patent application, wherein when the second patterned conductive layer is disposed on the second dielectric layer, the second patterned conductive layer can be electrically conductive. Material fills the second through holes to form the second conductive plugs. 2 6. The chip packaging process as described in item 22 of the scope of patent application, further comprising a patterned protective layer disposed on the second dielectric layer and the second patterned wire layer, and exposing the Some second bonding pads. 27. The chip packaging process as described in item 22 of the scope of the patent application, further including arranging a contact on the second bonding pads, respectively. 28. The chip packaging process according to item 27 of the scope of patent application, wherein the types of the contacts include one of a solder ball, a bump, and a pin. 29. According to the chip packaging process described in item 27 of the scope of the patent application, after the contacts are respectively disposed on the second bonding pads, the packaging structure of the chips is further divided. . '30. The chip packaging process as described in item 29 of the scope of patent application, wherein when the packaging structure of these wafers is divided, a single wafer is used as a unit for division. 3 1. The chip packaging process described in item 29 of the scope of patent application, wherein 'When dividing the packaging structure of these wafers, multiple wafers are used as the unit for division. 32. The chip packaging process described in item 24 of the scope of patent application, more package 142981-1001111.doc -7- This paper size applies to China National Standard (CNS) A4 specifications (210X297 mm. 533559

AS B3 C8 D8 6. Scope of patent application includes repeating steps (a) to (c) multiple times. 3 3. The chip packaging process according to item 32 of the scope of the patent application, wherein the materials of the second dielectric layers include acetaminophen, phenylcyclobutene, porous dielectric materials, and elastic buffer materials. one. 3 4. The chip packaging process according to item 32 of the scope of patent application, wherein the method of disposing the second patterned wire layers on the second dielectric layers includes sputtering, electroplating, and electroless plating. one. 3 5. The chip packaging process according to item 32 of the scope of patent application, wherein when the second patterned conductive layers are arranged on the second dielectric layers, the second patterns may be filled together. The conductive material of the conductive layer is formed in the second through holes to form the second conductive plugs. 3 6. The chip packaging process as described in item 32 of the scope of the patent application, further comprising configuring a patterned protective layer on the second dielectric layers farthest from the glass substrate and the second patterned conductive layer. Above the glass substrate, and the second bonding pads of the second patterned wire layer that are farthest from the glass substrate are exposed. 37. The chip packaging process according to item 32 of the scope of the patent application, further comprising arranging a contact point on the second bonding pads of the second patterned wire layer farthest from the glass substrate. 3 8. The chip packaging process according to item 37 of the scope of patent application, wherein the types of the contacts include one of a solder ball, a bump, and a pin. 39. As for the chip packaging process described in item 37 of the scope of application for profit, it is divided into 142981-1001111.doc -8- This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm). ASB ^ OD '

After applying the patent, don't arrange the contacts on the bonding pads, and then include the packaging structure that divides the crystals. 40. The chip packaging process as described in the "Scope of Patent Application", wherein the division of the package structure of these wafers is divided by a single wafer. 41. Wafer packaging process. In the case of the sealing structure of these wafers, the wafers are divided into multiple wafers. 4 2. A wafer packaging process, including at least: providing a first glass substrate, the The first glass substrate has a first surface. Known for a plurality of wafers, each of these wafers has an active surface and a corresponding one of the back, and each of these wafers has a plurality of respectively. Metal pads are respectively disposed on the corresponding active surfaces, and the wafers are attached to the first surface of the first glass substrate with the active surfaces; a filling layer is comprehensively formed on the first glass substrate. Overlying the first surface and covering the wafers; planarizing and thinning the filling layer and the wafers; and providing a second glass substrate having a second surface ′ and Glass substrate The second surface is affixed to the filling layer and the wafers; the first glass substrate is patterned to form a plurality of first through holes, 14298M001111.doc. The paper size applies to the Chinese National Standard (CNS) A4 specification (210X297 mm).

533559 AB B3 C8 D8

6. The patent application patent garden respectively exposes the metal pads; filling a conductive material in the first through holes to form a plurality of first conductive plugs; and disposing a first patterned wire layer on the first < On the glass substrate, the first patterned conductive layer is electrically connected to the metal pads through the conductive plugs, and part of the first patterned conductive layer extends to the wafers. The area other than above the active surface 'wherein the first patterned wire layer is more. There are a plurality of first-joint ridges. 43 _ The chip packaging process according to item 42 of the scope of patent application, wherein the material of the filling layer includes one of epoxide and polymer. 44. The chip packaging process according to item 42 of the scope of patent application, wherein the thickness of the first glass substrate is about 2 to 150 micrometers. 45 _ The wafer packaging process according to item 42 of the scope of patent application, wherein after attaching the second glass substrate and before patterning the first glass substrate, the method further includes thinning the thickness of the first glass substrate. 46_ The wafer packaging process described in item 42 of the scope of patent application, wherein the thickness of the first glass substrate after thinning is about 2 ~ 150 microns. 47. The wafer described in item 42 of scope of patent application In a packaging process, a method of disposing the first patterned conductive layer on the first glass substrate includes one of sputtering, electroplating, and electroless plating. 48. The chip packaging process described in item 42 of the scope of patent application, in which I42981-100111I.doc -10- This paper size applies to the Chinese National Standard (CNS) A4 specification (210X297 mm). Binding line 533559

AB β'3 C8 _______ DS ^ ____ VI. When applying for a patent, the park may 'fill' the first patterned conductive layer on the first glass substrate and fill the first patterned conductive layer with the conductive material. The first through holes are formed in the first through holes, respectively. 4 9 · According to the chip packaging process described in item 42 of the patent application scope, wherein the material of the filling layer includes one of epoxide and polymer. 50. The chip packaging process as described in item 42 of the scope of the patent application, further comprising a patterned configuration to protect the first glass substrate and the first patterned wiring layer, which exposes these First bonding pad. 5 1. The chip packaging process as described in item 42 of the application scope further includes separate arrangement-contacts on the first bonding pad of the enamel. 5 2. The chip packaging process as described in item 5 J of the scope of patent application, wherein the types of these contacts include one of a solder ball, a bump, and a pin. 5 3. According to the chip packaging process described in item 5 丨 of the scope of patent application, after disposing the contacts on the bonding pads separately, it further includes a packaging structure that divides the chips. 54. The chip packaging process described in item 53 of the scope of application for patents, wherein when the packaging structure of the chips is divided, a single wafer is used as a unit for division. 5 5. The chip packaging process as described in item 53 of the scope of the patent application, wherein when dividing the packaging structure of these wafers', division is performed by using a plurality of wafers as a unit. '56. The chip packaging process as described in item 44 of the scope of patent application, including: 142981-1001111.doc This paper size is applicable to China National Standard (CNS) A4 specifications (210 X 297 mm), patent application park ( a) A dielectric layer is disposed on the first glass substrate and the first patterned wire layer, wherein 'the dielectric layer has a plurality of second through holes' which respectively penetrate the dielectric layer corresponding to the first bonding pad. An electrical layer; (b) filling a conductive material into the second through holes to form a plurality of second conductive plugs respectively; and (c) disposing a second patterned wire layer on the dielectric layer, wherein the The second patterned conductive layer is electrically connected to the first patterned conductive layer through the second conductive plugs, and a portion of the second patterned conductive layer extends above the active surfaces of the wafers. In other regions, the second patterned wire layer further has a plurality of second bonding pads. Among them. Porous. 5 7. The chip packaging process as described in Item 56 of the scope of the patent application. The material of the dielectric layer includes one of polyethylenamine and phenylcyclobutene-based dielectric material layer elastic buffer material. 58. The method for disposing the second patterned wire layer on the second dielectric layer in the chip package manufacturing process described in item 56 of the scope of patent application includes sputtering, yes, electro-electric ore and electroless plating— . 59. The chip packaging process according to item 56 of the scope of patent application, wherein when the second patterned conductive layer is disposed on the dielectric layer, the conductive material of the second patterned conductive layer can be filled together. Enter the Du 1 flute-two through holes, and form the second conductive plugs respectively. 60. The chip packaging process described in item 56 of the scope of the patent application, further includes configuring a patterned protective layer on the second dielectric layer and the second figure 12-142981-1001111.doc This paper size applies Chinese national standards (CNS > A4 specification (210X297 mm) 533559 A8 B8 C8 D8 VI. Apply for patent on the patented wire layer and expose these second junctions. 61. As described in item 56 of the scope of patent application The chip packaging process further includes disposing a contact on the second bonding pads. 62. The chip packaging process as described in item 61 of the patent application scope, wherein the types of the contacts include solder balls and bumps And one of the pins. 63 · According to the chip packaging process described in item 61 of the scope of patent application, after the contacts are respectively arranged on the second bonding pads, the packaging structure of the chips is further divided. 64. The wafer. Packaging process as described in item 63 of the scope of patent application, wherein when the packaging structure of these wafers is divided, a single wafer is used as the unit. 65. Said chip packaging process, When dividing the packaging structure of these wafers, the division is performed by using multiple wafers as a unit. / 66 · The wafer packaging process described in item 56 of the scope of patent application, including repeating steps (a) to (c) Plural times. 67. The chip packaging process as described in item 66 of the scope of patent application, wherein the materials of the dielectric layers include polyethylenamine, phenylcyclobutene, porous dielectric materials, and elastic buffer materials. 68. The chip packaging process according to item 66 of the scope of patent application, wherein the method of disposing the second patterned conductor layers on the dielectric layers includes sputtering, electroplating, and electroless plating. One of them. 69. The chip packaging process described in item 66 of the scope of application for patents, in which \ 142981-1001111.doc -13- This paper size applies to the Chinese National Standard (CNS) A4 specification (210X 297 mm). 533559 A8 B8 C8 D8 6. Scope of patent application When the second patterned conductive layers are arranged on the dielectric layers, the conductive materials of the second patterned conductive layer may be filled in the second patterned conductive layers together. Through the holes to form the second 70. The chip packaging process described in item 66 of the scope of patent application, further comprising a patterned protective layer disposed on the second dielectric layers farthest from the glass substrate and the second patterned The second bonding pads which are the farthest from the glass substrate and are exposed from the second patterned conductive layer are the second bonding pads which are the farthest from the glass substrate. 7 1. As described in item 66 of the scope of patent application The chip packaging process further includes arranging a contact point on the second patterned conductive wire layer farthest from the second bonding pad of the glass substrate. 72. The chip packaging process according to item 71 of the scope of patent application, wherein the types of the contacts include one of a solder ball, a bump, and a pin. 73 · According to the chip packaging process described in item 71 of the scope of patent application, after the contacts are arranged on the bonding pads, respectively, the packaging structure for dividing the chips is further included. 74. The chip packaging process as described in item 73 of the scope of the patent application, wherein when the paired structure of the wafers is divided, the single wafer is used as the unit for division. 75. The wafer packaging process described in item 73 of the scope of the patent application, wherein when the packaging structure of the wafers is divided, multiple wafers are used as the unit for division. 76. — A kind of chip packaging process, including at least: 142981-1001111.doc-14- This paper size is applicable to China National Standard (CNS) A4 specification (210X297 mm). 533559 A8 B8 C8 __D8____ 6. Application scope A first glass substrate, the first glass substrate having a first surface; at least one wafer is selected, the wafer has an active surface and a corresponding back surface, and the wafer further has a plurality of solder pads arranged on the wafer; The active surface, and attaching the wafer to the first surface of the first glass substrate with the active surface; forming a first filling layer on the first surface of the first glass substrate comprehensively, and Covering the wafer; 'planarizing and thinning the first filling layer and the wafer; providing a second glass substrate' The second glass substrate has a second surface, and the second glass substrate is formed on the second surface Attached to the first filling layer and the wafer; removing the first filling layer and the first glass substrate; disposing a first dielectric layer on the surface of the glass substrate and the active surface of the wafer 'among them The first dielectric layer has a plurality of first through holes, which respectively penetrate the first dielectric layer in response to some metal rhenium; a conductive material is filled in the first through holes to form a plurality of first conductive holes, respectively. A plug; and disposing a first patterned wire layer on the first dielectric layer, wherein the first patterned wire layer passes through the first conductive plugs within the first through holes, and It is electrically connected to the metal pads, and part of the first patterned wire layer is extended to the main part of the chip 142981-1001111.doc .-15- _ This paper size applies to China National Standard (CNS) A4 specifications ( 210X297 mm) .: ''

A BCD 533559 6. Scope of patent application The area other than above the moving surface, wherein the first patterned wire layer further has a plurality of first bonding pads. 77. The chip packaging process described in item 7'6 of the scope of patent application, wherein the glass substrate further has a plurality of recesses, which are recessed on the surface of the glass substrate, respectively, and the wafers are respectively pasted on the back surface. Attached to the bottom wall of one of these pockets. 78. The chip packaging process described in item 77 of the scope of the patent application, wherein the depths of the cavities are respectively equal to the thickness of the wafers. 79. The chip packaging process according to item 77 of the scope of the patent application, wherein the recesses are formed by means of lithographic etching. 80. The chip packaging process as described in item 76 of the patent application scope, wherein the glass substrate comprises a patterned glass layer and a thermally conductive layer superimposed, and the surface is a distance from the glass layer One surface of the thermally conductive layer, and the glass layer has a plurality of openings penetrating through the glass layer, and the side walls of the openings and the surface of the thermally conductive layer form the recesses respectively, and the wafers are attached with the back surface On the bottom wall of one of the cavities. 8 1 · The chip packaging process according to item 80 of the scope of patent application, wherein the openings are formed on the glass layer by lithographic etching, and the thermal conductive layer is used as an etching end point. 8 2. The wafer packaging process according to item 80 of the scope of patent application, wherein the thickness of the glass layer is equal to the thickness of the wafers. 83. The chip packaging process as described in item 80 of the scope of application for patents, of which 142981-1001111.doc-16- This paper size applies to China National Standard (CNS) A4 specifications (210X297 mm): 533559 A8 B8 C8 D8. Scope of patent application The material of the thermally conductive layer includes metal. -84. The chip packaging process according to item 76 of the scope of patent application, wherein the material of the first dielectric layer includes one of polyimide, phenylcyclobutene, porous dielectric material and elastic buffer material . 85. The chip packaging process according to item 76 of the scope of patent application, wherein the method of disposing the first patterned conductive layer on the first dielectric layer includes one of sputtering, electroplating, and electroless plating. 86. The chip packaging process according to item 76 of the scope of patent application, wherein when the first patterned conductive layer is disposed on the first dielectric layer, the first patterned conductive layer can be combined with the first patterned conductive layer. A conductive material is filled in the first through holes, and the first conductive plugs are respectively formed. 8 7. The wafer / chip packaging process as described in item 76 of the scope of patent application, further comprising configuring a patterned protective layer on the first dielectric layer and the first patterned wire layer 5 and exposing the Some first joints. 88. The chip packaging process described in item 76 of the scope of the patent application, further includes disposing a contact on the first bonding pads, respectively. 89. The chip packaging process according to item 88 of the scope of patent application, wherein the types of the contacts include one of a solder ball, a wafer, a block, and a pin. 90. According to the chip packaging process described in item 88 of the scope of the patent application, after the contacts are respectively disposed on the bonding pads, the packaging structure of the chips is further divided. 9 1. The chip packaging process described in item 90 of the scope of application for patents, wherein when dividing the packaging structure of these chips, a single chip is used as a unit! 142981-1001111.doc -17- This paper size applies to China National Standard (CNS) Α4 specification (210 X 297 mm). 533559 A8 B8 C8 D8 -18 ·, divided by the scope of patent application. 92. The chip packaging process described in item 90 of the scope of the patent application, wherein when the packaging structure of the wafers is divided, multiple wafers are used as the unit for division. 93. The chip packaging process as described in item 76 of the scope of patent application, further comprising: (a) configuring a second dielectric layer on the first dielectric layer and the first patterned wire layer, wherein the first The two dielectric layers have a plurality of second through holes, which respectively penetrate the second dielectric layer corresponding to the first bonding pad; (b) Filling the second through holes with a conductive material to form a plurality of each A second conductive plug; and (c) disposing a second patterned conductive layer on the second dielectric layer, wherein the second patterned conductive layer is connected to the first conductive plug through the second conductive plugs. A patterned wire layer is electrically connected, and a portion of the second patterned wire layer extends beyond the active surface of the wafers. The second patterned wire layer further includes a plurality of second bonding pads. . 94. The chip packaging process according to item 93 of the scope of patent application, wherein the material of the second dielectric layer includes one of polyethylenamine, phenylcyclobutene, a porous dielectric material, and an elastic buffer material . 95. The chip packaging process as described in item 93 of the scope of patent application, wherein the second patterned wire layer is disposed on the second dielectric layer 142981-1001111.doc This paper size applies Chinese national standards ( CNS) A4 specification (210X297 mm). Decoration line 533559 B8 C8 D8 6. The patent application method includes one of sputtering, electroplating and non-electric clock. 96 As described in item 93 of the scope of patent application Chip packaging process »Wherein, when the second patterned conductive layer is disposed on the second dielectric layer, the conductive material of the second patterned conductive layer can be filled into the second through holes, and The second conductive plugs are respectively formed. 97. The chip packaging process 9 described in item 93 of the patent application scope further includes configuring a patterned protective layer on the second dielectric layer and the second patterned wire layer. The second bonding pads 098 are exposed on top. The chip packaging process 9 described in item 93 of the patent application scope further includes disposing a contact on the second bonding pads respectively. 99. The chip packaging process described in item 98 of the scope of patent application, wherein the types of these contacts include one of fresh balls, bumps and pins. 0100. The chip packaging process described in item 98 of scope of patent application After the contacts are respectively disposed on the second bonding pads, a package structure for dividing the chips is further included. 101. The wafer packaging process as described in item 100 of the scope of the patent application) In the packaging structure of the wafers, the wafers are divided by a single wafer. 102 The wafer packaging process described in item 100 of the scope of the patent application. J When dividing the packaging structure of these wafers, the wafers are divided in units of multiple wafers. 103. The chip packaging process described in item 93 of the scope of patent application) further includes repeating steps (a) to (c) multiple times. 142981-1001111.doc '-19- This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X 297 mm). 533559 A8 B8 C8 D8 VI. Patent application park 104. As described in the scope of the patent application In the chip packaging process, the materials of the second dielectric layers include one of polyethylenamine, phenylcyclobutene, a porous dielectric material, and an elastic buffer material. 105. The chip packaging process as described in item 103 of the scope of patent application, wherein the method of disposing the second patterned conductive layer on the second dielectric layers includes sputtering, electroplating, and electroless plating. 10. Packing 106. The chip packaging process as described in item 103 of the scope of the patent application, wherein the 'second enclosure conductive layers are disposed on the second dielectric layers' may be filled in together The conductive materials of the second patterned wire layers are formed in the second through holes, and the second conductive plugs are respectively formed. Order 107. The chip packaging process as described in item 103 of the scope of patent application, further includes configuring a patterned protective layer on the second dielectric layer farthest from the glass substrate and the second patterned wire layer. Those farthest from the glass substrate, and the second bonding pads of the second patterned wire layer farthest from the glass substrate are exposed. Farther one »The most.’. In the course of the process of layering its installation line, foot, seal and guide. The pinned top sheet and the crystal block cushion block are inscribed in two, the second item in the ball item is fresh, the first item is 03. Some 08 include 1 point, and the first packet is the first state of the first round. Zhe Fan Fan Ban Ban's spear with a spear point, special glasses, special points, please subdivide them, please apply for them should be included and included. »-20- 142981-1001111.doc This paper size applies to Chinese National Standard (CNS) A4 (210 X 297 mm). AS B8 C8 D8 Patent Application Park 11 10. As described in the 108th patent application In the wafer packaging process, after the contacts are respectively disposed on the bonding pads, the packaging structure of the wafers is further divided. 111 • The chip packaging process as described in item 110 of Shenyan's patent scope, in which the packaging structure of these wafers is divided by a single wafer or one of multiple wafers as a unit. 112. A chip packaging structure, including at least: a glass substrate;-a chip set 'the chip set has an active surface and a corresponding back side' and the chip set further has a plurality of metal pads, which are arranged in the On the active surface, and the chipset is attached to the glass substrate with the back surface; a filling layer. Formed on the glass substrate and surrounding the chipset, and the height of the filling layer is Aligned to the height of the active surface of the chipset; a thin glass layer is disposed on the filling layer and the chipset, wherein the thin glass layer has a plurality of first conductive plugs, which are electrically connected to the One of the metal plutoniums; and a laminated circuit layer disposed on the thin glass layer, the laminated circuit layer having an external circuit, wherein the external circuits are electrically connected to the chipset via the conductive inserts. Some metal plutonium, and at least part of the external circuit extends beyond the active surface of the chipset 'and the external circuit has a plurality of joints -21-14298M001111.doc 533559 A8 B8, C8, and D8. Patent-applied pads are located on the surface layer of the multilayer circuit layer, and each of the bonding pads is electrically connected to one of the metal pads of the chipset, wherein the multilayer circuit layer includes at least A patterned wire layer is arranged on the thin glass layer, and the patterned wire layer and the metal pads of the chipset are electrically connected through the first conductive plugs, wherein The patterned wire layer and the first conductive plugs form the external circuit, and the patterned wire layer forms the bonding pads. The external circuit further includes' at least one passive component, wherein the passive component is formed by the Part of the structure of the patterned wire layer, in which the material of the patterned wire layer is copper • 22-14298M001111.doc This paper size applies to the Chinese National Standard (CNS) A4 specification (210X297 mm)