JP5188426B2 - 半導体装置及びその製造方法、電子装置 - Google Patents
半導体装置及びその製造方法、電子装置 Download PDFInfo
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- JP5188426B2 JP5188426B2 JP2009061271A JP2009061271A JP5188426B2 JP 5188426 B2 JP5188426 B2 JP 5188426B2 JP 2009061271 A JP2009061271 A JP 2009061271A JP 2009061271 A JP2009061271 A JP 2009061271A JP 5188426 B2 JP5188426 B2 JP 5188426B2
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- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
Description
本発明の他の観点によれば、電極パッドが設けられた電極パッド形成面、及び該電極パッド形成面の反対側に位置する背面を有する電子部品を準備し、前記電子部品の背面及び側面を、前記電極パッド形成面を露出する多層構造体形成面を有する封止樹脂により封止する工程と、前記電極パッド形成面、及び前記多層構造体形成面に、積層された複数の絶縁層よりなる積層体と、前記電極パッド形成面、及び前記多層構造体形成面と接触する前記積層体の第1の面とは反対側に位置する前記積層体の第2の面に設けられた外部接続用パッドと、前記積層体に内設され、前記電極パッド及び前記外部接続用パッドと直接接続された配線パターンと、を有する多層配線構造体を形成する工程と、前記封止樹脂の前記多層構造体形成面とは反対側の面を研削し、前記電子部品の背面を露出する工程と、を有し、前記多層配線構造体を形成する工程は、前記封止樹脂と接触する第1の絶縁層の第1の面とは反対側に位置する前記第1の絶縁層の第2の面に配置された配線を有するように前記配線パターンを形成する工程と、前記封止樹脂及び前記第1の絶縁層を貫通すると共に、前記配線を露出する貫通孔を設ける工程と、前記貫通孔に、前記配線と接続され、高さが前記封止樹脂の厚さと前記第1の絶縁層の厚さとを加えた値よりも小さくなるように構成された導電部材を設ける工程と、を含むことを特徴とする半導体装置の製造方法が提供される。
図2は、本発明の実施の形態に係る電子装置の断面図である。
11,12 半導体装置
13 内部接続端子
15,16,92 電子部品
15A,16A 電極パッド形成面
15B,16B 背面
15C,16C 側面
18 封止樹脂
18A 多層配線構造体形成面
18B,56A,56B,57A,57B,92A,111A,112A 面
19 多層配線構造体
21〜23,137〜139 貫通孔
27〜29 導電部材
32 外部接続端子
35,36,38,39,106 電極パッド
27A,28A,29A,35A,36A,38A,39A,46A,47A,48A,49A 接続面
45 積層体
46〜49 外部接続用パッド
51〜54,101 配線パターン
55,102,103 ソルダーレジスト層
55A,55B,55C,55D,102A,103A,115〜117,121〜124,126〜129,131〜133 開口部
56,57 絶縁層
61,62,64,66,69,71,74,78 ビア
63,68,73,77 配線
81〜83 凹部
91 配線基板
93 モールド樹脂
94 金属ワイヤ
96 基板本体
96A 上面
96B 下面
97,98 パッド
111 支持体
112 接着剤
136 印刷用マスク
141 導電性ペースト
Claims (5)
- 電極パッドが設けられた電極パッド形成面、及び該電極パッド形成面の反対側に位置する背面を有する電子部品と、
前記電極パッド形成面を露出する多層構造体形成面と、該多層構造体形成面の反対側に位置すると共に、前記背面を露出する面とを有し、前記電子部品の側面を封止する封止樹脂と、
前記電極パッド形成面、及び前記多層構造体形成面に設けられ、積層された複数の絶縁層よりなる積層体と、前記電極パッド形成面、及び前記多層構造体形成面と接触する前記積層体の第1の面とは反対側に位置する前記積層体の第2の面に設けられた外部接続用パッドと、前記積層体に内設され、前記電極パッド及び前記外部接続用パッドと直接接続された配線パターンと、を有する多層配線構造体と、を備え、
前記配線パターンは、複数の前記絶縁層のうち、前記封止樹脂と接触する第1の絶縁層に設けられ、前記第1の絶縁層の第1の面とは反対側に位置する前記第1の絶縁層の第2の面に配置された配線を有し、
前記封止樹脂及び前記第1の絶縁層を貫通すると共に、前記配線を露出する貫通孔を設け、
前記貫通孔に、前記配線と接続され、高さが前記封止樹脂の厚さと前記第1の絶縁層の厚さとを加えた値よりも小さくなるように構成された導電部材を設けたことを特徴とする半導体装置。 - 前記導電部材は、導電性ペーストよりなることを特徴とする請求項1記載の半導体装置。
- 前記多層配線構造体の厚さは、前記封止樹脂の厚さ及び前記電子部品の厚さよりも薄いことを特徴とする請求項1又は2記載の半導体装置。
- 請求項1〜3のうち、いずれか1項記載の半導体装置と、
内部接続端子を介して、前記半導体装置と電気的に接続される他の半導体装置と、を備えたことを特徴とする電子装置。 - 電極パッドが設けられた電極パッド形成面、及び該電極パッド形成面の反対側に位置する背面を有する電子部品を準備し、前記電子部品の背面及び側面を、前記電極パッド形成面を露出する多層構造体形成面を有する封止樹脂により封止する工程と、
前記電極パッド形成面、及び前記多層構造体形成面に、積層された複数の絶縁層よりなる積層体と、前記電極パッド形成面、及び前記多層構造体形成面と接触する前記積層体の第1の面とは反対側に位置する前記積層体の第2の面に設けられた外部接続用パッドと、前記積層体に内設され、前記電極パッド及び前記外部接続用パッドと直接接続された配線パターンと、を有する多層配線構造体を形成する工程と、
前記封止樹脂の前記多層構造体形成面とは反対側の面を研削し、前記電子部品の背面を露出する工程と、を有し、
前記多層配線構造体を形成する工程は、
前記封止樹脂と接触する第1の絶縁層の第1の面とは反対側に位置する前記第1の絶縁層の第2の面に配置された配線を有するように前記配線パターンを形成する工程と、
前記封止樹脂及び前記第1の絶縁層を貫通すると共に、前記配線を露出する貫通孔を設ける工程と、
前記貫通孔に、前記配線と接続され、高さが前記封止樹脂の厚さと前記第1の絶縁層の厚さとを加えた値よりも小さくなるように構成された導電部材を設ける工程と、を含むことを特徴とする半導体装置の製造方法。
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JP2009061271A JP5188426B2 (ja) | 2009-03-13 | 2009-03-13 | 半導体装置及びその製造方法、電子装置 |
US12/722,769 US8294253B2 (en) | 2009-03-13 | 2010-03-12 | Semiconductor device, electronic device and method of manufacturing semiconductor device, having electronic component, sealing resin and multilayer wiring structure |
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