JP5870626B2 - 半導体装置及び半導体装置の製造方法 - Google Patents
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
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- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 229910002092 carbon dioxide Inorganic materials 0.000 description 1
- 239000001569 carbon dioxide Substances 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 1
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- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
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- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
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- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
- H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
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- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1047—Details of electrical connections between containers
- H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
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Description
図1A〜図1Pを参照して、実施例1による半導体装置の製造方法について説明する。
次に、図3A〜図3Eを参照して、実施例2による半導体装置の製造方法について説明する。以下、実施例1との相違点に着目して説明し、同一の構成については、説明を省略する場合がある。
図4に、実施例3による半導体装置の断面図を示す。再構築ウエハ17及び再配線層35からなる半導体装置55が、複数枚積み重ねられている。半導体装置55の各々は、実施例1または実施例2による方法で作製されたものである。
11 粘着フィルム
12 半導体チップ
13 パッド
14 回路形成面
15 支持ベース
15a 樹脂組成物
17 再構築ウエハ
18 第1の表面
19 第2の表面
20 絶縁膜
21 開口
24 シード層
25 フォトレジストパターン
26 開口
28 銅のめっき膜
30 配線
31 パッド
33 絶縁膜
34 露出パッド
35 再配線層
37 フォトレジスト膜
38 マーカ
40 スルーホール
43 導電膜
43a 導電ビア
43b 配線
43c パッド
50 保護フィルム
55 半導体装置
57 はんだ
Claims (7)
- 半導体チップ、及び該半導体チップに固定され、該半導体チップの縁よりも外方まで配置された絶縁性の樹脂からなり、無機フィラーを含有する支持ベースを含む再構築ウエハと、
前記再構築ウエハの一方の表面である第1の表面に形成され、絶縁性樹脂からなる絶縁膜、前記絶縁膜内に配置された複数の配線、前記絶縁膜内であって、前記半導体チップとは重ならない位置に配置された金属製の複数の第1のパッド、及び前記絶縁膜の表面に露出する金属製の複数の第2のパッドを含む再配線層と、
前記再構築ウエハの前記第1の表面とは反対側の第2の表面から、前記支持ベースを貫通して、前記第1のパッドまで達するスルーホールと、
前記スルーホール内に配置され、前記第1のパッドに接続された導電ビアと
を有する半導体装置。 - 前記第1のパッドの厚さが5μm以上である請求項1に記載の半導体装置。
- 前記第1のパッドと前記第2のパッドとが前記配線で接続されている請求項1または2に記載の半導体装置。
- 半導体チップ、及び該半導体チップに固定され、該半導体チップの縁よりも外方まで配置された絶縁性の樹脂からなり、無機フィラーを含有する支持ベースを含む再構築ウエハを形成する工程と、
前記再構築ウエハの一方の表面である第1の表面に、絶縁性の樹脂からなる第1の絶縁膜を形成する工程と、
前記第1の絶縁膜の上に、複数の配線、前記半導体チップとは重ならない位置に配置された金属製の第1のパッドを形成する工程と、
前記再構築ウエハの、前記第1の表面とは反対側の第2の表面にレーザビームを入射させることにより、前記支持ベースに、前記第1のパッドまで達するスルーホールを形成する工程と、
前記スルーホール内に、前記第1のパッドに接続された導電ビアを形成する工程と
を有する半導体装置の製造方法。 - 前記再構築ウエハを形成する工程は、
仮の支持体の支持面上に前記半導体チップを、前記半導体チップの回路形成面が前記仮の支持体に対向する向きで仮固定する工程と、
前記半導体チップ、及び前記仮の支持体の支持面を、樹脂組成物で覆う工程と、
前記樹脂組成物及び前記半導体チップを、前記仮の支持体から引き離す工程と、
前記樹脂組成物を硬化させることにより、前記支持ベースを形成する工程と、
を含む請求項4に記載の半導体装置の製造方法。 - 前記再構築ウエハを形成する工程で形成された前記再構築ウエハの前記支持ベースは、前記半導体チップの回路形成面とは反対側の表面及び側面に密着しており、
前記第1のパッドを形成した後、前記スルーホールを形成する前に、前記再構築ウエハを、前記第2の表面から、前記半導体チップが露出するまで研磨する工程を、さらに含む請求項4または5に記載の半導体装置の製造方法。 - 前記第1のパッドの厚さが5μm以上である請求項4乃至6のいずれか1項に記載の半導体装置の製造方法。
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