TW201906024A - 半導體封裝及半導體封裝的製程方法 - Google Patents

半導體封裝及半導體封裝的製程方法

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Publication number
TW201906024A
TW201906024A TW106140641A TW106140641A TW201906024A TW 201906024 A TW201906024 A TW 201906024A TW 106140641 A TW106140641 A TW 106140641A TW 106140641 A TW106140641 A TW 106140641A TW 201906024 A TW201906024 A TW 201906024A
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Taiwan
Prior art keywords
layer
wafer
carrier
semiconductor package
semiconductor
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TW106140641A
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English (en)
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TWI677035B (zh
Inventor
徐宏欣
林南君
張簡上煜
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力成科技股份有限公司
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Publication of TW201906024A publication Critical patent/TW201906024A/zh
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Publication of TWI677035B publication Critical patent/TWI677035B/zh

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Abstract

形成半導體封裝的方法包含提供半導體晶圓，於半導體晶圓上形成黏著層，切割半導體晶圓以形成複數個晶片。每一晶片具有複數個柱狀凸塊及自黏著層切割之黏著層片。將每一晶片之黏著層片黏著至載體的第一表面，形成模封層以包封晶片及載體，研磨模封層以顯露出複數個柱狀凸塊並產生研磨面，形成互連結構，且互連結構包含位於研磨面上的複數個線路，每一線路電性連接至對應晶片的柱狀凸塊。切割互連結構及模封層以形成複數個半導體封裝，每一半導體封裝包含對應線路及至少一晶片。

Description

半導體封裝及半導體封裝的製程方法
本發明係有關於一種半導體晶片封裝，特別是一種扇出型的半導體封裝。
晶圓級扇出封裝(wafer level fan-out packaging)製程為現今常見的技術。在晶圓級扇出封裝的製程中，設置有積體電路的晶圓會經過一系列的程序，例如研磨、焊晶、模封…等等，最終則會被切割為成品。晶圓級扇出封裝被視為適合用在小尺寸及高速的封裝。然而，由於環氧模封材料(epoxy molding compound，EMC)的牽引力會導致晶片位移，因此常造成晶圓級扇出封裝的成品品質下降。
本發明之一實施例提供一種形成半導體封裝的方法，方法包含提供半導體晶圓，於半導體晶圓上形成黏著層，切割半導體晶圓以形成複數個晶片。每一晶片具有複數個柱狀凸塊(pillar bump)及自黏著層切割之黏著層片。將每一晶片之黏著層片黏著至載體的第一表面，形成模封層以包封晶片及載體，研磨模封層以顯露出柱狀凸塊並產生研磨面，形成互連結構。互連結構包含位於研磨面上的複數個線路，每一線路電性連接至對應晶片的複數個柱狀凸塊。切割互連結構及模封層以形成複數個半導體封裝，每一半導體封裝包含對應線路及至少一晶片。
本發明另一實施例提供一種半導體封裝，半導體封裝包含載體、至少一晶片、模封層及互連結構。
每一晶片透過黏著層片黏著於載體的第一表面，且每一晶片具有複數個柱狀凸塊。模封層包封晶片及載體。互連結構形成於模封層的研磨面，並電性連接於晶片的柱狀凸塊。
第1至14圖說明根據本發明第一實施例所製造之半導體封裝於各步驟中的對應剖面圖。
在第1圖中，形成半導體封裝的方法可先提供半導體晶圓110。半導體晶圓110可具有複數個導電接墊120及絕緣層130。絕緣層130可形成於半導體晶圓110的主動面上。導電接墊120可形成於絕緣層130的開口中。導電接墊120可電性連接至半導體晶圓110上所形成的積體電路。
在第2圖中，複數個柱狀凸塊140可形成於導電接墊120上。介電層150可形成在絕緣層130上。柱狀凸塊140的高度可大於介電層150的高度。柱狀凸塊140可為銅、金或銅的合金。介電層150可為聚醯亞胺層(Polyimide，PI)。
如第3圖所示，黏著層160可以透過塗佈製程、網版印刷(screen printing)、鋼板印刷(stencil printing)或壓合製程(lamination process)形成於半導體晶圓110的下側(非主動面)。黏著層160對矽可產生良好的黏性。黏著層160可為B階段(B-stage)材質、環氧化物、矽氧樹脂、ABF(Ajinomoto build-up film)或前述各項的任意組合。
在第4圖中，在黏著層160形成於半導體晶圓110的下側之後，切割機具210便可用來將半導體晶圓110切割成複數個晶片200。每一晶片200包含複數個柱狀凸塊140及自黏著層160切割下來的黏著層片162。
如第5圖所示，每一晶片200可利用其黏著層片162維持性地黏著至載體300的第一表面310，使得晶片200能夠維持性地設置於載體300的第一表面310。載體300本身並不具有電性功能(例如傳導電壓或電流)。載體300可為玻璃、矽氧化物、其熱膨脹係數(coefficient of thermal expansion，CTE)與半導體晶圓110相近的材料，或前述各項的任意組合。載體300的導熱率可大於半導體晶圓110的導熱率。載體300上用以承載晶片200的承載區域可為方形、長方形或圓形。當晶片200放置於載體300的第一表面310時，可使晶片200的黏著層片162固化以將晶片200固定於載體300的第一表面310。如此一來，晶片200在後續的模封程序中就不會產生位置偏移。在後續的機械研磨拋光程序或化學機械拋光(chemical mechanical polishing，CMP)中，即可將黏著層片162自晶片200移除。
如第6圖所示，在每一晶片200的黏著層片162黏著至載體300的第一表面310後，可透過模封程序來形成模封層320以包封住晶片200及載體300。模封層320可為環氧模造物(epoxy molding compound，EMC)。由於晶片200會被固化的黏著層片162固定於載體300的第一表面310，且載體300的熱膨脹係數可幾乎與晶片200本體連帶黏著層片162的熱膨脹係數相等，因此在第一表面310上的晶片200不至於在形成模封層320時受到模封材料的牽引力影響。如此一來，就無需再對晶片200的位置偏移進行補償，進而能夠提升微影(lithography)製程的精準度。
如第7圖所示，模封層320可被研磨至顯露出柱狀凸塊140並形成研磨面321。
如第8圖所示，聚醯亞胺層332可形成於模封層320的研磨面321，並使部分的柱狀凸塊140顯露於表面。
如第9圖所示，重配置線路層(redistribution layer，RDL)334可形成於聚醯亞胺層332及柱狀凸塊140上。重配置線路層334可電性連接至柱狀凸塊140。根據最終半導體封裝的線路複雜程度，也可設置超過一層的重配置線路層334。
如第10圖所示，可於重配置線路層334上形成另一層的聚醯亞胺層336，並使部分的重配置線路層334露出。
如第11圖所示，球下金屬層338可形成於聚醯亞胺層336及部分露出於聚醯亞胺層336的重配置線路層334上。如此一來，包含聚醯亞胺層332、重配置線路334、聚醯亞胺層336及球下金屬層338的互連結構330便可形成於模封層320的研磨表面321上。互連結構330包含複數個線路340。每一個線路340都可電性連接至對應之晶片200的柱狀凸塊140。
如第12圖所示，包覆層360可形成於載體300的第二表面312。包覆層360可由網版印刷(screen printing)、鋼板印刷(stencil printing)或壓合製程(lamination process)來形成。包覆層360的材質可為環氧材料、矽氧材料、ABF(Ajinomoto build-up film)、晶背保護膠帶(LC tape)或其他與矽具有良好接合能力且能夠適用於後續雷射標印程序以在包覆層360上形成晶片方向標記及裝置資訊標記的材料。利用包覆層360，就能夠在封裝切割的程序中避免產生剝離或裂痕等問題。此外，包覆層360還可減少因為模封層320、聚醯亞胺層332及336以及重配置線路層334而產生的封裝翹曲。在本發明的有些實施例中，載體300可在形成包覆層360之前，先進行薄化，以減少最終半導體封裝的厚度。
在第13圖中，複數個焊接球350可形成於互連結構330的線路340上。舉例來說，焊接球350可形成於球下金屬層338，並可經由線路340電性連接至柱狀凸塊140。
如第14圖所示，切割機具410可用來切割互連結構330中的聚醯亞胺層332及336、模封層320、載體300及包覆層360以形成複數個半導體封裝400。每一個半導體封裝400可包含至少一晶片200及對應的線路340。每一半導體封裝400可為扇出結構的封裝，但本發明並不以此為限。
第15至18圖為本發明第二實施例之方法所製造之半導體封裝於各步驟中的對應剖面圖。
如第15圖所示，在使用切割機具410之前，並在互連結構330形成以後，可將載體300及黏著層片162移除。載體300可透過乾式蝕刻、溼式蝕刻、研磨程序、拋光程序或化學機械拋光(chemical mechanical polishing，CMP)等方式去除。黏著層片162可透過機械研磨程序、拋光程序、化學機械拋光或者選擇性蝕刻的方式去除。載體300可被部分研磨或全部研磨。若載體300被完全研磨，則黏著層片162甚至是晶片200的的部分也可能被研磨以減少最終半導體封裝的厚度。在本實例中，載體330會被研磨至顯露出晶片200的非主動面220。非主動面220與互連結構330位於相反兩側。
如第16圖所示，在移除載體300及黏著層片162之後，包覆層360可形成於晶片200上，並與互連結構330為相對面。
在第17圖中，焊接球350可形成於互連結構330上的線路340。舉例來說，焊接球350可形成於球下金屬層338，並可透過線路340與柱狀凸塊140電性連接。
如第18圖所示，切割機具410可用來切割模封層320及互連結構330的聚醯亞胺層332及336以形成複數個半導體封裝450。切割機具410可進一步切割包覆層360。每一半導體封裝450包含至少一晶片200以及對應的線路340。在本實施例中，半導體封裝450可為扇出結構的封裝，但本發明並不以此為限。
根據本發明的第三實施例，第19至32圖利用剖面圖說明形成半導體封裝的另一方法。第一實施例與第三實施例中所使用的相同符號係代表相同元件。
在第19圖中，可先提供基底500。基底500可由矽製成。光阻504可形成在載體500的第一表面501上。光阻504可作為蝕刻的遮罩以抵抗後續的溼式化學蝕刻或電漿蝕刻以達到選擇性的蝕刻。光阻504可透過塗佈製程、網版印刷、鋼板印刷或壓合製程來形成。此外，當基底500蝕刻完成後，便可利用酸、鹼或溶劑來移除光阻504。
如第20圖所示，基底500的第一表面501上可形成複數個孔穴510。在本實施例中，基底500可為矽晶圓，而孔穴510則可透過溼式化學蝕刻的程序形成。在另外的實施例中，孔穴510也可利用電漿蝕刻的方式形成。當溼式化學蝕刻執行完畢後，孔穴510的穴壁512會朝底往內斜向孔穴510的穴底514。在有些實施例中，第一表面501與孔穴510之穴壁512之間的角度θ可介於50度至60度。如第20圖所示，第一表面501與穴底514會與基底500的晶向平面＜110＞平行，並與基底500的晶向平面＜100＞相垂直。孔穴510的穴壁512則為基底500的晶向平面＜111＞。
如第21圖所示，電磁波干擾(electromagnetic interference，EMI)防護層530可連續性地形成於基底500以覆蓋孔穴510的穴壁512及穴底514。電磁波干擾防護層530可利用物理氣相沉積(physical vapor deposition，PVD)的方式形成於基底500上。電磁波干擾防護層530可包含三個金屬層521、522及523，而金屬層522可形成在金屬層521及523之間。在有些實施例中，金屬層521及523可為鈦金屬(titanium，Ti)，而金屬層522可為銅金屬(copper，Cu)。在另外的實施例中，金屬層521及523可為不鏽鋼(stainless steel，SUS)，而金屬層522可為銅金屬。此外，對準記號(fiducial marks)可形成於電磁波干擾防護層530上，以便後續在接合晶片200與電磁波干擾防護層530時能夠對準。後續的對準程序可能包含全域對準、局部對準或前兩項的結合。基底500及電磁波干擾防護層530可建構出用以承載晶片200的載體550。
在第22圖中，可透過晶片200中的黏著層片162維持性地黏著至載體550中連續的電磁波干擾防護層530以便將晶片200維持性地設置於孔穴510。第22圖中的晶片200可根據第1至第4圖的步驟製造取得。當晶片200被設置在孔穴510時，晶片200的黏著層片162可被固化以將晶片200固定於電磁波干擾防護層530。如此一來，在後續的模封過程中，晶片就能夠保持附著於電磁波干擾防護層530。
如第23圖所示，在晶片200的黏著層片162黏合至載體550之連續的電磁波干擾防護層530之後，可執行模封程序以使模封層320包封住晶片200及載體550。由於透過固化黏著層片162可將晶片200 固定於電磁波干擾防護層530，且基底500的熱膨脹係數實質上可與晶片200的本體連帶黏著層片162的熱膨脹係數相同，因此在電磁波干擾防護層530上的晶片200就不至於在形成模封層320時，受到牽引而移動位置。如此一來，就無需再對晶片200的位置偏移進行補償，進而能夠提升微影製程的精準度。
如第24圖所示，模封層320可被研磨至顯露出柱狀凸塊140並形成研磨面321。在有些實施例中，部分的電磁干擾防護層530及部分的基底500可利用相同的研磨程序一併去除。在部分的電磁波干擾防護層530及部分的基底500被研磨去除後，原先連續的電磁波干擾防護層530就被分為複數個電磁波干擾屏蔽層530A。
如第25圖所示，聚醯亞胺層332可形成於研磨面321上。研磨面321可包含彼此共平面的模封層320的表面、電磁波干擾防護層530的表面、基底500的表面及柱狀凸塊140的表面。
如第26圖所示，重配置線路層334可形成於聚醯亞胺層332及柱狀凸塊140上。根據最終半導體封裝的線路複雜度，重配置線路層334的數量可能不只一層。
如第27圖所示，聚醯亞胺層336可形成於重配置線路層334上，並使部分的重配置線路層334露出。
如第28圖所示，球下金屬層338可形成於聚醯亞胺層336及部分的重配置金屬層334上。如此一來，包含聚醯亞胺層332、重配置線路層334、聚醯亞胺層336及球下金屬層338的互連結構330就可形成於研磨面321上。互連結構330包含複數個線路340，每一個線路340可電性連接至對應晶片200的柱狀凸塊140。
如第29圖所示，薄化程序可將基底500變薄。薄化程序可利用研磨製程或蝕刻製程。
如第30圖所示，包覆層360可形成於基底500的第二表面502。包覆層360可由網版印刷、鋼板印刷或壓合製程來形成，而包覆層360的材質可為環氧材料、矽氧材料、ABF、晶背保護膠帶或其他與矽具有良好接合能力且能夠適用於後續雷射標印程序以在包覆層360上形成晶片方向標記及裝置資訊標記的材料。利用包覆層360，就能夠在封裝切割的程序中避免產生剝離或裂痕等問題。此外，包覆層360還可減少因為模封層320、聚醯亞胺層332及336以及重配置線路層334而產生的封裝翹曲。
如第31圖所示，焊接球350可形成於互連結構330的線路340上。舉例來說，焊接球350可形成於球下金屬338，並經由線路340電性連接至柱狀凸塊140。
如第32圖所示，切割機具410可用來切割至少互連結構330及基底500以形成複數個半導體封裝600。在有些實施例中，互連結構330中的聚醯亞胺層332及336也可被切割機具410切穿。每一個半導體封裝600包含對應的晶片200、用以提供電磁波干擾保護的電磁波干擾屏蔽層530A、部分的基底500及電性連接至晶片200之柱狀凸塊的對應線路340。每一半導體封裝600可為扇出結構，但本發明並不以此為限。
在本發明的第四實施例中，孔穴510可利用電漿蝕刻形成於基底500，而不利用溼式化學蝕刻。第33圖為根據本發明第四實施例所製造的半導體封裝700。半導體封裝700的結構與第32圖中半導體封裝600的結構相似。半導體封裝700與半導體封裝600的主要差異在於半導體封裝700的孔穴510的穴壁512會實質上垂直於孔穴510的穴底514。
第34圖為根據本發明第五實施例所製造的半導體封裝800。半導體封裝800的結構與第32圖所示之半導體封裝600的結構相似。在半導體封裝800中，柱狀凸塊140的高度會大於先前實施例中的柱狀凸塊140的高度。電磁波干擾屏蔽層530A及基底500會被模封層320包覆。若柱狀凸塊140已被模封層320給包覆，則可將模封層320研磨至顯露出柱狀凸塊140並形成研磨面321。然而在電磁波干擾屏蔽 層530A及載體550之基底500還未被研磨時，也可能即足以顯露出柱狀凸塊140並形成研磨面321。互連結構330可形成於模封層320的研磨面321上。包覆層360可形成於基底500的第二表面502。半導體封裝800可藉由切割至少互連結構330、模封層320及載體550來形成。在有些實施例中，互連結構330中的聚醯亞胺層332及336也可被切割機具410切穿。
第35圖為根據本發明第六實施例所製造的半導體封裝900。半導體封裝900的結構與第34圖所示之半導體封裝800的結構相似。半導體封裝900與半導體封裝800的主要差別在於半導體封裝900之孔穴510的穴壁512實質上會垂直於半導體封裝900之孔穴510的穴底514。若柱狀凸塊140已被模封層320給包覆，則可將模封層320研磨至顯露出柱狀凸塊140並形成研磨面321。然而在電磁波干擾屏蔽層530A及載體550之基底500還未被研磨時，也可能即足以顯露出柱狀凸塊140並形成研磨面321。互連結構330可形成於模封層320的研磨面321上。包覆層360可形成於基底500的第二表面502。半導體封裝900可藉由切割至少互連結構330、模封層320及載體550來形成。在有些實施例中，互連結構330中的聚醯亞胺層332及336也可被切割機具410切穿。
在第34圖及第35圖中，由於模封層320會完全包覆電磁波干擾屏蔽層530A，因此電磁波干擾屏蔽層530A與互連結構330之間並無直接接觸，然而本發明並不以此為限，例如在第32圖及第33圖中，電磁波干擾屏蔽層530A也可能接觸至互連結構330，舉例來說，電磁波干擾屏蔽層530A可能會耦接至互連結構330的聚醯亞胺層332，或是電性耦接至互連結構330的重配置線路層334。
根據本發明所提供的實施例，可在晶圓級扇出製程中形成黏著層。半導體晶圓可被切割成複數個晶片，且每個晶片可具有自黏著層切割的黏著層片。在模封程序執行之前，晶片上的黏著層片可被固化以將晶片固定於載體。由於晶片被固化的黏著層片固定在載體上，位於第一表面上的晶片就幾乎不會被模封材料的牽引力影響而移動。如此一來，最終半導體封裝的良率就能夠提升。此外，半導體封裝可包含電磁波干擾屏蔽層以提供電磁波干擾的保護。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
110‧‧‧半導體晶圓
120‧‧‧導電接墊
130‧‧‧絕緣層
140‧‧‧柱狀凸塊
150‧‧‧介電層
160‧‧‧黏著層
162‧‧‧黏著層片
210、410‧‧‧切割機具
200‧‧‧晶片
300‧‧‧載體
310‧‧‧載體的第一表面
312‧‧‧載體的第二表面
320‧‧‧模封層
321‧‧‧研磨面
330‧‧‧互連結構
332‧‧‧聚醯亞胺層
334‧‧‧重配置線路層
336‧‧‧聚醯亞胺層
338‧‧‧球下金屬層
340‧‧‧線路
350‧‧‧焊接球
360‧‧‧包覆層
400、450、600、700、800、900‧‧‧半導體封裝
220‧‧‧非主動面
500‧‧‧基底
501‧‧‧基底的第一表面
502‧‧‧基底的第二表面
504‧‧‧光阻
510‧‧‧孔穴
512‧‧‧孔壁
514‧‧‧孔底
521、522、523‧‧‧金屬層
530‧‧‧電磁波干擾防護層
530A‧‧‧電磁波干擾屏蔽層
第1至14圖為根據本發明第一實施例之方法所製造之半導體封裝於各步驟中的對應剖面圖。 第15至18圖為根據本發明第二實施例之方法所製造之半導體封裝於各步驟中的對應剖面圖。 第19至32圖為根據本發明第三實施例之方法所製造之半導體封裝於各步驟中的對應剖面圖。 第33圖為根據本發明第四實施例之方法所製造之半導體封裝的剖面圖。 第34圖為根據本發明第五實施例之方法所製造之半導體封裝的剖面圖。 第35圖為根據本發明第六實施例之方法所製造之半導體封裝的剖面圖。

Claims (13)

  1. 一種形成半導體封裝的方法，包含： 提供一半導體晶圓； 於該半導體晶圓上形成一黏著層； 切割該半導體晶圓以形成複數個晶片，每一晶片具有複數個柱狀凸塊(pillar bump)及自該黏著層切割之一黏著層片； 將該每一晶片之該黏著層片黏著至一載體的一第一表面； 形成一模封層以包封該些晶片及該載體； 研磨至少該模封層以顯露出該些柱狀凸塊並產生一研磨面； 形成一互連結構，該互連結構包含位於該研磨面上的複數個線路，每一線路電性連接至一對應晶片的複數個柱狀凸塊；及 切割至少該互連結構及該模封層以形成複數個半導體封裝，每一半導體封裝包含一對應線路及該些晶片中的至少一晶片。
  2. 如請求項1所述的方法，其中該載體具有形成於其中的複數個孔穴。
  3. 如請求項1所述的方法，另包含： 於該載體的一第二表面形成一包覆層； 其中該些半導體晶片係透過切割該互連結構、該模封層、該載體及該包覆層來形成。
  4. 如請求項1所述的方法，另包含： 於該載體上形成一電磁波干擾屏蔽層以包覆形成於該載體中之複數個孔穴的穴壁及穴底； 其中： 該每一晶片的該黏著層片係維持性地黏著至該電磁波干擾防護層；及 該每一半導體封裝另包含自該載體上之一電磁波干擾防護層切割的一電磁波干擾屏蔽層，且該每一晶片的該黏著層片係維持性地黏著至一對應的電磁波干擾屏蔽層。
  5. 如請求項1所述的方法，其中該載體之一熱導率大於該半導體晶圓的一熱導率。
  6. 一種半導體封裝，包含： 一載體； 至少一晶片，透過一黏著層片黏著於該載體的一第一表面，且該至少一晶片具有複數個柱狀凸塊； 一模封層，用以包封該至少一晶片及該載體；及 一互連結構，形成於該模封層的一研磨面，並電性連接於該至少一晶片的該些柱狀凸塊。
  7. 如請求項6所述之半導體封裝，另包含一包覆層，形成於該載體的一第二表面，其中該包覆層係透過網版印刷(screen printing)、鋼板印刷(stencil printing)或壓合製程(lamination process)來形成。
  8. 如請求項6所述之半導體封裝，其中該載體具有形成於其中的一孔穴。
  9. 如請求項8所述之半導體封裝，其中該載體包含一電磁干擾屏蔽層，該電磁干擾屏蔽層包覆該孔穴的複數個穴壁及一穴底，且該晶片係透過該黏著層片維持性地黏著於該電磁干擾屏蔽層。
  10. 如請求項9所述之半導體封裝，其中該孔穴的該些穴壁與該孔穴的該穴底互相垂直，或該孔穴的該些穴壁係朝底往內斜向該孔穴的該穴底。
  11. 如請求項9所述之半導體封裝，其中該互連結構係接觸至該電磁干擾屏蔽層。
  12. 如請求項11所述之半導體封裝，其中該互連結構係電性耦接於該電磁干擾屏蔽層。
  13. 如請求項6所述之半導體封裝，其中該載體的一導熱率係大於該晶片的一導熱率。
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