CN109119344A - 半导体封装及半导体封装的制造工艺方法 - Google Patents

半导体封装及半导体封装的制造工艺方法 Download PDF

Info

Publication number
CN109119344A
CN109119344A CN201711205544.1A CN201711205544A CN109119344A CN 109119344 A CN109119344 A CN 109119344A CN 201711205544 A CN201711205544 A CN 201711205544A CN 109119344 A CN109119344 A CN 109119344A
Authority
CN
China
Prior art keywords
chip
semiconductor packages
carrier
layer
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201711205544.1A
Other languages
English (en)
Inventor
徐宏欣
林南君
张简上煜
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Powertech Technology Inc
Original Assignee
Powertech Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Powertech Technology Inc filed Critical Powertech Technology Inc
Publication of CN109119344A publication Critical patent/CN109119344A/zh
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/52—Mounting semiconductor bodies in containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/782—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, each consisting of a single circuit element
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68372—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to support a device or wafer when forming electrical connections thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54433—Marks applied to semiconductor devices or parts containing identification or tracking information
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
    • H01L2223/54486—Located on package parts, e.g. encapsulation, leads, package substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H01L2924/15155—Shape the die mounting substrate comprising a recess for hosting the device the shape of the recess being other than a cuboid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H01L2924/15155—Shape the die mounting substrate comprising a recess for hosting the device the shape of the recess being other than a cuboid
    • H01L2924/15156—Side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/37—Effects of the manufacturing process
    • H01L2924/37001—Yield

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Dicing (AREA)

Abstract

本发明提供一种半导体封装及半导体封装的制造工艺方法，该方法包含提供半导体晶圆，于半导体晶圆上形成粘着层，切割半导体晶圆以形成多个芯片。每一芯片具有多个柱状凸块及自粘着层切割的粘着层片。将每一芯片的粘着层片粘着至载体的第一表面，形成模封层以包封芯片及载体，研磨模封层以显露出多个柱状凸块并产生研磨面，形成互连结构，且互连结构包含位于研磨面上的多个线路，每一线路电连接至对应芯片的柱状凸块。切割互连结构及模封层以形成多个半导体封装，每一半导体封装包含对应线路及至少一芯片。本发明通过粘着层可以提高半导体封装的良率。

Description

半导体封装及半导体封装的制造工艺方法
技术领域
本发明是有关于一种半导体芯片封装，特别是一种扇出型的半导体封装及半导体封装的制造工艺方法。
背景技术
晶圆级扇出封装(wafer level fan-out packaging)制造工艺为现今常见的技术。在晶圆级扇出封装的制造工艺中，设置有集成电路的晶圆会经过一系列的程序，例如研磨、焊晶、模封等等，最终则会被切割为成品。晶圆级扇出封装被视为适合用在小尺寸及高速的封装。然而，由于环氧模封材料(epoxy molding compound，EMC)的牵引力会导致芯片位移，因此常造成晶圆级扇出封装的成品品质下降。
发明内容
本发明提供一种半导体封装及半导体封装的制造工艺方法，以提高半导体封装的良率。
本发明的一实施例提供一种形成半导体封装的方法，方法包含提供半导体晶圆，于半导体晶圆上形成粘着层，切割半导体晶圆以形成多个芯片。每一芯片具有多个柱状凸块(pillar bump)及自粘着层切割的粘着层片。将每一芯片的粘着层片粘着至载体的第一表面，形成模封层以包封芯片及载体，研磨模封层以显露出柱状凸块并产生研磨面，形成互连结构。互连结构包含位于研磨面上的多个线路，每一线路电连接至对应芯片的多个柱状凸块。切割互连结构及模封层以形成多个半导体封装，每一半导体封装包含对应线路及至少一芯片。
本发明另一实施例提供一种半导体封装，半导体封装包含载体、至少一芯片、模封层及互连结构。
每一芯片通过粘着层片粘着于载体的第一表面，且每一芯片具有多个柱状凸块。模封层包封芯片及载体。互连结构形成于模封层的研磨面，并电连接于芯片的柱状凸块。
本发明可在晶圆级扇出制造工艺中形成粘着层。半导体晶圆可被切割成多个芯片，且每个芯片可具有自粘着层切割的粘着层片。在模封程序执行之前，芯片上的粘着层片可被固化以将芯片固定于载体，如此一来，位于第一表面上的芯片就几乎不会被模封材料的牵引力影响而移动。最终半导体封装的良率就能够提升。此外，半导体封装可包含电磁波干扰屏蔽层以提供电磁波干扰的保护。
附图说明
图1至图14为根据本发明第一实施例的方法所制造的半导体封装于各步骤中的对应剖面图。
图15至图18为根据本发明第二实施例的方法所制造的半导体封装于各步骤中的对应剖面图。
图19至图32为根据本发明第三实施例的方法所制造的半导体封装于各步骤中的对应剖面图。
图33为根据本发明第四实施例的方法所制造的半导体封装的剖面图。
图34为根据本发明第五实施例的方法所制造的半导体封装的剖面图。
图35为根据本发明第六实施例的方法所制造的半导体封装的剖面图。
符号说明：
110 半导体晶圆
120 导电接垫
130 绝缘层
140 柱状凸块
150 介电层
160 粘着层
162 粘着层片
210、410 切割机具
200 芯片
300 载体
310 载体的第一表面
312 载体的第二表面
320 模封层
321 研磨面
330 互连结构
332 聚酰亚胺层
334 重配置线路层
336 聚酰亚胺层
338 球下金属层
340 线路
350 焊接球
360 包覆层
400、450、600、700、800、900 半导体封装
220 非主动面
500 基底
501 基底的第一表面
502 基底的第二表面
504 光阻
510 孔穴
512 孔壁
514 孔底
521、522、523 金属层
530 电磁波干扰防护层
530A 电磁波干扰屏蔽层
具体实施方式
图1至图14说明根据本发明第一实施例所制造的半导体封装于各步骤中的对应剖面图。
在图1中，形成半导体封装的方法可先提供半导体晶圆110。半导体晶圆110可具有多个导电接垫120及绝缘层130。绝缘层130可形成于半导体晶圆110的主动面上。导电接垫120可形成于绝缘层130的开口中。导电接垫120可电连接至半导体晶圆110上所形成的集成电路。
在图2中，多个柱状凸块140可形成于导电接垫120上。介电层150可形成在绝缘层130上。柱状凸块140的高度可大于介电层150的高度。柱状凸块140可为铜、金或铜的合金。介电层150可为聚酰亚胺层(Polyimide，PI)。
如图3所示，粘着层160可以通过涂布制造工艺、网版印刷(screen printing)、钢板印刷(stencil printing)或压合制造工艺(lamination process)形成于半导体晶圆110的下侧(非主动面)。粘着层160对硅可产生良好的粘性。粘着层160可为B阶段(B-stage)材质、环氧化物、硅氧树脂、ABF(Ajinomoto build-up film)或前述各项的任意组合。
在图4中，在粘着层160形成于半导体晶圆110的下侧之后，切割机具210便可用来将半导体晶圆110切割成多个芯片200。每一芯片200包含多个柱状凸块140及自粘着层160切割下来的粘着层片162。
如图5所示，每一芯片200可利用其粘着层片162维持性地粘着至载体300的第一表面310，使得芯片200能够维持性地设置于载体300的第一表面310。载体300本身并不具有电性功能(例如传导电压或电流)。载体300可为玻璃、硅氧化物、其热膨胀系数(coefficientof thermal expansion，CTE)与半导体晶圆110相近的材料，或前述各项的任意组合。载体300的导热率可大于半导体晶圆110的导热率。载体300上用以承载芯片200的承载区域可为方形、长方形或圆形。当芯片200放置于载体300的第一表面310时，可使芯片200的粘着层片162固化以将芯片200固定于载体300的第一表面310。如此一来，芯片200在后续的模封程序中就不会产生位置偏移。在后续的机械研磨抛光程序或化学机械抛光(chemicalmechanical polishing，CMP)中，即可将粘着层片162自芯片200移除。
如图6所示，在每一芯片200的粘着层片162粘着至载体300的第一表面310后，可通过模封程序来形成模封层320以包封住芯片200及载体300。模封层320可为环氧模造物(epoxy molding compound，EMC)。由于芯片200会被固化的粘着层片162固定于载体300的第一表面310，且载体300的热膨胀系数可几乎与芯片200本体连带粘着层片162的热膨胀系数相等，因此在第一表面310上的芯片200不至于在形成模封层320时受到模封材料的牵引力影响。如此一来，就无需再对芯片200的位置偏移进行补偿，进而能够提升光刻(lithography)制造工艺的精准度。
如图7所示，模封层320可被研磨至显露出柱状凸块140并形成研磨面321。
如图8所示，聚酰亚胺层332可形成于模封层320的研磨面321，并使部分的柱状凸块140显露于表面。
如图9所示，重配置线路层(redistribution layer，RDL)334可形成于聚酰亚胺层332及柱状凸块140上。重配置线路层334可电连接至柱状凸块140。根据最终半导体封装的线路复杂程度，也可设置超过一层的重配置线路层334。
如图10所示，可于重配置线路层334上形成另一层的聚酰亚胺层336，并使部分的重配置线路层334露出。
如图11所示，球下金属层338可形成于聚酰亚胺层336及部分露出于聚酰亚胺层336的重配置线路层334上。如此一来，包含聚酰亚胺层332、重配置线路334、聚酰亚胺层336及球下金属层338的互连结构330便可形成于模封层320的研磨表面321上。互连结构330包含多个线路340。每一个线路340都可电连接至对应的芯片200的柱状凸块140。
如图12所示，包覆层360可形成于载体300的第二表面312。包覆层360可由网版印刷(screen printing)、钢板印刷(stencil printing)或压合制造工艺(laminationprocess)来形成。包覆层360的材质可为环氧材料、硅氧材料、ABF(Ajinomoto build-upfilm)、晶背保护胶带(LC tape)或其他与硅具有良好接合能力且能够适用于后续雷射标印程序以在包覆层360上形成芯片方向标记及装置资讯标记的材料。利用包覆层360，就能够在封装切割的程序中避免产生剥离或裂痕等问题。此外，包覆层360还可减少因为模封层320、聚酰亚胺层332及336以及重配置线路层334而产生的封装翘曲。在本发明的有些实施例中，载体300可在形成包覆层360之前，先进行薄化，以减少最终半导体封装的厚度。
在图13中，多个焊接球350可形成于互连结构330的线路340上。举例来说，焊接球350可形成于球下金属层338，并可经由线路340电连接至柱状凸块140。
如图14所示，切割机具410可用来切割互连结构330中的聚酰亚胺层332及336、模封层320、载体300及包覆层360以形成多个半导体封装400。每一个半导体封装400可包含至少一芯片200及对应的线路340。每一半导体封装400可为扇出结构的封装，但本发明并不以此为限。
图15至图18为本发明第二实施例的方法所制造的半导体封装于各步骤中的对应剖面图。
如图15所示，在使用切割机具410之前，并在互连结构330形成以后，可将载体300及粘着层片162移除。载体300可通过干式蚀刻、湿式蚀刻、研磨程序、抛光程序或化学机械抛光(chemical mechanical polishing，CMP)等方式去除。粘着层片162可通过机械研磨程序、抛光程序、化学机械抛光或者选择性蚀刻的方式去除。载体300可被部分研磨或全部研磨。若载体300被完全研磨，则粘着层片162甚至是芯片200的的部分也可能被研磨以减少最终半导体封装的厚度。在本实例中，载体330会被研磨至显露出芯片200的非主动面220。非主动面220与互连结构330位于相反两侧。
如图16所示，在移除载体300及粘着层片162之后，包覆层360可形成于芯片200上，并与互连结构330为相对面。
在图17中，焊接球350可形成于互连结构330上的线路340。举例来说，焊接球350可形成于球下金属层338，并可通过线路340与柱状凸块140电连接。
如图18所示，切割机具410可用来切割模封层320及互连结构330的聚酰亚胺层332及336以形成多个半导体封装450。切割机具410可进一步切割包覆层360。每一半导体封装450包含至少一芯片200以及对应的线路340。在本实施例中，半导体封装450可为扇出结构的封装，但本发明并不以此为限。
根据本发明的第三实施例，图19至图32利用剖面图说明形成半导体封装的另一方法。第一实施例与第三实施例中所使用的相同符号是代表相同元件。
在图19中，可先提供基底500。基底500可由硅制成。光阻504可形成在载体500的第一表面501上。光阻504可作为蚀刻的光掩膜以抵抗后续的湿式化学蚀刻或等离子蚀刻以达到选择性的蚀刻。光阻504可通过涂布制造工艺、网版印刷、钢板印刷或压合制造工艺来形成。此外，当基底500蚀刻完成后，便可利用酸、碱或溶剂来移除光阻504。
如图20所示，基底500的第一表面501上可形成多个孔穴510。在本实施例中，基底500可为硅晶圆，而孔穴510则可通过湿式化学蚀刻的程序形成。在另外的实施例中，孔穴510也可利用等离子蚀刻的方式形成。当湿式化学蚀刻执行完毕后，孔穴510的穴壁512会朝底往内斜向孔穴510的穴底514。在有些实施例中，第一表面501与孔穴510的穴壁512之间的角度θ可介于50度至60度。如图20所示，第一表面501与穴底514会与基底500的晶向平面<110>平行，并与基底500的晶向平面<100>相垂直。孔穴510的穴壁512则为基底500的晶向平面<111>。
如图21所示，电磁波干扰(electromagnetic interference，EMI)防护层530可连续性地形成于基底500以覆盖孔穴510的穴壁512及穴底514。电磁波干扰防护层530可利用物理气相沉积(physical vapor deposition，PVD)的方式形成于基底500上。电磁波干扰防护层530可包含三个金属层521、522及523，而金属层522可形成在金属层521及523之间。在有些实施例中，金属层521及523可为钛金属(titanium，Ti)，而金属层522可为铜金属(copper，Cu)。在另外的实施例中，金属层521及523可为不锈钢(stainless steel，SUS)，而金属层522可为铜金属。此外，对准记号(fiducial marks)可形成于电磁波干扰防护层530上，以便后续在接合芯片200与电磁波干扰防护层530时能够对准。后续的对准程序可能包含全域对准、局部对准或前两项的结合。基底500及电磁波干扰防护层530可建构出用以承载芯片200的载体550。
在图22中，可通过芯片200中的粘着层片162维持性地粘着至载体550中连续的电磁波干扰防护层530以便将芯片200维持性地设置于孔穴510。图22中的芯片200可根据图1至图4的步骤制造取得。当芯片200被设置在孔穴510时，芯片200的粘着层片162可被固化以将芯片200固定于电磁波干扰防护层530。如此一来，在后续的模封过程中，芯片就能够保持附着于电磁波干扰防护层530。
如图23所示，在芯片200的粘着层片162粘合至载体550的连续的电磁波干扰防护层530之后，可执行模封程序以使模封层320包封住芯片200及载体550。由于通过固化粘着层片162可将芯片200固定于电磁波干扰防护层530，且基底500的热膨胀系数实质上可与芯片200的本体连带粘着层片162的热膨胀系数相同，因此在电磁波干扰防护层530上的芯片200就不至于在形成模封层320时，受到牵引而移动位置。如此一来，就无需再对芯片200的位置偏移进行补偿，进而能够提升光刻制造工艺的精准度。
如图24所示，模封层320可被研磨至显露出柱状凸块140并形成研磨面321。在有些实施例中，部分的电磁干扰防护层530及部分的基底500可利用相同的研磨程序一并去除。在部分的电磁波干扰防护层530及部分的基底500被研磨去除后，原先连续的电磁波干扰防护层530就被分为多个电磁波干扰屏蔽层530A。
如图25所示，聚酰亚胺层332可形成于研磨面321上。研磨面321可包含彼此共平面的模封层320的表面、电磁波干扰防护层530的表面、基底500的表面及柱状凸块140的表面。
如图26所示，重配置线路层334可形成于聚酰亚胺层332及柱状凸块140上。根据最终半导体封装的线路复杂度，重配置线路层334的数量可能不只一层。
如图27所示，聚酰亚胺层336可形成于重配置线路层334上，并使部分的重配置线路层334露出。
如图28所示，球下金属层338可形成于聚酰亚胺层336及部分的重配置金属层334上。如此一来，包含聚酰亚胺层332、重配置线路层334、聚酰亚胺层336及球下金属层338的互连结构330就可形成于研磨面321上。互连结构330包含多个线路340，每一个线路340可电连接至对应芯片200的柱状凸块140。
如图29所示，薄化程序可将基底500变薄。薄化程序可利用研磨制造工艺或蚀刻制造工艺。
如图30所示，包覆层360可形成于基底500的第二表面502。包覆层360可由网版印刷、钢板印刷或压合制造工艺来形成，而包覆层360的材质可为环氧材料、硅氧材料、ABF、晶背保护胶带或其他与硅具有良好接合能力且能够适用于后续雷射标印程序以在包覆层360上形成芯片方向标记及装置资讯标记的材料。利用包覆层360，就能够在封装切割的程序中避免产生剥离或裂痕等问题。此外，包覆层360还可减少因为模封层320、聚酰亚胺层332及336以及重配置线路层334而产生的封装翘曲。
如图31所示，焊接球350可形成于互连结构330的线路340上。举例来说，焊接球350可形成于球下金属338，并经由线路340电连接至柱状凸块140。
如图32所示，切割机具410可用来切割至少互连结构330及基底500以形成多个半导体封装600。在有些实施例中，互连结构330中的聚酰亚胺层332及336也可被切割机具410切穿。每一个半导体封装600包含对应的芯片200、用以提供电磁波干扰保护的电磁波干扰屏蔽层530A、部分的基底500及电连接至芯片200的柱状凸块的对应线路340。每一半导体封装600可为扇出结构，但本发明并不以此为限。
在本发明的第四实施例中，孔穴510可利用等离子蚀刻形成于基底500，而不利用湿式化学蚀刻。图33为根据本发明第四实施例所制造的半导体封装700。半导体封装700的结构与图32中半导体封装600的结构相似。半导体封装700与半导体封装600的主要差异在于半导体封装700的孔穴510的穴壁512会实质上垂直于孔穴510的穴底514。
图34为根据本发明第五实施例所制造的半导体封装800。半导体封装800的结构与图32所示的半导体封装600的结构相似。在半导体封装800中，柱状凸块140的高度会大于先前实施例中的柱状凸块140的高度。电磁波干扰屏蔽层530A及基底500会被模封层320包覆。若柱状凸块140已被模封层320给包覆，则可将模封层320研磨至显露出柱状凸块140并形成研磨面321。然而在电磁波干扰屏蔽层530A及载体550的基底500还未被研磨时，也可能即足以显露出柱状凸块140并形成研磨面321。互连结构330可形成于模封层320的研磨面321上。包覆层360可形成于基底500的第二表面502。半导体封装800可藉由切割至少互连结构330、模封层320及载体550来形成。在有些实施例中，互连结构330中的聚酰亚胺层332及336也可被切割机具410切穿。
图35为根据本发明第六实施例所制造的半导体封装900。半导体封装900的结构与图34所示的半导体封装800的结构相似。半导体封装900与半导体封装800的主要差别在于半导体封装900的孔穴510的穴壁512实质上会垂直于半导体封装900的孔穴510的穴底514。若柱状凸块140已被模封层320给包覆，则可将模封层320研磨至显露出柱状凸块140并形成研磨面321。然而在电磁波干扰屏蔽层530A及载体550的基底500还未被研磨时，也可能即足以显露出柱状凸块140并形成研磨面321。互连结构330可形成于模封层320的研磨面321上。包覆层360可形成于基底500的第二表面502。半导体封装900可藉由切割至少互连结构330、模封层320及载体550来形成。在有些实施例中，互连结构330中的聚酰亚胺层332及336也可被切割机具410切穿。
在图34及图35中，由于模封层320会完全包覆电磁波干扰屏蔽层530A，因此电磁波干扰屏蔽层530A与互连结构330之间并无直接接触，然而本发明并不以此为限，例如在图32及图33中，电磁波干扰屏蔽层530A也可能接触至互连结构330，举例来说，电磁波干扰屏蔽层530A可能会耦接至互连结构330的聚酰亚胺层332，或是电性耦接至互连结构330的重配置线路层334。
根据本发明所提供的实施例，可在晶圆级扇出制造工艺中形成粘着层。半导体晶圆可被切割成多个芯片，且每个芯片可具有自粘着层切割的粘着层片。在模封程序执行之前，芯片上的粘着层片可被固化以将芯片固定于载体。由于芯片被固化的粘着层片固定在载体上，位于第一表面上的芯片就几乎不会被模封材料的牵引力影响而移动。如此一来，最终半导体封装的良率就能够提升。此外，半导体封装可包含电磁波干扰屏蔽层以提供电磁波干扰的保护。
以上所述仅为本发明的较佳实施例，凡依本发明权利要求所做的均等变化与修饰，皆应属本发明的涵盖范围。

Claims (13)

1.一种形成半导体封装的方法，其特征在于，包含：
提供一半导体晶圆；
于所述半导体晶圆上形成一粘着层；
切割所述半导体晶圆以形成多个芯片，每一芯片具有多个柱状凸块及自所述粘着层切割的一粘着层片；
将所述每一芯片的所述粘着层片粘着至一载体的一第一表面；
形成一模封层以包封所述芯片及所述载体；
研磨至少所述模封层以显露出所述柱状凸块并产生一研磨面；
形成一互连结构，所述互连结构包含位于所述研磨面上的多个线路，每一线路电连接至一对应芯片的多个柱状凸块；及
切割至少所述互连结构及所述模封层以形成多个半导体封装，每一半导体封装包含一对应线路及所述芯片中的至少一芯片。
2.如权利要求1所述的形成半导体封装的方法，其特征在于，所述载体具有形成于其中的多个孔穴。
3.如权利要求1所述的形成半导体封装的方法，其特征在于，另包含：
于所述载体的一第二表面形成一包覆层；
其中所述半导体芯片是通过切割所述互连结构、所述模封层、所述载体及所述包覆层来形成。
4.如权利要求1所述的形成半导体封装的方法，其特征在于，另包含：
于所述载体上形成一电磁波干扰屏蔽层以包覆形成于所述载体中的多个孔穴的穴壁及穴底；
其中：
所述每一芯片的所述粘着层片是维持性地粘着至所述电磁波干扰防护层；及
所述每一半导体封装另包含自所述载体上的一电磁波干扰防护层切割的一电磁波干扰屏蔽层，且所述每一芯片的所述粘着层片是维持性地粘着至一对应的电磁波干扰屏蔽层。
5.如权利要求1所述的形成半导体封装的方法，其特征在于，所述载体的一热导率大于所述半导体晶圆的一热导率。
6.一种半导体封装，其特征在于，包含：
一载体；
至少一芯片，通过一粘着层片粘着于所述载体的一第一表面，且所述至少一芯片具有多个柱状凸块；
一模封层，用以包封所述至少一芯片及所述载体；及
一互连结构，形成于所述模封层的一研磨面，并电连接于所述至少一芯片的所述柱状凸块。
7.如权利要求6所述的半导体封装，其特征在于，另包含一包覆层，形成于所述载体的一第二表面，其中所述包覆层是通过网版印刷、钢板印刷或压合制造工艺来形成。
8.如权利要求6所述的半导体封装，其特征在于，所述载体具有形成于其中的一孔穴。
9.如权利要求8所述的半导体封装，其特征在于，所述载体包含一电磁干扰屏蔽层，所述电磁干扰屏蔽层包覆所述孔穴的多个穴壁及一穴底，且所述芯片是通过所述粘着层片维持性地粘着于所述电磁干扰屏蔽层。
10.如权利要求9所述的半导体封装，其特征在于，所述孔穴的所述穴壁与所述孔穴的所述穴底互相垂直，或所述孔穴的所述穴壁是朝底往内斜向所述孔穴的所述穴底。
11.如权利要求9所述的半导体封装，其特征在于，所述互连结构是接触至所述电磁干扰屏蔽层。
12.如权利要求11所述的半导体封装，其特征在于，所述互连结构是电性耦接于所述电磁干扰屏蔽层。
13.如权利要求6所述的半导体封装，其特征在于，所述载体的一导热率是大于所述芯片的一导热率。
CN201711205544.1A 2017-06-23 2017-11-27 半导体封装及半导体封装的制造工艺方法 Pending CN109119344A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/630,972 US20180374717A1 (en) 2017-06-23 2017-06-23 Semiconductor package and method of forming the same
US15/630,972 2017-06-23

Publications (1)

Publication Number Publication Date
CN109119344A true CN109119344A (zh) 2019-01-01

Family

ID=64692708

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201711205544.1A Pending CN109119344A (zh) 2017-06-23 2017-11-27 半导体封装及半导体封装的制造工艺方法

Country Status (3)

Country Link
US (1) US20180374717A1 (zh)
CN (1) CN109119344A (zh)
TW (1) TWI677035B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113471160A (zh) * 2021-06-29 2021-10-01 矽磐微电子(重庆)有限公司 芯片封装结构及其制作方法

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10510679B2 (en) * 2017-06-30 2019-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device with shield for electromagnetic interference
US10714431B2 (en) * 2017-08-08 2020-07-14 UTAC Headquarters Pte. Ltd. Semiconductor packages with electromagnetic interference shielding
US11227777B2 (en) * 2018-10-09 2022-01-18 Micron Technology, Inc. Sacrificial separators for wafer level encapsulating

Citations (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1624888A (zh) * 2003-12-03 2005-06-08 育霈科技股份有限公司 扩散式晶圆型态封装的结构与其形成方法
CN101175394A (zh) * 2006-10-31 2008-05-07 比亚迪股份有限公司 一种防电磁干扰的多层复合材料及其制备方法
CN101202253A (zh) * 2006-12-13 2008-06-18 育霈科技股份有限公司 具有良好热膨胀系数效能的圆片级封装及其方法
CN101840910A (zh) * 2009-03-16 2010-09-22 株式会社瑞萨科技 半导体器件及其制造方法
US20110241041A1 (en) * 2010-03-30 2011-10-06 Micron Technology, Inc. Light emitting diode thermally enhanced cavity package and method of manufacture
CN102610590A (zh) * 2011-01-24 2012-07-25 群成科技股份有限公司 具电磁干扰屏蔽的封装模块
CN102610577A (zh) * 2011-01-18 2012-07-25 索尼公司 用于嵌入一个或多个电子构件的封装的制造方法
CN102751204A (zh) * 2012-07-16 2012-10-24 江阴长电先进封装有限公司 一种扇出型圆片级芯片封装方法
CN202905686U (zh) * 2012-07-30 2013-04-24 江阴长电先进封装有限公司 一种多芯片圆片级封装结构
CN103426858A (zh) * 2012-05-18 2013-12-04 台湾积体电路制造股份有限公司 具有金属绝缘体金属电容器的封装件及其制造方法
US20140062607A1 (en) * 2012-08-31 2014-03-06 Vijay K. Nair Ultra slim rf package for ultrabooks and smart phones
CN104241210A (zh) * 2014-09-29 2014-12-24 华进半导体封装先导技术研发中心有限公司 一种低成本超薄扇出型封装结构及其制作方法
CN105022228A (zh) * 2014-04-30 2015-11-04 住友电木株式会社 感光性树脂材料和树脂膜
CN105097720A (zh) * 2015-06-30 2015-11-25 南通富士通微电子股份有限公司 封装结构的形成方法
CN105140189A (zh) * 2015-07-08 2015-12-09 华进半导体封装先导技术研发中心有限公司 板级扇出型芯片封装器件及其制备方法
CN105244307A (zh) * 2015-09-01 2016-01-13 华进半导体封装先导技术研发中心有限公司 扇出型封装结构的制作方法
CN105355569A (zh) * 2015-11-05 2016-02-24 南通富士通微电子股份有限公司 封装方法
CN105390429A (zh) * 2015-11-05 2016-03-09 南通富士通微电子股份有限公司 封装方法
CN106098664A (zh) * 2016-06-12 2016-11-09 华天科技（昆山）电子有限公司 一种埋入式半导体芯片扇出型封装结构及其制作方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030197285A1 (en) * 2002-04-23 2003-10-23 Kulicke & Soffa Investments, Inc. High density substrate for the packaging of integrated circuits
KR101049390B1 (ko) * 2005-12-16 2011-07-14 이비덴 가부시키가이샤 다층 프린트 배선판 및 그 제조 방법
US20080217761A1 (en) * 2007-03-08 2008-09-11 Advanced Chip Engineering Technology Inc. Structure of semiconductor device package and method of the same
TWI548049B (zh) * 2014-09-19 2016-09-01 矽品精密工業股份有限公司 半導體結構及其製法
US9899285B2 (en) * 2015-07-30 2018-02-20 Semtech Corporation Semiconductor device and method of forming small Z semiconductor package
US9640498B1 (en) * 2015-10-20 2017-05-02 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out (InFO) package structures and methods of forming same

Patent Citations (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1624888A (zh) * 2003-12-03 2005-06-08 育霈科技股份有限公司 扩散式晶圆型态封装的结构与其形成方法
CN101175394A (zh) * 2006-10-31 2008-05-07 比亚迪股份有限公司 一种防电磁干扰的多层复合材料及其制备方法
CN101202253A (zh) * 2006-12-13 2008-06-18 育霈科技股份有限公司 具有良好热膨胀系数效能的圆片级封装及其方法
CN101840910A (zh) * 2009-03-16 2010-09-22 株式会社瑞萨科技 半导体器件及其制造方法
US20110241041A1 (en) * 2010-03-30 2011-10-06 Micron Technology, Inc. Light emitting diode thermally enhanced cavity package and method of manufacture
CN102610577A (zh) * 2011-01-18 2012-07-25 索尼公司 用于嵌入一个或多个电子构件的封装的制造方法
CN102610590A (zh) * 2011-01-24 2012-07-25 群成科技股份有限公司 具电磁干扰屏蔽的封装模块
CN103426858A (zh) * 2012-05-18 2013-12-04 台湾积体电路制造股份有限公司 具有金属绝缘体金属电容器的封装件及其制造方法
CN102751204A (zh) * 2012-07-16 2012-10-24 江阴长电先进封装有限公司 一种扇出型圆片级芯片封装方法
CN202905686U (zh) * 2012-07-30 2013-04-24 江阴长电先进封装有限公司 一种多芯片圆片级封装结构
US20140062607A1 (en) * 2012-08-31 2014-03-06 Vijay K. Nair Ultra slim rf package for ultrabooks and smart phones
CN105022228A (zh) * 2014-04-30 2015-11-04 住友电木株式会社 感光性树脂材料和树脂膜
CN104241210A (zh) * 2014-09-29 2014-12-24 华进半导体封装先导技术研发中心有限公司 一种低成本超薄扇出型封装结构及其制作方法
CN105097720A (zh) * 2015-06-30 2015-11-25 南通富士通微电子股份有限公司 封装结构的形成方法
CN105140189A (zh) * 2015-07-08 2015-12-09 华进半导体封装先导技术研发中心有限公司 板级扇出型芯片封装器件及其制备方法
CN105244307A (zh) * 2015-09-01 2016-01-13 华进半导体封装先导技术研发中心有限公司 扇出型封装结构的制作方法
CN105355569A (zh) * 2015-11-05 2016-02-24 南通富士通微电子股份有限公司 封装方法
CN105390429A (zh) * 2015-11-05 2016-03-09 南通富士通微电子股份有限公司 封装方法
CN106098664A (zh) * 2016-06-12 2016-11-09 华天科技（昆山）电子有限公司 一种埋入式半导体芯片扇出型封装结构及其制作方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113471160A (zh) * 2021-06-29 2021-10-01 矽磐微电子(重庆)有限公司 芯片封装结构及其制作方法

Also Published As

Publication number Publication date
US20180374717A1 (en) 2018-12-27
TWI677035B (zh) 2019-11-11
TW201906024A (zh) 2019-02-01

Similar Documents

Publication Publication Date Title
CN107768295B (zh) 半导体封装及其制造方法
CN106356340B (zh) 半导体器件及其制造方法
US9685421B2 (en) Methods for high precision microelectronic die integration
CN106233462B (zh) 半导体器件以及半导体器件的制造方法
US7193301B2 (en) Semiconductor device and manufacturing method thereof
US7413925B2 (en) Method for fabricating semiconductor package
CN102969305B (zh) 用于半导体结构的管芯对管芯间隙控制及其方法
CN109119344A (zh) 半导体封装及半导体封装的制造工艺方法
JP2001313350A (ja) チップ状電子部品及びその製造方法、並びにその製造に用いる疑似ウエーハ及びその製造方法
KR20150104467A (ko) 반도체 디바이스의 제조 방법 및 이에 따른 반도체 디바이스
US20150125993A1 (en) Interposer, manufacturing method thereof, semiconductor package using the same, and method for fabricating the semiconductor package
CN107068645A (zh) 半导体器件及制造方法
CN105428329A (zh) 具有ubm的封装件和形成方法
KR20170070779A (ko) 웨이퍼 레벨 패키지 및 제조 방법
CN103811394A (zh) 载具晶圆及其制造方法以及封装方法
JP2010147096A (ja) 半導体装置及び半導体装置の製造方法
KR20040030302A (ko) 회로 장치의 제조 방법
TWI642145B (zh) 半導體封裝基板及其製造方法
KR20040027345A (ko) 회로 장치의 제조 방법
CN109427700A (zh) 集成电路封装及其制作方法
US11195788B2 (en) Hybrid dielectric scheme in packages
KR101605610B1 (ko) 반도체 디바이스의 제조 방법 및 이에 따른 반도체 디바이스
US9991206B1 (en) Package method including forming electrical paths through a mold layer
TW201327746A (zh) 半導體堆疊結構及其製法
CN114649219A (zh) 半导体器件及其制造方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication

Application publication date: 20190101

RJ01 Rejection of invention patent application after publication