CN107768295B - 半导体封装及其制造方法 - Google Patents

半导体封装及其制造方法 Download PDF

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Publication number
CN107768295B
CN107768295B CN201611032378.5A CN201611032378A CN107768295B CN 107768295 B CN107768295 B CN 107768295B CN 201611032378 A CN201611032378 A CN 201611032378A CN 107768295 B CN107768295 B CN 107768295B
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rdl structure
semiconductor packages
layer
connector
packages according
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CN107768295A (zh
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施信益
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Micron Technology Inc
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Micron Technology Inc
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Abstract

本发明公开了一种半导体封装，包含一内连部件，被模塑料环绕包覆，其中内连部件包含第一重布层结构；第二重布层结构，设于内连部件上；多个第一连接件，设于第二重布层结构上；抛光停止层，覆盖于内连部件的表面上；多个第二连接件，设于抛光停止层中；以及至少一半导体晶粒设于第二连接件上。

Description

半导体封装及其制造方法
技术领域
本发明涉及半导体封装技术领域，特别是涉及一种制造具有高密度及混合式中介层衬底的半导体内连装置的方法。
背景技术
如本领域所已知的，在2.5D集成电路(IC)封装中，多个晶粒或芯片通常被设置在硅中介层上。硅中介层借由使用穿硅通孔(through substrate via或through siliconvia,下称TSV)技术达到晶粒之间的内连及外部的输出/输入(I/O)。然后，硅中介层通常经由C4凸块设置在一封装衬底上。
然而，TSV硅中介层是相对昂贵的，因此，本领域仍需要一种改进的半导体封装，其具有无TSV的中介层，而这样的中介层仍可以提供非常细间距的内连结构。
美国专利公开号US 2015/0371965 A1公开一种制造高密度电路薄膜的方法。此先前技术的缺点之一是在切割电路薄膜重布层I之前移除临时载板I。由于移除了临时载板I，缺乏足够的机械支撑，使电路薄膜重布层I的处里变得困难且产品合格率也因此较低。
发明内容
本发明的一主要目的在提供一种改良的方法，用于制造一半导体装置，其具有混合式、无TSV的中介层衬底。
本发明的另一目的在提供一种改良的方法，用于制造具有高合格率的半导体装置。
本发明一方面，提出一种半导体装置的制造方法。首先提供第一载板，其上设有抛光停止层。之后，于抛光停止层上形成重布层结构。接着，对重布层结构与第一载板进行一第一切割工艺，构成彼此分离的个别的内连部件。然后，将多个内连部件重排并安置在第二载板上。接着，形成模塑料，使其覆盖多个所述内连部件。再去除所述第二载板，以显露出各内连部件的第一重布层结构的表面。之后，于第一重布层结构的显露出的表面上与模塑料上，形成第二重布层结构。然后，于第二重布层结构上形成第一连接件。再使所述第一连接件与一第三载板接合。接着抛光模塑料与第一载板。之后完全去除第一载板以显露出抛光停止层。然后，于抛光停止层中形成复数开口。最后，分别于开口中形成第二连接件。
本发明一方面，提供一种半导体封装，包含：内连部件，被一模塑料环绕包覆，其中内连部件包含第一重布层结构；第二重布层结构，设于内连部件与模塑料上，其中第二重布层结构与第一重布层结构电连接；多个第一连接件，设于第二重布层结构上；抛光停止层，覆盖于内连部件的表面上；多个第二连接件，设于抛光停止层中；以及至少一半导体晶粒设于第二连接件上。
为让本发明的上述目的、特征及优点能更明显易懂，下文特举优选实施方式，并配合附图，作详细说明如下。然而如下的优选实施方式与附图仅供参考与说明用，并非用来对本发明加以限制。
附图说明
附图包括对本发明的实施例提供进一步的理解，及被并入且构成说明书中的一部份。附图说明一些本发明的实施例，并与说明书一起用于解释其原理。
图1至图16是根据本发明的实施例所绘示的制造半导体封装的示例性方法的剖面图。
其中，附图标记说明如下：
110 第一载板
111 抛光停止层
200 第一重布层(RDL)结构
201 介电层
202 绕线层
204 凸块垫
10 内连部件
120 第二载板
121 黏着层
300 模塑料
300a 第一表面
200a 上表面
300b 第二表面
400 第二重布层结构
401 介电层
402 绕线层
404 焊垫
403 防焊层
420 第一连接件
130 第三载板
131 黏着层
510 凹陷处
111a 开口
620 第二连接件
11 第一半导体晶粒
12 第二半导体晶粒
1 半导体封装
具体实施方式
于下文中，是加以陈述本发明的具体实施方式，所述具体实施方式可参考相对应的附图，使所述附图构成实施方式的一部分。同时也借由说明，公开本发明可据以施行的方式。所述实施例已被清楚地描述足够的细节，使本领域技术人员可据以实施本发明。其他实施例亦可被加以施行，且对于其结构上所做的改变仍属本发明所涵盖的范畴。
因此，下文的细节描述将不被视为一种限定，且本发明所涵盖的范畴仅被权利要求书以及其同意义的涵盖范围。本发明的一或多个实施例将参照附图描述，其中，相同元件符号始终用以表示相同元件，且其中阐述的结构未必按比例所绘制。
术语“晶粒”、“芯片”、“半导体芯片”及“半导体晶粒”于整个说明书中可互换使用。
文中所使用的术语“晶圆”及“衬底”包括任何具有暴露表面的结构，于所述表面上根据本发明沉积一层，例如，形成例如重布层的电路结构。术语“衬底”被理解为包括半导体晶圆，但不限于此。术语“衬底”亦可用以指加工过程中的半导体结构，且可包括已被制造在其上的其它层。
请参考图1至图16。图1至图16是根据本发明的实施例所绘示的制造半导体封装的示例性方法的剖面图。
如图1所示，首先，提供一第一载板110。根据本发明一实施例，第一载板110可包含硅或金属，优选包含硅。例如，第一载板110可为一晶圆形状硅载板。接着，在第一载板110的第一表面上沉积一抛光停止层111。抛光停止层111可包含介电层或钝化层，例如：抛光停止层111可包含氮化硅，氧化硅，或它们的组合。
如图2所示，随后，于抛光停止层111上形成第一重布层(RDL)结构200。根据本发明一实施例，第一RDL结构200可包含至少一介电层201以及至少一绕线层202。应理解的是，第一RDL结构200可包含多层介电材料及多层绕线层。多个凸块垫204是形成于第一RDL 200中且电连接至绕线层202。
如图3所示，进行一切割工艺，以构成彼此分离的个别的内连部件10。内连部件10是无源器件，即无有源电路被形成在每个内连部件10上。
值得注意的是，在进行切割工艺时，第一载板110仍与第一RDL结构200接合在一起，并未分离，以提供足够的机械支持。如果第一载板110在切割工艺之前被移除，厚度很薄的第一RDL结构200(约10微米厚)会变得难以处理，且将降低合格率。
随后，如图4所示，将多个内连部件10重排并安置在第二载板120上。第二载板120可包含黏着层121。第二载板120可包含硅或玻璃，但不限于此。第二载板120可为晶圆形状或矩形面板形状。被翻面的内连部件10可重排并安置在黏着层121上。根据本发明一实施例，绕线层202的暴露表面是与黏着层121直接接触。
如图5所示，形成一模塑料300，使其覆盖多个内连部件10及黏着层121的上表面。然后，对模塑料300进行一固化工艺。根据本发明一实施例，模塑料300可包含环氧树脂和硅石填料的混合物，但不限于此。
可选地，模塑料300的上部分可被抛光或研磨去除，使得第一载板110的表面被显露出来，且与模塑料300的第一表面300a齐平。
如图6所示，在形成模塑料300之后，移除第二载板120及黏着层121，以显露出绕线层202。此时，第一重布层结构200的上表面200a与模塑料300的第二表面300b齐平。
然后，如图7所示，于模塑料300的第二表面300b及第一重布层结构200的绕线层202上，形成第二重布层结构400。根据本发明一实施例，第二重布层结构400可透过使用印刷电路板(PCB)工艺来制造。
根据本发明一实施例，第二重布层结构400可包含一介电层401以及一绕线层402。介电层401可包含增层绝缘膜(Ajinomoto build-up film,ABF)、预浸材(prepreg)、聚酰亚胺(polyimide)、苯环丁烯(Benzocyclobutene,BCB)，或其类似物。绕线层402可包含铜，但不限于此。绕线层402电连接至绕线层202。
根据本发明一实施例，在第二重布层结构400中形成多个焊垫404。焊垫404透过防焊层403中的开口被分别显露出来。
接着，如图8所示，多个第一连接件420，例如锡凸块、锡球、或其类似物形成于相应的焊垫404上。例如，第一连接件420可为球型格栅数组(ball grid array,BGA)锡球，但不限于此。根据本发明一实施例，多个第一连接件420可具有一球间距(或凸块间距)，其等同于一母板或一印刷电路板上的球垫间距。
如图9所示，随后，使第一连接件420与第三载板130接合。根据本发明一实施例，第三载板130可包含硅或玻璃，但不限于此。第三载板130可为晶圆形状或矩形面板形状。根据本发明一实施例，第三载板130与第二载板120具有相同形状。在第三载板130上可设置黏着层131。第一连接件420与黏着层131直接接触。
然后，如图10所示，对模塑料300的第一表面300a与第一载板110进行一抛光工艺，以去除至少一部份的模塑料300及至少一部份的各第一载板110。
如图11所示，根据本发明一实施例，各第一载板110的剩余部分可利用湿式蚀刻或干式蚀刻去除。在完全去除各第一载板110之后，形成一凹陷处510。抛光停止层111从凹陷处510中被显露出来。
如第12图所示，在去除第一载板110之后，进行一抛光工艺以移除一部份的模塑料300，其中抛光工艺会停止于抛光停止层111上，此时，使得抛光停止层111的上表面与模塑料300的第一表面300a齐平。
如图13所示，进行光刻工艺及蚀刻工艺，以于抛光停止层111中形成多个开口111a，其中开口111a分别显露出凸块垫204。
如图14所示，随后，分别于开口111a中形成第二连接件620，例如微凸块。第二连接件620可包含金、银、铜、镍、钨、或它们的组合。第二连接件620具有一细间距，其等同于被设置到内连部件10上的各半导体晶粒的主表面上的输出/输入垫(I/O pad)间距。
然后，如图15所示，至少一第一半导体晶粒11及至少一第二半导体晶粒12设于内连部件10上。第一半导体晶粒11及第二半导体晶粒12可以是覆晶芯片，使其有源面朝下面向第二连接件620。第一半导体晶粒11及第二半导体晶粒12是借由第二连接件620电连接第一RDL结构200。
第一半导体晶粒11及第二半导体晶粒12是具有一定功能的有源集成电路芯片，例如，图形处理单元(GPU)、中央处理单元(CPU)、存储器芯片等。根据本发明一实施例，第一半导体晶粒11及第二半导体晶粒12可被一起设置于一封装内，且可为具有其特定功能的不同的芯片。可选地，底胶(图未示)可被应用于各晶粒的下方。
最后，如图16所示，利用本领域已知的方法将第三载板130及黏着层131去除。接着，进行一切割工艺，构成彼此分离的个别的半导体封装1。应理解的是，虽然在附图中绘示各封装包含两个晶粒，但在一些实施例中，各半导体封装1可以包含单个晶粒。根据本发明实施例，没有使用模塑料以覆盖至少一所述半导体晶粒。
以上所述仅为本发明的优选实施例而已，并不用于限制本发明，对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (19)

1.一种半导体封装，其包括：
内连部件，其由模塑料环绕，其中所述内连部件包括第一重布层(RDL)结构；
第二RDL结构，其安置于所述内连部件与所述模塑料上，其中所述第二RDL结构与所述第一RDL结构电连接；
多个第一连接件，其安置于所述第二RDL结构的第一侧上，所述第二RDL结构的第一侧与安置于所述内连部件和所述模塑料上的所述第二RDL结构的第二侧相对；
抛光停止层，其覆盖所述内连部件的第一侧上，所述内连部件的第一侧与所述第二RDL结构在其上安置的所述内连部件的第二侧相对，其中所述抛光停止层包括多个开口；
多个第二连接件，其安置于所述第一RDL结构的介电层上且在所述第一RDL结构的介电层中，所述多个第二连接件安置在所述内连部件的所述第一侧上且形成于所述抛光停止层的所述多个开口中；以及
至少一个半导体晶粒，其安装于所述多个第二连接件的至少一者上。
2.根据权利要求1所述的半导体封装，其中所述抛光停止层包含氮化硅、氧化硅或其组合。
3.根据权利要求1所述的半导体封装，其中所述第一连接件为BGA球。
4.根据权利要求3所述的半导体封装，其中所述第一连接件具有球间距，所述球间距匹配于母板或印刷电路板(PCB)上的球垫间距。
5.根据权利要求4所述的半导体封装，其中所述第二连接件为微凸块。
6.根据权利要求5所述的半导体封装，其中所述第二连接件具有细间距，所述细间距匹配于所述至少一个半导体晶粒的主表面上的输出/输入(I/O)垫间距。
7.根据权利要求1所述的半导体封装，其中所述抛光停止层与所述模塑料的上表面齐平。
8.根据权利要求1所述的半导体封装，其中所述至少一个半导体晶粒通过所述多个第二连接件中的所述至少一者与所述第一RDL结构电连接。
9.根据权利要求1所述的半导体封装，其中所述至少一个半导体晶粒安装在所述多个第二连接件的所述至少一者上以使得所述至少一个半导体晶粒的主表面面对所述多个第二连接件中的所述至少一者。
10.根据权利要求1所述的半导体封装，其中所述第一RDL结构包括所述介电层和绕线层。
11.根据权利要求1所述的半导体封装，其中所述第二RDL结构包括介电层和绕线层。
12.根据权利要求1所述的半导体封装，其中所述第二RDL结构与所述第一RDL结构电连接且其中所述第二RDL的绕线层与所述第一RDL结构的绕线层电连接。
13.根据权利要求10所述的半导体封装，其中所述第一RDL结构进一步包括电连接至所述绕线层的凸块垫，且其中所述多个第二连接件形成于所述凸块垫的上方。
14.根据权利要求1所述的半导体封装，其中所述抛光停止层包括介电层或钝化层。
15.根据权利要求1所述的半导体封装，其中所述第二RDL结构进一步包括焊垫，且其中所述多个第一连接件形成于所述第二RDL结构的各个焊垫之上。
16.根据权利要求1所述的半导体封装，其进一步包括在所述第二RDL结构的所述第一侧上形成的防焊层，且其中所述多个第一连接件经由开口形成于所述防焊层中。
17.一种半导体封装，其包括：
第一重布层(RDL)结构，其由模塑料环绕；
第二RDL结构，其安置于所述第一RDL结构上且与所述第一RDL结构电连接；
多个第一连接件，其安置于所述第二RDL结构的第一侧上，所述第二RDL结构的第一侧与在所述第一RDL结构上安置的所述第二RDL结构的第二侧相对；
抛光停止层，其安置于所述第一RDL结构的第一侧上，所述第一RDL结构的第一侧与所述第二RDL结构在其上安置的所述第一RDL结构的第二侧相对，其中所述抛光停止层包括多个开口；
多个第二连接件，其经由所述第一RDL结构的所述第一侧形成于所述第一RDL结构中且形成于所述抛光停止层的所述多个开口中；以及
半导体晶粒，其安装于至少一个第二连接件之上。
18.根据权利要求17所述的半导体封装，其中所述多个第一连接件为BGA球，且具有与母板或印刷电路板(PCB)上的球垫间距匹配的球间距。
19.根据权利要求17所述的半导体封装，其中所述多个第二连接件为微凸块且具有与所述半导体晶粒的主表面上的输出/输入(I/O)垫间距匹配的细间距。
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Families Citing this family (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10085352B2 (en) 2014-10-01 2018-09-25 Qorvo Us, Inc. Method for manufacturing an integrated circuit package
US10773952B2 (en) 2016-05-20 2020-09-15 Qorvo Us, Inc. Wafer-level package with enhanced performance
US10468329B2 (en) 2016-07-18 2019-11-05 Qorvo Us, Inc. Thermally enhanced semiconductor package having field effect transistors with back-gate feature
US10784149B2 (en) 2016-05-20 2020-09-22 Qorvo Us, Inc. Air-cavity module with enhanced device isolation
CN109716511A (zh) 2016-08-12 2019-05-03 Qorvo美国公司 具有增强性能的晶片级封装
EP3497719B1 (en) 2016-08-12 2020-06-10 Qorvo Us, Inc. Wafer-level package with enhanced performance
SG11201901194SA (en) 2016-08-12 2019-03-28 Qorvo Us Inc Wafer-level package with enhanced performance
US10109502B2 (en) 2016-09-12 2018-10-23 Qorvo Us, Inc. Semiconductor package with reduced parasitic coupling effects and process for making the same
US10749518B2 (en) 2016-11-18 2020-08-18 Qorvo Us, Inc. Stacked field-effect transistor switch
US10068831B2 (en) 2016-12-09 2018-09-04 Qorvo Us, Inc. Thermally enhanced semiconductor package and process for making the same
US10755992B2 (en) * 2017-07-06 2020-08-25 Qorvo Us, Inc. Wafer-level packaging for enhanced performance
US10366972B2 (en) 2017-09-05 2019-07-30 Qorvo Us, Inc. Microelectronics package with self-aligned stacked-die assembly
US10784233B2 (en) 2017-09-05 2020-09-22 Qorvo Us, Inc. Microelectronics package with self-aligned stacked-die assembly
US11152363B2 (en) 2018-03-28 2021-10-19 Qorvo Us, Inc. Bulk CMOS devices with enhanced performance and methods of forming the same utilizing bulk CMOS process
US10804246B2 (en) 2018-06-11 2020-10-13 Qorvo Us, Inc. Microelectronics package with vertically stacked dies
KR102551034B1 (ko) 2018-09-07 2023-07-05 삼성전자주식회사 반도체 패키지 및 그 제조방법
US11069590B2 (en) 2018-10-10 2021-07-20 Qorvo Us, Inc. Wafer-level fan-out package with enhanced performance
US10964554B2 (en) 2018-10-10 2021-03-30 Qorvo Us, Inc. Wafer-level fan-out package with enhanced performance
US11646242B2 (en) 2018-11-29 2023-05-09 Qorvo Us, Inc. Thermally enhanced semiconductor package with at least one heat extractor and process for making the same
US11387157B2 (en) 2019-01-23 2022-07-12 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US20200235040A1 (en) 2019-01-23 2020-07-23 Qorvo Us, Inc. Rf devices with enhanced performance and methods of forming the same
US20200235066A1 (en) 2019-01-23 2020-07-23 Qorvo Us, Inc. Rf devices with enhanced performance and methods of forming the same
KR20210129656A (ko) 2019-01-23 2021-10-28 코르보 유에스, 인크. Rf 반도체 디바이스 및 이를 형성하는 방법
KR20210009762A (ko) 2019-07-18 2021-01-27 삼성전자주식회사 팬-아웃 웨이퍼 레벨 패키지 제조 방법
TWI739142B (zh) * 2019-08-12 2021-09-11 力成科技股份有限公司 半導體封裝結構及其製造方法
CN111128751B (zh) * 2019-10-25 2022-02-25 桂林电子科技大学 中介层的制造方法
US11646289B2 (en) 2019-12-02 2023-05-09 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US11923238B2 (en) 2019-12-12 2024-03-05 Qorvo Us, Inc. Method of forming RF devices with enhanced performance including attaching a wafer to a support carrier by a bonding technique without any polymer adhesive
KR20210111003A (ko) 2020-03-02 2021-09-10 삼성전자주식회사 반도체 패키지
CN111554641A (zh) * 2020-05-11 2020-08-18 上海天马微电子有限公司 半导体封装件及其制作方法
CN111430313A (zh) * 2020-05-11 2020-07-17 上海天马微电子有限公司 半导体封装及其制作方法
CN113035825A (zh) * 2021-02-02 2021-06-25 日月光半导体制造股份有限公司 半导体封装结构及其形成方法
WO2024077035A1 (en) 2022-10-04 2024-04-11 Enertia Microsystems Inc. Vibratory gyroscopes with resonator attachments

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103050486A (zh) * 2011-10-17 2013-04-17 台湾积体电路制造股份有限公司 形成封装堆叠结构的工艺
CN105047651A (zh) * 2014-04-30 2015-11-11 台湾积体电路制造股份有限公司 3d堆叠芯片封装件

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8604600B2 (en) * 2011-12-30 2013-12-10 Deca Technologies Inc. Fully molded fan-out
US9484319B2 (en) 2011-12-23 2016-11-01 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming extended semiconductor device with fan-out interconnect structure to reduce complexity of substrate
US9721862B2 (en) * 2013-01-03 2017-08-01 STATS ChipPAC Pte. Ltd. Semiconductor device and method of using a standardized carrier to form embedded wafer level chip scale packages
US9711379B2 (en) 2014-04-30 2017-07-18 Taiwan Semiconductor Manufacturing Company, Ltd. 3D stacked-chip package
US9799622B2 (en) 2014-06-18 2017-10-24 Dyi-chung Hu High density film for IC package
US9941207B2 (en) * 2014-10-24 2018-04-10 STATS ChipPAC Pte. Ltd. Semiconductor device and method of fabricating 3D package with short cycle time and high yield
US9899285B2 (en) * 2015-07-30 2018-02-20 Semtech Corporation Semiconductor device and method of forming small Z semiconductor package

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103050486A (zh) * 2011-10-17 2013-04-17 台湾积体电路制造股份有限公司 形成封装堆叠结构的工艺
CN105047651A (zh) * 2014-04-30 2015-11-11 台湾积体电路制造股份有限公司 3d堆叠芯片封装件

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