TWI767082B - 用於形成半導體裝置之後柱方法及半導體裝置 - Google Patents

用於形成半導體裝置之後柱方法及半導體裝置 Download PDF

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TWI767082B
TWI767082B TW107138485A TW107138485A TWI767082B TW I767082 B TWI767082 B TW I767082B TW 107138485 A TW107138485 A TW 107138485A TW 107138485 A TW107138485 A TW 107138485A TW I767082 B TWI767082 B TW I767082B
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substrate
conductive
conductive material
semiconductor device
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TW201937658A (zh
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安尼庫瑪 查杜魯
韋恩 Ｈ 黃
沙彌爾 Ｓ 維哈卡
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美商美光科技公司
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Abstract

本文中揭示具有用一導電材料填充之一或多個通孔之半導體裝置。在一項實施例中，一半導體裝置包含一半導體基板，該半導體基板具有一第一側、接近該第一側之複數個電路元件及與該第一側相對之一第二側。一通孔可延伸在該第一側與該第二側之間，且該通孔中之一導電材料可延伸超過該基板之該第二側以界定該導電材料之一突出部分。該半導體裝置可具有形成在該第二側上方且圍繞該導電材料之該突出部分之一高導電柱及形成在該第一側上方且電耦合至該通孔中之該導電材料之一短導電墊。

Description

用於形成半導體裝置之後柱方法及半導體裝置
本技術大體上係關於具有矽穿孔(TSV)之半導體裝置，且更特定言之係關於用於製造具有電耦合至TSV之導電柱之半導體裝置之系統及方法。
在半導體處理中，矽穿孔(TSV)往往用於提供相鄰半導體晶粒之間之電連接。TSV之製造涉及將深孔蝕刻至一半導體基板之一前側中，且用諸如銅之一導電填充物來填充所得孔。通常接著將導電柱形成為電耦合至基板之前側處之TSV之導電填充物，且基板自其後側薄化直至曝露導電填充物。接著，在基板之後側處之TSV之曝露導電材料上方形成凸塊下金屬(UBM)構件。
更特定言之，圖1A至圖1G係圖解說明根據先前技術之製造一半導體裝置100之一方法中之各個階段之橫截面視圖。如圖1A中展示，半導體裝置100包含一基板102，基板102具有一前側107、與前側相對之一後側109、及前側107中及/或上之複數個電路元件104(例如，電線、跡線、互連件、電晶體等)。舉例而言，金屬跡線可形成在基板102之前側107上，而積體電路元件可定位於基板102中金屬跡線下方。圖1A進 一步展示在TSV 106已形成於基板102中之後的半導體裝置100。特定言之，TSV自前側107延伸至基板102中但無法在後側109處接達。可使用此項技術中之熟知程序來形成TSV 106。舉例而言，可藉由在基板102中形成孔且用一導電材料105填充孔而製造TSV。
圖1A進一步展示在導電柱108已形成在基板102之前側107上以電耦合至TSV 106之對應者之導電材料105之後的半導體裝置100。導電柱108係具有在基板102之前側107上方約10μm至100μm之間(例如，約35μm至60μm之間)之一高度的相對較高結構。如此項技術中所熟知，可藉由一適合電鍍或無電式電鍍程序製造導電柱108。在其他實施例中，可使用其他沈積技術(例如，濺鍍沈積)來代替電鍍或無電式電鍍。
圖1B展示在基板102已經由一黏著層112附接至一載體110(例如，矽載體)之後的半導體裝置100。載體110可用於貫穿基板102之後側109上之中間處理步驟而提供額外穩定性，且隨後可連同黏著層112一起被移除。如圖1B中展示，黏著層112具有大於導電柱108之高度之一厚度且因此可形成為完全包圍導電柱108。相應地，黏著層112可具有約10μm至100μm之間(例如，約35μm至60μm之間)之一厚度。如圖1B中展示，藉由相對較厚黏著層112對載體110施加之力可導致載體110翹曲。特定言之，由黏著層112賦予之黏著力可導致載體110翹曲使得載體110之一後側119實質上非共面。在可對基板102之後側109實行進一步處理步驟之前，載體110必須經平坦化以(舉例而言)允許在隨後處理階段期間精確處置及對準載體110(及附接至其之半導體裝置100)。相應地，圖1C圖解說明在載體110之後側119已經平坦化為大致共面之後的載體110及半導體裝置100。
圖1D展示在基板102之後側109已經薄化以曝露穿過基板102之後側109之TSV 106之導電材料105之後的半導體裝置100。可使用(舉例而言)此項技術中已知之一適合背面研磨程序來薄化基板102。如圖1D中展示，在薄化基板102之後，TSV 106之導電材料105之一部分可突出超過基板102之後側109。
圖1E展示在一介電質層114已沈積在基板102之後側109上方及TSV 106之導電材料105之曝露部分上方之後的半導體裝置100。介電質層114可包括SiOx材料(例如，二氧化矽)、原矽酸四乙酯(TEOS)、其他氧化物材料等。如圖1F中展示，介電質層114及/或TSV 106之導電材料105之曝露部分隨後經薄化以共平坦化導電材料105之曝露部分及介電質層114。因此，在薄化之後，TSV 106之導電材料105及介電質層114一起界定半導體裝置100之一平坦後側115。通常使用一化學機械平坦化(CMP)程序來達成薄化。
圖1G展示在UBM構件116已形成在半導體裝置100之後側115上以電耦合至TSV 106之對應者之導電材料105之後的半導體裝置100。相較於導電柱108，UBM構件116係相對較短構件，其具有在半導體裝置100之後側115上方約1μm至10μm之間(例如，約1μm至5μm之間)之一高度。如此項技術中所熟知，可藉由一適合電鍍或無電式電鍍程序製造導電柱108。在其他實施例中，可使用其他沈積技術(例如，濺鍍沈積)來代替電鍍或無電式電鍍。圖1G進一步圖解說明(i)在已移除載體110及黏著層112(圖1F)之後且(ii)在將焊球或焊錫凸塊118沈積至導電柱108上之後的半導體裝置100。舉例而言，一模板印刷機器可將離散焊錫膏塊沈積至導電柱108上且接著可使焊錫膏回熔以在導電柱108上形成焊球118。
應注意，參考圖1A至圖1G圖解說明之先前技術程序之一個缺點係在移除載體110之後，無法在隨後處理階段中(例如，在製造另一半導體裝置100期間)重用載體110。特定言之，由於載體110必須經平坦化(圖1C)以解決由黏著層112導致之翹曲(圖1B)，故載體110不適合用於許多額外半導體製程中。
在一實施例中，一種半導體裝置包括：一基板，其具有一第一側、接近該第一側之複數個電路元件及與該第一側相對之一第二側；一通孔，其自該第一側延伸穿過該基板至該第二側；一導電材料，其在該通孔中且具有延伸超過該基板之該第二側之一突出部分；一導電墊，其在該第一側上且電耦合至該導電材料；及一導電柱，其在該第二側上至少部分包圍該導電材料之該突出部分且電耦合至該導電材料。
在另一實施例中，使用一種製造一半導體裝置之方法。該方法包括：在一基板之一第一側上形成導電墊且將該等導電墊電耦合至部分延伸穿過基板之通孔之導電材料；自基板之一第二側移除材料使得通孔之導電材料突出超過基板之第二側以界定導電材料之突出部分；及在基板之第二側上且至少部分圍繞導電材料之突出部分形成導電柱。
在另一實施例中，一種半導體裝置包括：一基板，其具有一前側、該前側處之複數個電路元件及與該前側相對之一後側；矽穿孔(TSV)，其等在該基板中，該等TSV包含延伸穿過該基板之一導電材料；第一導電結構，其等在該基板之該前側上且電耦合至該等TSV，其中該等第一導電結構具有該基板之該前側上方小於約10μm之一高度；及第二導電結構，其等在該基板之該後側上且電耦合至該等TSV，其中該等第二導 電結構具有該基板之該後側上方約30μm至100μm之間之一高度。
100:半導體裝置
102:基板
104:電路元件
105:導電材料
106:矽穿孔(TSV)
107:前側
108:導電柱
109:後側
110:載體
112:黏著層
114:介電質層
115:後側
116:凸塊下金屬(UBM)構件
118:焊球
119:後側
200:半導體裝置
201:半導體裝置/半導體晶粒
202:基板
204:電路元件
205:導電材料
206:矽穿孔(TSV)
207:前側
208:導電柱
209:後側
210:載體
211:突出部分
212:黏著層
216:導電墊
218:導電構件
219:載體之後側
220:單粒化道
303:堆疊
330:半導體裝置總成
340:封裝基板
342:電連接體
350:模製材料
400:系統
402:處理器
404:記憶體
405:輸入/輸出裝置
408:子系統或組件
H1:高度/距離
H2:高度/距離
H3:高度/距離
參考以下圖式可更佳地理解本發明技術之許多態樣。圖式中之組件不一定按比例繪製。代替地，強調清楚地圖解說明本發明技術之原理。
圖1A至圖1G係圖解說明根據先前技術之製造一半導體裝置之一方法中之各個階段之橫截面視圖。
圖2A至圖2F係圖解說明根據本發明技術之實施例之製造一半導體裝置之一方法中之各個階段之橫截面視圖。
圖3係根據本發明技術之實施例之一半導體裝置總成之一橫截面視圖。
圖4係根據本發明技術之實施例之包含一半導體裝置之一系統之一示意圖。
下文中描述用於製造半導體裝置之方法及相關系統及方法之數項實施例之具體細節。熟習相關技術者將認知，可在晶圓級或晶粒級執行本文中描述之方法之適合階段。因此，取決於使用術語「基板」之內容背景，術語「基板」可指代一晶圓級基板或指代一單粒化晶粒級基板。此外，除非內容背景另有指示，否則可使用習知半導體製造技術來形成本文中揭示之結構。可(舉例而言)使用化學氣相沈積、物理氣相沈積、原子層沈積、旋塗及/或其他適合技術來沈積材料。類似地，可(舉例而言)使用電漿蝕刻、濕式蝕刻、化學機械平坦化或其他適合技術來移除材料。熟習相關技術者亦將瞭解，本技術可具有額外實施例，且可在無下文中參考圖 2A至圖4描述之實施例之數個細節之情況下實踐本技術。
在下文中描述之數項實施例中，製造具有TSV之一半導體裝置之一方法包含在半導體裝置之一基板之一前側上形成凸塊下金屬(UBM)構件且將UBM構件電耦合至TSV之對應者。基板可具有接近前側之作用電路元件。方法可進一步包含使用一薄黏著層來將一載體晶圓附接至基板之前側及隨後薄化基板之一後側以顯露TSV。方法亦可包含在TSV之曝露部分上及/或周圍直接形成比UBM構件高的導電柱。接著，可使載體與基板解耦合且在額外半導體製程中重用載體。
相對於在基板之前側上形成較高導電柱(例如，如在參考圖1A至圖1G圖解說明之習知方法中)，在基板之前側上形成UBM結構使一較薄黏著層能夠用於將半導體裝置耦合至載體。預期較薄黏著層將不導致載體之明顯翹曲且因此在對基板之後側實行之處理階段之前無需平坦化載體。相應地，可在後續半導體製程中重用載體，從而降低利用載體之半導體製程之成本。另外，在一些實施例中，導電柱可具有明顯大於TSV之曝露部分之體積的一體積。因此，在形成導電柱之前無需平坦化或其他薄化步驟，從而進一步降低製造成本。
如本文中使用，術語「垂直」、「橫向」、「上」及「下」可指代半導體裝置中之構件鑑於圖中展示之定向之相對方向或位置。舉例而言，「上」或「最上」可指代與另一構件相比，定位為更接近一頁面之頂部之一構件。然而，此等術語應廣泛解釋為包含具有其他定向(諸如顛倒或傾斜定向)之半導體裝置，其中頂部/底部、上方/下方、之上/之下、上/下及左/右可取決於定向而互換。
圖2A至圖2F係圖解說明根據本發明技術之實施例之製造一 半導體裝置200之一方法中之各個階段之橫截面視圖。通常，一半導體裝置可製造(舉例而言)為一離散裝置或製造為一較大晶圓或面板之部分。在晶圓級或面板級製造中，一較大半導體裝置係在經單粒化以形成複數個個別裝置之前形成。為方便說明及理解，圖2A至圖2F圖解說明可單粒化為兩個個別半導體裝置(例如，半導體晶粒)201(圖2F)之半導體裝置200之製造。然而，熟習此項技術者將容易理解，半導體裝置200之製造可經按比例調整為晶圓及/或面板級，即，包含更多組件以便能夠單粒化為兩個以上半導體裝置201，同時包含與本文中描述類似之構件且使用類似程序。
如圖2A中展示，半導體裝置200可包含一基板(例如，矽基板)202，其具有一前側207、與前側207相對之一後側209及前側207中及/或上之複數個電路元件(例如，一作用層)204。舉例而言，電路元件204可包含電線、跡線、互連件、電晶體等。在一些實施例中，金屬跡線可形成於基板202之前側207上，而積體電路元件可定位於基板202中金屬跡線下方。電路元件204可包含(舉例而言)一記憶體電路(例如，一動態隨機記憶體(DRAM))、一控制器電路(例如，一DRAM控制器)、一邏輯電路及/或其他電路。
圖2A進一步展示在一或多個矽穿孔(TSV)206已形成於基板202中之後的半導體裝置200。特定言之，TSV 206自前側207延伸至基板202中但無法在後側209處接達(例如，TSV 206不在後側209處自基板202曝露或顯露)。TSV 206可包含電耦合至電路元件204之一導電材料205，且可使用此項技術中之熟知程序來形成。舉例而言，可藉由形成(例如，蝕刻)穿過基板202之前側207之孔且用導電材料205填充孔而製造TSV 206。用於形成孔之程序可包含一光微影程序，接著一或多個濕式及/或乾式化學蝕刻程序。導電材料205可包括銅、鎳、焊錫(例如，基於SnAg之焊錫)、導體填充環氧樹脂及/或其他導電材料。在一些實施例中，TSV 206可包含安置於導電材料205與周圍基板202之間之一障壁材料及/或其他材料。
圖2A進一步展示在導電墊(例如，UBM構件)已形成在基板202之前側207上方以電耦合至TSV 206之對應者之導電材料205之後的半導體裝置200。在一些實施例中，導電墊216具有在基板202之前側207上方約1μm至10μm之間(例如，約1μm至5μm之間，小於約5μm等)之一高度H1(例如，延伸超過基板202之前側207一距離H1)。可藉由一適合電鍍或無電式電鍍程序或使用其他適合沈積技術(例如，濺鍍沈積)來製造導電墊216。導電墊216可包括銅、鎳、鋁焊錫(例如，基於SnAg之焊錫)、導體填充環氧樹脂及/或其他導電材料，且可包括相同或不同導電材料之一或多個層。舉例而言，在某些實施例中，導電墊包括(i)具有約2μm之一厚度(例如，在前側207上方之高度)之鎳之一第一層及(ii)在第一層上且具有約0.1μm之一厚度之鋁之一第二層。在其他實施例中，導電墊216可係形成(例如，沈積)於基板202之前側207上之一晶種層之一部分。舉例而言，晶種層可係焊錫可潤濕使得無需一單獨鍍覆程序來形成導電墊216。在此等實施例中，導電墊216可具有約0.1μm至1μm之間之一厚度。
圖2B展示在基板202已經由一黏著層212附接至一載體210之後的半導體裝置200。在載體210隨後自基板202解耦合(例如，釋放、移除等)之前，載體210可為基板202之後側209上之後續處理階段提供機 械支撐。載體210可係由(例如)矽、絕緣體上覆矽、化合物半導體(例如，氮化鎵)、玻璃或其他適合材料形成之一臨時載體。黏著層212可係將載體210固定至基板202之前側207及/或導電墊216之一次性膜(例如，環氧基材料之一層壓膜)或其他適合材料。
如圖2B中展示，黏著層212可具有大於導電墊216之高度H1之一厚度且因此可形成為完全或部分包圍導電墊216。相應地，在某些實施例中，黏著層212可具有約1μm至30μm之間(例如，約5μm至10μm之間、約10μm至20μm之間等)之一厚度。相較於參考圖1A至圖1G圖解說明之習知方法，黏著層212之總體積可減小，此係因為黏著層212可具有等於或僅略微大於形成於基板202之前側207上之相對較短導電墊216之一厚度。在一些實施例中，黏著層212足夠薄(例如，具有一足夠小的體積)使得由黏著層212賦予之任何黏著力未導致載體210、基板202及/或半導體裝置200之其他組件之明顯翹曲。舉例而言，在一些實施例中，載體210可包含一後側219，其在經由黏著層212將載體210耦合至基板202之後保持大致共面。相應地，在對基板202之後側209實行之後續處理步驟之前無需平坦化載體210之後側219。另外，降低在載體210耦合至半導體裝置200或隨後自半導體裝置200解耦合時黏著層212損壞基板202或導電墊216的風險。
圖2C展示在基板202之後側209已經薄化以曝露穿過基板之後側209之TSV 206之導電材料205之後的半導體裝置200。可使用(舉例而言)此項技術中已知之一適合背面研磨程序來薄化基板202。如圖2C中展示，在薄化基板202之後，TSV 206之各者中之導電材料205之一突出部分211可突出超過基板202之後側209。在一些實施例中，TSV 206之各者 中之導電材料205之突出部分211可具有在基板202之後側209上方約1μm至10μm之間(例如，小於約2μm，小於約5μm等)之一高度H2(例如，可延伸超過基板202之後側209一距離H2)。在某些實施例中，高度H2係約4μm。在一些實施例中，高度H2對於突出部分211之各者而言大致相同，而在其他實施例中，突出部分211之高度H2可改變。舉例而言，用於顯露TSV 206之導電材料205之背面研磨程序可在某些區域中對基板202之後側209過度拋光及/或拋光不足使得導電材料205不均勻地顯露。此外，在一些實施例中，導電材料205在背面研磨之後未突出超過基板202之後側209。舉例而言，在此等實施例中，基板202之後側209可與TSV 206之導電材料205之一上表面共面。
圖2D展示在導電柱208已形成在基板202之後側209上以電耦合至TSV 206之對應者之導電材料205之後的半導體裝置200。在圖2D中圖解說明之實施例中，導電柱208形成為包圍(例如，覆蓋)TSV中之導電材料205之突出部分211。在一些實施例中，導電柱208可僅部分包圍突出部分211(例如，安置成鄰近少於突出部分211之全部側及/或鄰近少於突出部分211之一總表面積)。在其中導電材料205未突出超過基板202之後側209之某些實施例中，導電柱208可形成在基板202之後側209處曝露之導電材料205之全部或一部分上方。
在一些實施例中，導電柱208具有在基板202之後側209上方約10μm至100μm之間(例如，約35μm至100μm之間，約35μm至60μm之間等)之一高度H3(例如，延伸超過基板202之後側209一距離H3)。應注意，導電柱208可實質上高於導電墊216。舉例而言，在一些實施例中，高度H3可比高度H1大至少約四倍。在其他實施例中，高度H3可比高 度H1大約一倍、九倍等。可藉由一適合電鍍或無電式電鍍程序或使用其他適合沈積技術(例如，濺鍍沈積)來製造導電柱208。導電柱208可包括銅、鎳、鋁焊錫(例如，基於SnAg之焊錫)、導體填充環氧樹脂及/或其他導電材料，且可包括相同或不同導電材料之一或多個層。在一些實施例中，導電柱208包含適於促成一鍍覆程序之一或多個晶種層。
應注意，導電柱208之體積可實質上比導電材料205之突出部分211之體積大(例如，約一倍、四倍、九倍等)，此係因為導電柱208之高度H3(例如，實質上)比突出部分211之高度H2大，且在一些實施例中，導電柱208包圍突出部分211使得其等具有一更大(例如，實質上更大)橫向厚度。相應地，在一些實施例中，可在突出部分211正上方及/或周圍製造導電柱208而無需任何中間步驟來平坦化突出部分211。即，降低TSV在薄化程序(圖2C)期間「顯露」之程度之重要性，此係因為突出部分211之任何非平坦性、不規則性、可變性等由導電柱208之更大體積所包含(例如，補償)。舉例而言，相較於參考圖1A至圖1G圖解說明之習知方法，可製造半導體裝置200而不在基板202之後側209上形成一介電質或其他層，且因此未隨後薄化(例如，經由一化學機械平坦化(CMP)程序)介電材料及/或導電材料205以形成半導體裝置200之一平坦後側表面。因此，在一些實施例中，半導體裝置200不包含導電柱208與基板202之間之一介電質層，且導電柱208直接接觸突出部分211及基板202。同樣地，在一些實施例中，突出部分211並非共面。相較於(舉例而言)習知程序，預期此等平坦化及/或介電質沈積階段之省略降低製造成本。
圖2E圖解說明在已移除載體210及黏著層212(圖2D)之後的半導體裝置200。在一些實施例中，黏著層212允許載體210經由一真 空、烙製針(poker pin)、雷射或其他光源或其他適合方法自半導體裝置200容易地移除使得可再次重用載體210。移除載體210及黏著層212曝露基板202之前側207及導電墊216。
圖2E進一步圖解說明在導電構件(例如，焊球或焊錫凸塊)218已沈積至(例如，形成於)導電柱208上之後的半導體裝置200。舉例而言，一模板印刷機器可將離散焊錫膏塊沈積至導電柱208上且接著可使焊錫膏回熔以在導電柱208上形成焊球或焊錫凸塊。如圖2E中進一步展示，可沿著半導體裝置200提供單粒化道220以(舉例而言)促成半導體裝置200單粒化為複數個較小半導體裝置(例如，半導體晶粒)。相應地，圖2F展示在經單粒化以形成兩個半導體晶粒201之後之半導體裝置200。明確言之，基板202可在單粒化道220(圖2E)處切割以將半導體晶粒201彼此分離。一旦單粒化，個別半導體晶粒201便可經由導電構件218及/或經由導電墊216附接至外部電路(例如，相同半導體晶粒)，且因此併入至大量系統及/或裝置中。
舉例而言，圖3係根據本發明技術之實施例之一半導體裝置總成330(「總成330」)之一橫截面視圖。總成330包含以一堆疊303配置於一封裝基板340上的複數個半導體晶粒201(圖2F)。在圖3中圖解說明之實施例中，總成330包含配置成一「前至後」組態的四個半導體晶粒201(例如，半導體晶粒201之前作用側207面向半導體晶粒201之一鄰近者之後側209)。應注意，在圖3中圖解說明之實施例中，半導體晶粒201經配置使得各半導體晶粒201之前側207背對封裝基板340，而導電柱208自各半導體晶粒201之後側209延伸朝向封裝基板340。實務上，總成330可包含不同數目個半導體晶粒201，諸如一個晶粒、兩個晶粒、三個晶粒、五 個晶粒、八個晶粒、十六個晶粒或更多。同樣地，半導體晶粒201可具有其他適合定向，諸如「前至前」。在一些實施例中，半導體晶粒201可係相同的(例如，製造為具有相同設計及規格之記憶體晶粒)，而在其他實施例中，半導體晶粒201可彼此不同(例如，不同類型之記憶體晶粒或控制器、邏輯、記憶體及/或其他晶粒之一組合)。舉例而言，在一些實施例中，最上半導體晶粒201不包含TSV。在其他實施例中，最上半導體晶粒201可包含在後側209處未顯露之TSV，且可經定向使得前側207面向堆疊303中之下半導體晶粒201。
舉例而言，在一項實施例中，頂部晶粒可係無TSV之一晶粒，或可係其中TSV未藉由定向其使得作用表面向下而顯露之一晶粒，不同於圖3中所展示。
封裝基板340可包含一重佈層、一插入器、一印刷電路板、一介電間隔件、另一半導體晶粒(例如，一邏輯晶粒)或另一適合基板。封裝基板340可進一步包含電耦合至封裝基板340且經組態以將半導體晶粒201電耦合至外部裝置或電路(未展示)的電連接體342(例如，焊球、導電凸塊、導電柱、導電環氧樹脂及/或其他適合導電元件)。如圖3中進一步展示，一模製材料350可形成在封裝基板340上方且至少部分圍繞(例如，囊封)半導體晶粒201以保護半導體晶粒201及/或總成330之其他組件使之免受可損壞半導體晶粒201之外部污染物或力的影響。
具有上文中參考圖2A至圖3描述之構件之半導體裝置之任一者可併入至大量更大及/或更複雜系統之任一者中，系統之一代表性實例係圖4中示意性地展示之系統400。系統400可包含一處理器402、一記憶體404(例如，SRAM、DRAM、快閃記憶體及/或其他記憶體裝置)、輸 入/輸出裝置405及/或其他子系統或組件408。上文中參考圖2A至圖3描述之半導體晶粒可包含於圖4中展示之元件之任一者中。所得系統400可經組態以執行廣泛多種適合運算、處理、儲存、感測、成像及/或其他功能之任一者。相應地，系統400之代表性實例包含(而不限於)電腦及/或其他資料處理器，諸如桌上型電腦、膝上型電腦、網際網路設備、手持式裝置(例如，掌上型電腦、可穿戴電腦、蜂巢式或行動電話、個人數位助理、音樂播放器等)、平板電腦、多處理器系統、基於處理器或可程式化消費型電子器件、網路電腦及微型電腦。系統400之額外代表性實例包含燈、相機、運載工具等。關於此等及其他實例，系統400可容置於一單一單元中或分佈於多個互連單元(例如，透過一通信網路)上。系統400之組件可相應地包含本端及/或遠端記憶體儲存裝置及廣泛多種適合電腦可讀媒體之任一者。
自前述內容，將瞭解，本文中已出於圖解之目的描述本技術之特定實施例，但可作出各種修改而不偏離本發明。因此，本發明除如藉由隨附發明申請專利範圍限制外並不受限。此外，在其他實施例中亦可組合或消除在特定實施例之內容背景中描述之新技術之特定態樣。此外，儘管已在新技術之某些實施例之內容背景中描述與彼等實施例相關之優點，然而其他實施例亦可展現此等優點且並非全部實施例需要展現此等優點以落在本技術之範疇內。因此，本發明及相關技術可涵蓋本文中未明確展示或描述之其他實施例。
201:半導體裝置/半導體晶粒
202:基板
204:電路元件
207:前側
208:導電柱
209:後側
303:堆疊
330:半導體裝置總成
340:封裝基板
342:電連接體
350:模製材料

Claims (26)

  1. 一種半導體裝置，其包括：一基板，其具有一第一側、接近該第一側之複數個電路元件及與該第一側相對之一第二側；一通孔，其自該第一側延伸穿過該基板至該第二側；一導電材料，其在該通孔中且具有延伸超過該基板之該第二側之一突出部分；一導電墊，其在該第一側上且電耦合至該導電材料，其中該導電墊具有在該基板之該第一側上方小於約10μm之一高度；及一導電柱，其在該第二側上至少部分包圍該導電材料之該突出部分且電耦合至該導電材料，其中該導電柱具有在該基板之該第二側上方約30μm至100μm之間之一高度，其中該導電柱之一體積比該導電材料之該突出部分之一體積大至少九倍，且其中該基板不包含在該第二側上之一絕緣層。
  2. 如請求項1之半導體裝置，其中該導電墊之該高度介於約0.1μm至5μm之間。
  3. 如請求項1之半導體裝置，其中該導電柱之該高度介於約35μm至60μm之間。
  4. 如請求項1之半導體裝置，其中該導電柱完全包圍該導電材料之該突 出部分。
  5. 如請求項1之半導體裝置，其中該基板直接接觸該導電柱。
  6. 如請求項1之半導體裝置，其中該通孔係一第一通孔，其中該導電材料係一第一導電材料，其中該導電柱係一第一導電柱，且其進一步包括：一第二通孔，其自該第一側延伸穿過該基板至該第二側；一第二導電材料，其在該第二通孔中且具有延伸超過該基板之該第二側之一突出部分；及一第二導電柱，其在該第二側上至少部分包圍該第二導電材料之該突出部分且電耦合至該第二導電材料，其中該第一導電材料之該突出部分具有在該基板之該第二側上方之一第一高度，其中該第二導電材料之該突出部分具有在該基板之該第二側上方之一第二高度，且其中該第一高度不同於該第二高度。
  7. 如請求項1之半導體裝置，其中該導電材料之一表面實質上與該基板之該第一側共面。
  8. 一種製造一半導體裝置之方法，該方法包括：在一基板之一第一側上形成導電墊且將該等導電墊電耦合至部分延伸穿過該基板之通孔之導電材料，其中該等導電墊具有在該基板之該第一側上方小於約10μm之一高度；自該基板之一第二側移除材料使得該等通孔之該導電材料突出超過 該基板之該第二側以界定該導電材料之突出部分；及在該基板之該第二側上且至少部分圍繞該導電材料之該等突出部分之複數對應者(corresponding ones)形成導電柱，其中該等導電柱具有在該基板之該第二側上方約30μm至100μm之間之一高度，其中該等導電柱之複數個別者(individual ones)具有一體積比該導電材料之該等突出部分之該等對應者之一體積大至少九倍。
  9. 如請求項8之方法，其進一步包括：在形成該等導電墊之後，經由具有小於約30μm之一厚度之一黏著劑將一載體耦合至該基板之該第一側。
  10. 如請求項8之方法，其進一步包括：在形成該等導電墊之後，經由具有小於約10μm之一厚度之一黏著劑將一載體耦合至該基板之該第一側。
  11. 如請求項8之方法，其進一步包括：在形成該等導電墊之後，將一載體耦合至該基板之該第一側；及在形成該等導電柱之後，將該載體自該基板解耦合，其中在將該載體耦合至該基板之前且在自該基板移除該載體之後該載體具有相同厚度。
  12. 如請求項8之方法，其中形成該等導電墊包含將一導電墊材料至少部分鍍覆至(a)該基板之該第一側及(b)該等通孔之該導電材料上。
  13. 如請求項8之方法，其中形成該等導電柱包含將一導電柱材料至少部分鍍覆至(a)該基板之該第二側上及(b)該導電材料之該等突出部分周圍。
  14. 如請求項8之方法，其中該等導電柱之該高度比該等導電墊之該高度大至少四倍。
  15. 如請求項8之方法，其中在該基板之該第一側上形成該等導電墊包含在接近該基板之一作用區域處形成該等導電墊。
  16. 如請求項8之方法，其中在自該基板移除該材料之後，該導電材料之該等突出部分之一第一者具有在該基板之該第二側上方之一第一高度，且該等突出部分之一第二者具有在該基板之該第二側上方不同於該第一高度的一第二高度；且形成該等導電柱包含形成(a)圍繞該等突出部分之該第一者之該等導電柱之一第一者及(b)圍繞該等突出部分之該第二者之該等導電柱之一第二者。
  17. 如請求項8之方法，其中該基板係一半導體晶圓或面板，且其中該方法進一步包括切割該基板以形成個別半導體晶粒。
  18. 如請求項8之方法，其中該方法不包含平坦化該導電材料之該等突出部分。
  19. 如請求項8之方法，其進一步包括在形成該等導電墊之後將一載體耦合至該基板之該第一側，且其中該方法不包含平坦化該載體。
  20. 如請求項8之方法，其中該方法不包含在該基板之該第二側上形成一絕緣層。
  21. 一種半導體裝置，其包括：一基板，其具有一前側、該前側處之複數個電路元件及與該前側相對之一後側；矽穿孔(TSV)，其等在該基板中，該等TSV包含延伸穿過該基板之一導電材料，且其中該等TSV之該導電材料突出超過該基板之該後側以界定該等TSV之突出部分；第一導電結構，其等在該基板之該前側上且電耦合至該等TSV，其中該等第一導電結構具有在該基板之該前側上方小於約10μm之一高度；及第二導電結構，其等在該基板之該後側上且電耦合至該等TSV，其中該等第二導電結構具有在該基板之該後側上方約30μm至100μm之間之一高度，其中該等第二導電結構覆蓋對應TSV之該等突出部分，且其中該等第二導電結構之各者具有一體積，該體積比該等突出部分之一對應者之一體積大至少九倍。
  22. 如請求項21之半導體裝置，其中該等TSV之該等突出部分各具有在該基板之該後側上方小於約5μm之一高度。
  23. 如請求項21之半導體裝置，其中該等TSV之該等突出部分並非共面。
  24. 如請求項21之半導體裝置，其中該等第一導電結構係凸塊下金屬(UBM)結構。
  25. 如請求項21之半導體裝置，其中該等第一導電結構包括一晶種層。
  26. 如請求項21之半導體裝置，其中該基板不包含在該後側上方之一絕緣層。
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